JPH07201994A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide the construction and manufacturing method of a semiconductor device with which the etching of a contact hole having minute dimensions and a large aspect ratio can be realized with good reproducibility and uniformity. CONSTITUTION:When a contact hole 7 is formed through an SiO2 system interlayer insulating films 2 and 5 by etching, a wide dummy region 5a is also etched. An etching stopper layer pattern 3a is formed in the part of the interlayer insulating film positioned in the thickness direction beforehand in order not to expose a lower layer wiring 1 in the dummy region 5a. With the progress of the etching of the dummy region 5a, oxygen is released into the etching atmosphere. Therefore, the deposition of excessive CF system products is controlled and side wall protective films can be formed under optimum conditions. With this constitution, the contact hole having an excellent shape can be formed and, further, the particle contamination can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device including an interlayer insulating film having a connection hole which is fine and has a large aspect ratio and faces a lower wiring.

[0002]

2. Description of the Related Art As semiconductor device design rules such as LSI are miniaturized from a level of half micron to quarter micron, and a multi-layer wiring structure is frequently used, there is a demand for fine processing techniques such as photolithography and dry etching. It is getting more severe. In the field of dry etching, for example, since the opening diameter of a contact hole that opens in an interlayer insulating film is becoming finer and the aspect ratio is becoming higher, a new problem of a defective opening shape of the contact hole and an increase in contact resistance due to this Is causing.

Conventionally, SiO₂Dry etch of the system interlayer insulation film
In ching, CF_Four, CHF ₃Many CF-based gases
It has been used. This is because the C contained in the CF-based gas is Si.
O₂The C-O bond is generated on the surface of the layer and the Si-O bond is weakened.
Reaction product S with a high vapor pressure due to cleavage
iF_FourAnd CO, CO₂Etching progresses by forming
Etching gas and its resist
The deposition of CF type polymer which is a side reaction product with the mask
A machine for anisotropic etching that is used to form a wall protection film.
It is based on the structure. Deposition of CF-based polymers is usually
SiO that is the material layer to be etched₂Etching of interlayer insulating film
Due to the oxidation reaction by oxygen atoms released during ching,
Etching proceeds while being appropriately removed.

By the way, in recent years, as the opening diameter of the connection hole becomes finer, the area to be etched decreases, and the amount of released oxygen atoms tends to decrease. Therefore, the balance of the competitive reaction between the deposition and removal of the CF-based polymer is disturbed, and the connection hole etching has to be performed in the atmosphere in the etching chamber in which the CF-based polymer is excessive. This may reduce the reproducibility and uniformity of etching, or, in an extreme case, may stop etching of a high-aspect-ratio contact hole midway. In addition, this is also an unfavorable direction for particle contamination of the substrate to be etched and the inside of the etching chamber.

Therefore, a small amount of O ₂ gas is usually added to the CF-based gas to oxidize and remove the excess CF-based polymer to keep the balance of the competitive reaction and to optimize the deposition amount of the side wall protective film. According to this method, it is necessary in principle to adjust the added amount of O ₂ gas according to the opening ratio and the opening area of the resist mask each time the type of the substrate to be etched changes. Also, since an oxidizing gas is added,
The etching selectivity with respect to the resist mask is reduced, the resist film is reduced, and the problem of controllability of the connection hole opening diameter due to resist receding remains.

[0006]

SUMMARY OF THE INVENTION The object of the present invention is to prevent excessive CF-based polymer from being deposited when opening fine and high aspect ratio contact holes in an interlayer insulating film, and to improve uniformity and reproducibility. It is an object of the present invention to provide a semiconductor device capable of realizing high dry etching and a manufacturing method thereof.

Another object of the present invention is to realize dry etching which has a high selection ratio with respect to a resist mask and which does not require complicated flow rate ratio control of etching gas according to the aperture ratio and opening area of the resist mask. The present invention provides a semiconductor device having fine and high aspect ratio contact holes and a method of manufacturing the same.

Still another object of the present invention is to provide a semiconductor device having fine and high aspect ratio contact holes, which can prevent excessive deposition of CF type polymer and realize clean dry etching without fear of particle contamination. It is to provide the manufacturing method.

[0009]

The semiconductor device of the present invention comprises:
In order to solve the above-mentioned problems, in a semiconductor device including an interlayer insulating film having a connection hole facing a lower wiring layer, in a semiconductor device including a connection hole forming region, one portion in the thickness direction of the interlayer insulating film is provided. This structure employs a structure in which an etching stopper layer is provided in the part. As the interlayer insulating film, a SiO ₂ material layer, that is, SiO ₂ , or PSG, BSG, BP
The effect of the present invention is remarkably exhibited when a material containing oxygen such as SG or AsSG is selected and the opening diameter of the connection hole is 0.5 μm or less. As the etching stopper layer, Si
It may be selected from materials having an etching selection ratio with respect to the O ₂ based material layer, and for example, Si ₃ N ₄ or the like is preferable.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming the first interlayer insulating film and the etching stopper layer on the lower wiring layer, the step of removing the etching stopper layer in the connection hole forming region, and the second step. A step of forming an interlayer insulating film,
A step of forming a connection hole penetrating the first interlayer insulating film and the second interlayer insulating film and facing the lower wiring layer, and at the same time removing a part of the second interlayer insulating film on the etching stopper;
It is characterized by including and.

The term "connection hole forming region" as used herein means
It refers to the formation position of the connection hole and the periphery thereof, that is, the region including a region slightly wider than the connection hole. It is sufficient to allow for the alignment margin for forming the resist pattern, for example, to allow for this area to be about twice as large as the actual connection hole.

The lower wiring layer referred to in this specification means
Not only the lower layer wiring pattern but also a semiconductor substrate on which an active layer and the like are formed are included. Therefore, the connection hole in this specification includes both a contact hole and a via hole.

[0013]

The point of the present invention is that the second interlayer insulating film on the etching stopper is etched at the same time when the connection hole is etched, and a semiconductor device structure and a manufacturing method which can realize this are adopted. In point. Since the etching of the second interlayer insulating film on the etching stopper does not particularly relate to the device characteristics of the semiconductor device, it will be referred to as dummy region etching hereinafter.

Since the total area of the dummy region is much larger than the total area of the fine connection holes, a large amount of oxygen is generated with the etching of this region. This oxygen controls the deposition of CF-based polymer, which is a by-product of reaction, and prevents the formation of an excessive side wall protective film in the etching portion of the contact hole, so that uniform etching with excellent reproducibility becomes possible. Further, since there is no excessive CF-based polymer deposition, there is no concern that the particle level will deteriorate.

Since the etching of the dummy region is performed simultaneously with the etching of the connection hole, there is no concern that the etching process will be complicated. However, an etching stopper layer having a high etching selectivity with respect to the interlayer insulating film is provided so that the underlying wiring layer is not exposed.

[0016]

EXAMPLES Specific examples of the present invention will be described below.

Example 1 This example is an example in which the present invention is applied to a step of forming a contact hole in an interlayer insulating film of a Si substrate, which will be described with reference to FIG.

First, as shown in FIG. 1 (a), a first interlayer insulating film 2 made of SiO _{2 is} formed as a lower wiring layer 1 on a semiconductor substrate such as Si by a low pressure CVD method using O ₃ / TEOS. , The etching stopper layer 3 made of Si ₃ N ₄ is sequentially formed by the plasma CVD method using SiH ₄ / NH ₃ . The thicknesses of the first interlayer insulating film 2 and the etching stopper layer 3 are, for example, 500 nm and 100 nm, respectively. Illustration of the diffusion layer and the like formed on the semiconductor substrate is omitted.

Next, a resist pattern 4 having an opening diameter larger than that of the contact hole pattern, including the contact hole formation planned region, is formed. The opening diameter of the resist pattern 4 is 700 nm, for example.

The etching stopper layer 3 is patterned using the resist pattern 4 as a mask. For this etching, for example, Japanese Patent Application Laid-Open No. 62-
As disclosed in Japanese Patent No. 102530, CH ₂ F ₂ , C
A mixed gas of NF ₃ added to a CF-based gas having a small C / F ratio such as H ₃ F may be used to select an etching condition having a selection ratio with the underlying layer made of SiO ₂ , but the present invention is not limited to this. .

As a result, the etching stopper layer pattern 3a is left on the entire surface of the first interlayer insulating film 2 except for the contact hole formation planned region. Subsequently, after removing the resist, as shown in FIG. 1B, a second interlayer insulating film 5 is formed on the entire surface to a thickness of 600 nm as an example. The second interlayer insulating film 5 is also a low pressure CV using, for example, O ₃ / TEOS.
It is formed of SiO ₂ by the D method.

Next, as shown in FIG. 1C, an actual contact hole pattern is formed on the second interlayer insulating film 5.
A resist pattern 6 having a dummy region and an opening is newly formed. The opening pattern of the dummy area is formed in the area of the etching stopper layer pattern 3a left previously.
The opening pattern diameter of the contact hole is 0.3 as an example.
The diameter is 5 nm. The opening pattern of the dummy region is not particularly limited, but is, for example, 2 to 3 μm, and as described above, an area capable of sufficiently releasing oxygen is opened.

The processed substrate processed up to this point was set in an RF bias application type ECR plasma etching apparatus, and as an example, it was etched under the following conditions. C ₆ F ₆ 30 sccm Gas pressure 1.3 Pa Microwave power 1200 W (2.45 GHz) RF bias power 250 W (800 kHz) Substrate temperature 0 ° C. As proposed in the specification of 5-60755, C
By using ₆ F ₆ gas, 30 for Si ₃ N ₄
As described above, a selection ratio of 50 or more with respect to Si is obtained. Therefore, etching stops at the upper surface of the lower wiring layer 1 which is the Si substrate in the contact hole pattern portion and at the upper surface of the etching stopper layer pattern 3a which is Si ₃ N ₄ in the pattern portion of the dummy region, and the connection hole 7 and the dummy region 5a are formed. Is formed.

In this etching process, since the area to be etched is conventionally narrowed, oxygen is not released from the interlayer insulating film, and the shape of the connection hole deteriorates as the etching process progresses or as the number of etching processes increases. However, there is a risk that the etching may stop halfway. However, in this embodiment, the dummy etching region 5
By etching a at the same time, the amount of oxygen released increases, so that the deposition of excess side reaction products of CF-based polymer is controlled, and good opening of contact holes can be realized without such a concern.

Example 2 This example is an example in which the present invention is applied to processing a via hole on an Al alloy wiring layer as the lower wiring layer 1, and FIG.
Will be described with reference to.

As shown in FIG. 1 (a), Al-1% Si
The lower wiring layer 1 made of is formed by sputtering to have a thickness of, for example, 600 nm on a base insulating film (not shown), and processed into a desired wiring shape. Then, for example, O ₃ / TEOS /
First of PSG by low pressure CVD method using PH ₃
The inter-layer insulating film 2, the etching stopper layer 3 made of Si ₃ N ₄ and the resist pattern 4 are formed by the plasma CVD method. The opening diameter of the resist pattern 4 is formed to be larger than that of the via hole pattern, for example, to be 500 nm in the via hole formation planned region. As an example, the thicknesses of the first interlayer insulating film 2 and the etching stopper layer 3 are 400 nm and 80 nm, respectively.

The etching stopper layer 3 is patterned using the resist pattern 4 as a mask. As a result, the etching stopper layer pattern 3a is left on the entire surface of the first interlayer insulating film 2 except for the contact hole formation planned region. Subsequently, after removing the resist, a second interlayer insulating film 5 is formed on the entire surface to a thickness of 500 nm as an example, as shown in FIG. The second interlayer insulating film 5 is also made of, for example, O ₃
PSG by low pressure CVD method using / TEOS / PH ₃
To form.

Next, as shown in FIG. 1C, an actual contact hole pattern is formed on the second interlayer insulating film 5.
A resist pattern 6 having a dummy area opened is newly formed. The pattern of the dummy area is formed on the area of the etching stopper layer pattern 3a left previously. The opening pattern of the contact hole is, for example, 0.25 μm, and the opening pattern of the dummy region is not particularly limited here as well, but is, for example, 2 to 3 μm.

The substrate to be processed processed up to this point was set in an RF bias application type ECR plasma etching apparatus, and as an example, it was etched under the following conditions. C ₆ F ₆ 30 sccm Gas pressure 1.3 Pa Microwave power 1200 W (2.45 GHz) RF bias power 200 W (800 kHz) Substrate temperature 0 ° C. Under these etching conditions, etching proceeds by the same mechanism as in Example 1. Then, as shown in FIG. 1D, the via hole 7 and the dummy etching region 5a having a good shape were formed.

Although the present invention has been described with reference to the two examples, the present invention is not limited to these examples.

For example, although Si ₃ N ₄ is selected as the material of the etching stopper layer, the material is not limited to this, and any material having a selective ratio with the SiO ₂ -based interlayer insulating film may be selected. This etching stopper layer may be provided at any position in the thickness direction of the SiO ₂ -based interlayer insulating film. However, for the purpose of the present invention, it is more effective to receive the supply of oxygen from the dummy region during most of the etching of the connection hole 7. Therefore, it is preferable to provide it in the lower half of the interlayer insulating film. That is, it is more preferable to select the thickness of the second interlayer insulating film to be larger than the thickness of the first interlayer insulating film, but the effect of the present invention can be obtained without necessarily selecting such a position. Is.

The thickness of the etching stopper layer is 100 nm or 80 nm in this embodiment, but it may be thinner than this. It only has to remain as an etching mask until the etching of the connection hole 7 is completed, and the thickness can be appropriately selected depending on the etching conditions and the like.

[0033]

As is apparent from the above description, in the present invention, in the etching of the fine connection hole having a large aspect ratio, the dummy region is simultaneously etched in addition to the original connection hole, so that the excess CF is removed. It is possible to control the deposition of the system reaction product and optimize the formation of the sidewall protective film, and it is possible to form the contact hole etching having an excellent shape with good reproducibility and uniformity.

By adopting a structure in which an etching stopper layer is previously formed on a part of the dummy region in the thickness direction of the interlayer insulating film, the etching can be stopped here and the lower layer wiring is exposed. Can be reliably prevented.

Further, since it is not particularly necessary to add oxygen gas to the etching gas, it is possible to realize a stable dry etching process free from the complicated flow rate ratio control according to the substrate to be etched.

Furthermore, since excessive reaction products are not generated, it is possible to prevent contamination of particles in the substrate to be etched as well as contamination of the etching chamber, which contributes to the realization of a clean process.

Due to the above effects, it greatly contributes to a semiconductor device having an etching process for contact holes such as contact holes and via holes based on a fine design rule of the deep submicron class, and a manufacturing method thereof, and is industrially used. High value.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining Embodiments 1 and 2 to which the present invention is applied, in the order of steps, in which (a) shows a first wiring on a lower layer wiring.
(B) shows a state in which the interlayer insulating film and the etching stopper layer have been formed and a resist pattern having an opening including a connection hole forming region has been formed, and the etching stopper layer including the connection hole forming region has been removed. 2C is a state in which the interlayer insulating film is formed, FIG. 7C is a state in which a resist pattern is formed by opening the connection hole and the dummy region, and FIG. 9D is a state in which the connection region is opened and the dummy region is etched at the same time.

[Explanation of symbols]

 1 Lower wiring layer 2 First interlayer insulating film 3 Etching stopper layers 4, 6 Resist pattern 5 Second interlayer insulating film 5a Dummy etching region 7 Connection hole

Claims (4)

[Claims] 1. A semiconductor device including an interlayer insulating film having a connection hole facing a lower wiring layer, wherein an etching stopper layer is provided in a part of a thickness direction of the interlayer insulating film except the connection hole forming region. A semiconductor device characterized by the following. 2. The semiconductor device according to claim 1, wherein the interlayer insulating film is made of a SiO ₂ -based material layer. 3. The semiconductor device according to claim 1, wherein the connection hole has an opening diameter of 0.5 μm or less. 4. A step of forming a first interlayer insulating film and an etching stopper layer on a lower wiring layer, a step of removing the etching stopper layer in a connection hole forming region, a step of forming a second interlayer insulating film, Forming a connection hole that penetrates the first interlayer insulating film and the second interlayer insulating film and faces the lower wiring layer, and simultaneously removes the second interlayer insulating film on the etching stopper layer; A method of manufacturing a semiconductor device, comprising: