JPH0864580A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the generation of an aluminium crowning due to a sputtering readhesion of a base metal wiring in the case where a connection hole is opened in an interlayer insulating film on a metal wiring, such as an Al metal wiring. CONSTITUTION: An antireflection film 2 is kept formed on a metal wiring 1 and is used as an etching stopper at the time of opening of a connection hole 5 along with the intrinsic antireflection function of the film 2 at the time of a patterning of the wiring 1. The exposed part of the film 2 is removed with downflow plasma. Accordingly, as the energy of ions of the downflow plasma is small, the exposed metal wiring is never sputtered. In the case where the connection holes of different depths are simultaneously opened, the effect of the film 2 is large. It is also possible that resist masks 4 are simultaneously subjected to ashing with the downflow plasma.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a step of opening a fine connecting hole facing a metal wiring in an interlayer insulating film.

[0002]

2. Description of the Related Art As semiconductor device design rules such as LSI are miniaturized from a level of half micron to quarter micron, and a multi-layer wiring structure is frequently used, there is a demand for fine processing techniques such as photolithography and dry etching. It is getting more severe. This is no exception in the process of opening contact holes such as contact holes and via holes. Especially in recent years,
P (Chemical Mechanical Poli
Since the surface of the interlayer insulating film is flattened by the introduction of a global flattening process such as (shing), the thickness of the interlayer insulating film varies depending on the location.
A process of simultaneously opening connection holes having different depths is often used.

In the simultaneous opening process of the connecting holes having different depths, the shallow connecting holes are completely opened in the early stage of etching, and the deep connecting holes are continuously opened. Etching is inevitable. In particular, at the opening of the connection hole facing the lower layer metal wiring made of Al-based metal, spatter redeposition of the lower layer metal wiring due to overetching is formed on the side surface of the interlayer insulating film or the resist mask and remains even after the resist mask is removed. Remains as.

This problem will be described with reference to FIGS. 3 (a) to 3 (d). First, as shown in FIG. 3A, an interlayer insulating film 3 is formed on a metal wiring 1 made of Al-based metal or the like, and a resist mask 4 for opening a contact hole is further formed. Next, as shown in FIG. 3B, the connection hole 5 facing the metal wiring 1 is opened. This connection hole 5 is shown assuming a shallow connection hole among the plurality of connection holes in the substrate to be etched. Subsequently, when the step of opening a deep connection hole (not shown) is continued, the shallow connection hole 5 is exposed to excessive overetching exceeding 100%, and the surface of the metal wiring 1 exposed at the bottom of the connection hole 5 is removed. Sputtering is caused by ion bombardment, and spatter reattachments 6 adhere to the side surfaces of the connection hole 5 and the resist mask 4. This state is shown in FIG.
Shown in

When the resist mask 4 is ashed or peeled off, the spatter redeposition material 6 remains in a form protruding from the connection hole 5. This spatter reattachment 6 looks like a crown when observed by SEM, and is therefore called an aluminum crown. If the contact plug and the upper layer wiring are formed with the spatter reattachment 6 remaining, the step coverage of the upper layer wiring layer and the like deteriorates.

The spatter reattachment 6 is mainly composed of Al-based metal, so it can be removed by Cl-based gas.
At the same time, the metal wiring 1 is also etched, and there is a concern that after-corrosion may occur. Further, although it is possible to remove the spatter reattachment material 6 by a physical method such as a brush / scrubber or a spin processor, there is a risk of particle contamination,
The problem of process complexity remains. The problems of these conventional techniques are that the reliability of the device is lowered particularly in a semiconductor device having a fine connection hole having an opening diameter of 0.5 μm or less,
It was unacceptable.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems. When opening a connection hole facing a metal wiring, even if excessive over-etching is performed, an aluminum crown or the like is used. It is an object of the present invention to provide a method for manufacturing a semiconductor device without forming a reattachment by sputtering.

Another object of the present invention is to form a spatter reattachment such as an aluminum crown in a shallow connection hole facing a metal wiring when a plurality of fine connection holes having different depths are simultaneously opened. It is an object of the present invention to provide a method for manufacturing a semiconductor device without a problem.

Still another object of the present invention is to reduce step coverage of upper layer wiring, after-corrosion, due to spatter redeposition such as aluminum crown in the step of opening a fine connecting hole facing metal wiring. Is to provide a method of manufacturing a semiconductor device that solves problems such as deterioration of throughput due to complication of processes. Other problems of the present invention will be made clear by the description of the present specification and the accompanying drawings.

[0010]

The semiconductor device of the present invention comprises:
SUMMARY OF THE INVENTION In order to solve the above problems, in a method for manufacturing a semiconductor device, which includes a step of opening a connection hole facing the metal wiring in an interlayer insulating film on the metal wiring having an antireflection film, The hole opening step is characterized by including a first step of etching the interlayer insulating film using the antireflection film as an etching stopper and a second step of etching the antireflection film with downflow plasma. Is. It is one of the features of the present invention that the resist mask can be removed by ashing at the same time as the etching of the antireflection film in the second step.

As the interlayer insulating film used in the present invention, SiO
_2- based material layer, that is, SiO ₂ , or PSG, BS
G, BPSG, AsSG, etc. can be used. As the antireflection film formed on the metal wiring, TiON,
SiON, TiN, SiN, a-Si, SiC or the like can be used.

The contact hole opening step of the present invention is highly effective when used in the step of simultaneously opening contact holes having different depths on the same substrate to be etched. Similarly, the effect is large when used in the step of opening a connection hole having an opening diameter of 0.5 μm or less.

[0013]

The point of the present invention is to provide an antireflection film at the time of resist exposure for forming a metal wiring pattern on the metal wiring, and use this antireflection film as an etching stopper at the time of opening a connection hole, and then use a downflow etching apparatus Therefore, the antireflection film is removed by etching.

[0014] As is well known, CF _x ⁺ is an ionic main etchant of silicon oxide interlayer dielectric film including SiO _2, to form a C-O bond on the surface of SiO _2, SiO bond By weakening or cutting the radical, the reaction by the radical main etchant (F ^* ) is assisted, and SiF ₄ and C, which are reaction products with high vapor pressure, are assisted.
O and CO ₂ are desorbed and etching proceeds. On the other hand, S
On each of the above-described antireflection films having no i-O bond or few Si-O bonds, CF _x ⁺ itself polymerizes by plasma to deposit a CF-based polymer, and etching stops.

In the second step of etching the antireflection film, the incident ion energy due to the downflow plasma is small, at most about 20 eV, so that the metal wiring of the lower layer is not sputtered. If a mixed gas of an F-based gas and an oxidizing gas is used as the downflow plasma source at this time, the CF deposited at the same time as the etching of the antireflection film is performed.
In addition to removing the system polymer, the resist mask can be removed by ashing at the same time, which results in a high throughput process.

When a Ti-based material such as TiON is used for the antireflection film, T is used as a reaction product having a high vapor pressure.
It is necessary to form and etch TiO _x F _y which is an oxyfluoride of i. For this purpose, the downflow plasma using the above-described mixed gas of F-based gas and oxidizing gas is convenient.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. In the etching apparatus used in each of the following examples, a substrate bias application type ECR plasma etching apparatus and a downflow plasma etching apparatus are connected via a gate valve, and a substrate to be etched can be transported between both etching apparatuses. It is a thing. The substrate bias application type ECR plasma etching apparatus used for etching the interlayer insulating film is not limited to this type and may be a parallel plate type RIE apparatus or a magnetron RIE apparatus.

Example 1 This example is an example in which a connection hole facing the metal wiring is opened in an interlayer insulating film on the metal wiring having TiON as an antireflection film, which is shown in FIGS. ) Will be described. It should be noted that FIG.
The same components as those in (a) to (d) are designated by the same reference numerals.

First, an interlayer insulating film 3 made of SiO ₂ is formed on a metal wiring 1 made of Al-based metal such as Al-1% Si having an antireflection film 2 made of TiON on its upper surface. A resist mask 4 for opening the connection hole which is exposed is formed. The resist mask 4 has an opening diameter of 0.35 μm, for example, and is formed by a chemically amplified resist and excimer laser lithography. Antireflection film 2
Is for preventing exposure light from being reflected from the metal wiring layer when forming a resist mask (not shown) for patterning the metal wiring 1. Interlayer insulation film 3
Has been planarized by CMP, and its thickness is distributed between 0.5 μm and 1.0 μm, for example, corresponding to the structure of the base. In the portion where the connection hole is to be formed shown in FIG. 1A, the thickness of the interlayer insulating film 3 is assumed to be as thin as 0.5 μm.

The substrate to be etched shown in FIG. 1A was placed on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and the interlayer insulating film 3 was etched under the following conditions as an example. C ₄ F ₈ 45 sccm CH ₂ F ₂ 5 sccm Gas pressure 1 Pa Microwave power 1000 W (2.45 GHz) RF bias power 200 W (800 kHz) Substrate temperature 0 ° C. In this etching step, CH is a deposition gas. ₂ F ₂
As a result, the etching proceeds while the CF-based or CHF-based polymer is deposited on the substrate to be etched. These deposits are immediately sputtered out on the surface perpendicular to the ion incident direction, or are oxidized and removed by the supply of oxygen from the underlying SiO ₂ that is subjected to ion bombardment, but remain on the pattern side surface parallel to the ion incident direction. Then, a sidewall protection film (not shown) is formed, and anisotropic etching proceeds.

When the etching progresses and the surface of the antireflection film 2 is exposed, the supply of oxygen from this surface is small, so that the deposition becomes dominant, and the CF or CHF polymer is deposited and the etching stops. This state is shown in FIG.

On the other hand, the antireflection film 2 is not exposed at the opening portion of the connection hole in the thick region of the interlayer insulating film 3, and the etching is continued. Therefore, the antireflection film 2 in the region of the shallow interlayer insulating film 3 exposed earlier is continuously subjected to ion bombardment. However, since the metal wiring 1 is not directly subjected to ion bombardment due to the presence of the deposited polymer and the antireflection film thereunder, spatter reattachment of the metal wiring 1 does not occur even if overetching of more than 100% is performed.

In the subsequent second step, the substrate to be etched was transferred to a downflow plasma etching apparatus, and as an example, the exposed portion of the antireflection film 2 was removed under the following conditions. C ₄ F ₈ 20 sccm O ₂ 30 sccm Gas pressure 133 Pa Microwave power 1000 W (2.45 GHz) Substrate temperature 100 ° C. In this etching process, first, CF-based or CHF-based polymer deposited on the surface or side surface of the antireflection film is removed. Oxidation removed,
Next, the antireflection film 2 made of TiON has the effect of heating the substrate, forms oxyfluoride, and is easily removed to complete the connection hole 5. This state is shown in FIG.

The metal wiring 1 exposed at the bottom of the connection hole 5 is exposed to downflow plasma, but is not sputtered because the ion energy is 20 eV or less.

In the present embodiment, the antireflection film on the metal wiring is used as an etching stopper, and the antireflection film is removed by downflow plasma in the second step. Therefore, the surface of the metal wiring is subjected to sputtering. Never. Therefore, the aluminum crown does not occur even when a plurality of connection holes having different depths are simultaneously opened.

Example 2 This example is an example in which a connection hole facing the metal wiring is opened in an interlayer insulating film on the metal wiring having SiON as an antireflection film, and this is shown in FIGS. ) Will be described.

First, an interlayer insulating film 3 made of SiO ₂ is formed on a metal wiring 1 made of an Al-based metal such as Al-1% Si-0.5% Cu having an antireflection film 2 made of SiON on its upper surface. Then, a resist mask 4 for opening a connection hole facing the metal wiring 1 is formed. The resist mask 4 has an opening diameter of 0.35 μm, for example, and is formed by a chemically amplified resist and excimer laser lithography.
The antireflection film 2 is for preventing the exposure light from being reflected from the metal wiring layer when forming a resist mask (not shown) for patterning the metal wiring 1. The interlayer insulating film 3 is flattened by CMP,
The thickness is distributed between 0.5 μm and 1.0 μm, for example, corresponding to the structure of the base. In the portion where the connection hole is to be formed shown in FIG.
And the thin part is assumed.

The substrate to be etched shown in FIG. 1A was placed on the substrate stage of a substrate bias application type ECR plasma etching apparatus, and the interlayer insulating film 3 was etched under the following conditions as an example. C ₄ F ₈ 45 sccm CH ₂ F ₂ 5 sccm Gas pressure 1 Pa Microwave power 1000 W (2.45 GHz) RF bias power 200 W (800 kHz) Substrate temperature 0 ° C The etching mechanism in this etching process is the same as the previous example. Is.

When the etching progresses and the surface of the antireflection film 2 is exposed, the supply of oxygen from this surface is small and the deposition becomes dominant, and the CF or CHF polymer is deposited and the etching stops. This state is shown in FIG.

On the other hand, the antireflection film 2 is not yet exposed at the opening portion of the connection hole in the thick region of the interlayer insulating film 3, and the etching is continued. Therefore, the antireflection film 2 in the previously exposed shallow interlayer insulating film 3 region is continuously subjected to ion bombardment. However, since the metal wiring 1 is not directly subjected to ion bombardment due to the presence of the deposited polymer and the antireflection film thereunder, spatter reattachment of the metal wiring 1 does not occur even if overetching of more than 100% is performed.

In the subsequent second step, the substrate to be etched was transferred to a down-flow plasma etching apparatus, and as an example, the exposed portion of the antireflection film 2 was removed under the following conditions. C ₄ F ₈ 20 sccm O ₂ 80 sccm Gas pressure 133 Pa Microwave power 1000 W (2.45 GHz) Substrate temperature 100 ° C. In this etching step, CF or CHF polymer deposited on the surface or side surface of the antireflection film is first removed. Oxidation removed,
Next, the antireflection film 2 made of SiON is easily removed due to the effect of heating the substrate, and the connection hole 5 is completed. The down-flow plasma etching condition is that the O ₂ concentration is higher than that in the first embodiment, and the ashing of the resist mask 4 also proceeds at the same time and is removed. This state is shown in Figure 2.
It is shown in (c).

The metal wiring 1 exposed at the bottom of the connection hole 5 is exposed to downflow plasma, but is not sputtered because the ion energy is 20 eV or less.

In this embodiment, SiO on the metal wiring is used.
Since the antireflection film made of N is used as an etching stopper and the antireflection film is removed by downflow plasma in the second step, the surface of the metal wiring is not subjected to sputtering. Therefore, the aluminum crown does not occur even when a plurality of connection holes having different depths are simultaneously opened. Moreover, since resist ashing is performed at the same time, a process with high throughput becomes possible.

The present invention has been described above with reference to the two examples, but the present invention is not limited to these examples.

For example, TiON is used as the material of the antireflection film.
I chose SiON and SiON, but not limited to this, TiN, Si
Any antireflection material having a selection ratio with respect to the SiO ₂ -based interlayer insulating film such as N, a-Si, or SiC may be selected.

Although SiO ₂ has been exemplified as the material for the interlayer insulating film, PSG, BSG, BPSG and AsS containing impurities are used.
You may use G etc. In the case of these silicate glasses, the thickness of the interlayer insulating film in the connection hole forming portion is often different due to the flattening by the reflow treatment after the film formation,
The present invention can be preferably applied to metal wirings other than Al-based metals. In the case of a laminated interlayer insulating film using an inorganic coating insulating film such as SOG, the utility value of the present invention is also great.

Al-1% Si or Al-1 is used as metal wiring.
% Si-0.5% Cu is illustrated, but pure Al and other A
The l-based alloy also easily forms an aluminum crown.
The same applies to metal wiring in which an Al-based metal is laminated on a refractory metal such as W. In addition to the Al-based metal layer, it can be applied to metal wiring such as Cu or Au that is easily sputtered.

[0038]

As is apparent from the above description, by adopting the present invention, sputter re-creation can be achieved even if excessive over-etching is performed when the connection hole facing the metal wiring is opened in the interlayer insulating film on the metal wiring. It has become possible to prevent the generation of aluminum crowns and the like due to adhesion.

Particularly, in a highly integrated semiconductor device of recent years, when a plurality of fine connection holes having different depths are formed in the globally flattened interlayer insulating film, the above effect is great. . Conventionally, the generated aluminum crown or the like has been removed by a post-treatment wet process, but there is no concern about a decrease in after-corrosion or particle level due to this.

Due to the above effects, the present invention greatly contributes to a method of manufacturing a semiconductor device having a step of etching contact holes such as contact holes and via holes based on a fine design rule of the deep submicron class.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a first embodiment to which the present invention is applied in the order of steps, (a) showing a state where an interlayer insulating film and a resist mask are formed on a metal wiring having an antireflection film, (b) () Is a state in which the interlayer insulating film is etched and etching is stopped on the antireflection film, and (c) is a state in which the antireflection film is removed by downflow plasma to complete the connection hole.

2A and 2B are schematic cross-sectional views illustrating Example 2 to which the present invention is applied in the order of steps, in which FIG. 2A is a state in which an interlayer insulating film and a resist mask are formed on a metal wiring having an antireflection film, and FIG. () Is a state in which the interlayer insulating film is etched and etching is stopped on the antireflection film, and (c) is a state in which the antireflection film and the resist mask are simultaneously removed by downflow plasma to complete the connection hole.

3A and 3B are schematic cross-sectional views illustrating a conventional connection hole opening step in the order of steps, FIG. 3A is a state in which an interlayer insulating film and a resist mask are formed on a metal wiring, and FIG. 3B is an etching of the interlayer insulating film. Then, the metal wiring is exposed, (c) is a state in which a spatter reattachment is formed by overetching, and (d) is a state in which the resist mask is removed and the sputter reattachment is projected from the surface of the interlayer insulating film. is there.

[Explanation of symbols]

 1 Metal wiring 2 Antireflection film 3 Interlayer insulating film 4 Resist mask 5 Connection hole 6 Spatter reattachment

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: a step of opening a connection hole facing a metal wiring in an interlayer insulating film on a metal wiring having an antireflection film. A method of manufacturing a semiconductor device, comprising: a first step of etching the interlayer insulating film using a film as an etching stopper; and a second step of etching the antireflection film with downflow plasma. 2. The semiconductor device according to claim 1, wherein in the second step, the resist mask is ashed simultaneously with the etching of the antireflection film by downflow plasma containing an F-based gas and an oxidizing gas. Manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of opening the connection hole is a step of simultaneously opening connection holes having different depths on the same substrate to be etched. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the connection hole has an opening diameter of 0.5 μm or less.