JPH05121378A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To realize a lower-resistant contact without damaging a lower-layer wire material layer in the case where a contact is formed in the lower-layer wire material layer coated with a reflection preventive film. CONSTITUTION:When a via hole 3a is opened in a PSG interlayer insulating film 3 on an Al-1% Si layer 1 having a TiON reflection preventive film 2 on the upper surface, upon exposing the TiON reflection preventive film 2, etching is completed performing by an ion mode to separate a resist, and thereafter a wafer is soaked in an ammoniahydrogen peroxide mixed solution to selectively remove the TiON reflection preventive film 2 having a high ratio resistance. Thus, even after an upper layer wiring is formed, a contact resistance does not increase. Also, as this removing process is the wetetching, a sputter product of an Al-1% Si layer 1 of an under layer is not erroneously reattached to the side wall part of the via hole unlike the prior art and a coverage of an upper layer wiring is also improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly, in a multilayer wiring structure, when electrical connection is made to a lower wiring material layer having an antireflection film on the upper surface, the lower wiring material layer is damaged. It relates to a method of realizing a low resistance contact without giving.

[0002]

2. Description of the Related Art As semiconductor devices have become highly integrated and highly densified as seen in VLSI, ULSI, etc., the proportion of wiring portions on a device chip tends to increase. In order to prevent the chip area from increasing due to this, multi-layer wiring is being developed. In the manufacturing process of a semiconductor device having such a multilayer wiring structure, in order to form a via hole or the like for electrical connection between the upper and lower wiring material layers, an insulating film is formed with the lower wiring material layer as a base. The process of etching is essential.

A typical material for the insulating film is a silicon oxide (SiO ₂ ) material. The etching of the SiO ₂ -based material layer is generally performed under the condition that a high incident ion energy can be obtained because it is necessary to break the strong Si—O bond. That is, the etching mechanism of the SiO ₂ -based material layer is closer to a physical process such as sputtering rather than a chemical process such as radical reaction. The most commonly used etching gas is a gas mainly containing a fluorocarbon compound, and CF _x ⁺ generated from this compound contributes to anisotropic etching.

On the other hand, aluminum (Al) alloys, refractory metal silicides, etc. are widely used as wiring materials for semiconductor devices. The surface of these material layers having a high light reflectance is formed by photolithography. It is becoming essential to provide an antireflection film for the purpose of improving accuracy. This is because the exposure wavelength for the resist material layer shifts to the shorter wavelength side as the design rule of the semiconductor device becomes finer, and the pattern dimension approaches the exposure wavelength. This is because it is difficult to achieve stable resolution above. In the case where the antireflection film is not provided, the influence of the reflected light appears strongly, the resist pattern is deformed, and the line width of the obtained wiring pattern is likely to change.

The antireflection film may be composed of an amorphous silicon layer or the like, but in recent years, a titanium (Ti) -based material layer such as a titanium compound or a titanium alloy is often used because it can be formed in the same step as a barrier metal. It has become so. For example, Proceedings
of 8th VMIC Conference (1
991), p. 13 and p. 34 is TiN, and Proceedings of 38th Semiconductor Integrated Circuit Symposium p.
13 (1990), TiON is used as an antireflection film on each Al-based material layer.

[0006]

By the way, when the insulating film is etched to make contact with the lower wiring material layer covered with the antireflection film, some problems occur. This problem will be described with reference to FIG. The first problem is that if the antireflection film is left on the bottom surface of the connection hole, the contact resistance increases. For example, in Figure 2.
As shown in (a), in a wafer in which an antireflection film 12 made of a Ti type material layer, an interlayer insulating film 13 made of PSG, etc., and a resist pattern 14 are sequentially laminated on an Al type material layer 11, Consider a case where the interlayer insulating film 13 is etched through the opening 14a formed in the resist pattern 14. An etching gas mainly containing a fluorocarbon compound is used for this etching.

FIG. 2B shows a state in which the interlayer insulating film 13 is etched and the via hole 13a is formed. Here, the antireflection film 12 is exposed on the bottom surface of the via hole 13a. At this point, the antireflection film 12 is formed from F ^* in the plasma to the underlying Al film when the interlayer insulating film 13 is etched.
It contributes to protecting the system material layer 11 and preventing the formation of AlF _{x and the} like. However, if a via hole 13a is buried in this state to form a plug and an upper layer wiring is further formed, the contact resistance will increase significantly. For example, typical TiN has a resistivity of about 200.
μΩ · cm and TiON are about 2 mΩ · cm, and both are higher by 2 to 3 digits than 3 μΩ · cm of Al. The actual measured value of the contact resistance is higher than the value calculated from the above-mentioned specific resistance. It is considered that this is because TiF _x is formed due to fluorine contained in the etching gas for the insulating film.

Therefore, it is desired to remove the antireflection film, but the second problem arises in this removal. It is sputter removal of the lower wiring material layer and redeposition of sputter products. The etching of the interlayer insulating film 13 requires high incident ion energy as described above, and thus the underlayer selectivity is likely to deteriorate. Therefore, if the antireflection film 12 is etched by directly applying the conditions for etching the interlayer insulating film 13, the surface of the Al-based material layer 11 is sputtered during overetching, and the film thickness is reduced. Also, the sputtered Al-based material layer 11 is
Redeposited on the side wall portion of the pattern as it is or in the form of AlF _x or the like to form a redeposit layer 11a as shown in FIG. 2C. This redeposited material layer 11a is
Once formed, it is extremely difficult to remove, and even after removing the resist mask 14 by ashing,
As shown in FIG. 2D, the via hole 13a remains in a state of protruding from the opening end. This reattachment layer 11a
Is also called an aluminum crown because it looks like a crown when the wafer is viewed from above with an electron microscope. The redeposited material layer 11a is damaged and becomes a dust source, and when it is projected for a long time, the coverage (coverability) of the material layer formed on the upper layer may be deteriorated, so that the yield of the semiconductor device is significantly increased. It causes to lower.

Therefore, the present invention provides a method capable of preventing the lower wiring material layer from being removed or redeposited when making contact with the lower wiring material layer having an antireflection film on the upper surface, and reducing the contact resistance. To aim.

[0010]

The present invention is proposed to achieve the above objects. That is, the method for manufacturing a semiconductor device according to the first invention of the present application includes a step of selectively etching an insulating film laminated on a lower wiring material layer covered with an antireflection film to open a connection hole. ,
And a step of selectively removing the antireflection film exposed on the bottom surface of the connection hole.

A semiconductor device manufacturing method according to a second invention of the present application is characterized in that the antireflection film is formed of a Ti-based material layer.

Further, the method of manufacturing a semiconductor device according to the third invention of the present application is characterized in that the antireflection film is removed by wet etching.

[0013]

In the first invention of the present application, since the antireflection film on the bottom surface of the contact hole is selectively removed, when the contact hole is filled with the plug material in the later step, the plug material and the lower wiring material layer are directly connected to each other. You will come into contact. Therefore, even if the antireflection film is made of a material having a high specific resistance, there is no fear that the contact resistance will increase.

In the second invention of the present application, the case where the antireflection film is a Ti-based material layer is assumed as the most practical case. This prevents the contact resistance from rising even when, for example, TiN, TiON or the like is used as the antireflection film. Furthermore, in the third invention of the present application,
The antireflection film is removed by wet etching.
That is, since the antireflection film is decomposed and removed by a chemical reaction, no physical removal or damage to the lower wiring material layer due to incident ions occurs, and therefore, there is no fear that a redeposited material layer is formed.

[0015]

EXAMPLES Specific examples of the present invention will be described below. This embodiment applies the second invention and the third invention of the present application, and Al-1% Si exposed on the bottom surface of the via hole.
This is an example in which the TiON antireflection film on the layer is removed by using an ammonia-hydrogen peroxide mixed solution. This process
This will be described with reference to FIG.

First, as shown in FIG. 1A, a TiON antireflection film 2 and a PSG interlayer insulating film 3 are sequentially laminated on an Al-1% Si layer 1 which constitutes a lower wiring, and further thereon. A wafer having a resist mask 4 patterned into a predetermined shape was prepared. Here, the Al
The -1% Si layer 1 is formed to a thickness of about 600 nm by high temperature sputtering using a magnetron sputtering device, and the conditions are, for example, an Ar flow rate of 100 SC.
CM, gas pressure 0.4 Pa, DC power 10 kW, and wafer temperature 500 ° C.

The TiON antireflection film 2 is formed to a thickness of about 30 nm by reactive sputtering using a magnetron sputtering apparatus, and the conditions are, for example, Ar flow rate 70 SCCM, N ₂ -6% O ₂ flow rate 40 S.
CCM, gas pressure 0.4 Pa, DC power 5 kW, and wafer temperature 150 ° C. This condition is optimized for g-line exposure.

The Al-1% Si layer 1 and the TiON antireflection film 2 are formed by using a resist mask (not shown).
It is patterned into a predetermined shape by a known etching gas such as BCl ₃ / Cl ₂ . The PSG interlayer insulating film 3 is formed by atmospheric pressure CVD to a thickness of about 500 nm, and the conditions are, for example, a SiH ₄ flow rate of 80 SCCM,
PH ₃ flow rate 7 SCCM, O ₂ flow rate 1000 SCCM, N
₂ Flow rate was 3200 SCCM and wafer temperature was 410 ° C.

Further, the resist mask 4 is patterned by using a novolac-based positive photoresist material (manufactured by Tokyo Ohka Kogyo Co., Ltd .; trade name TSMR-V3) by g-line exposure and alkali development. The opening diameter of the opening 4a is about 500 nm.

The above wafer is set in a magnetron RIE (reactive ion etching) apparatus, and as an example, c-
The PSG interlayer insulating film 3 is etched through the opening 4a under the conditions of C ₄ F ₈ flow rate of 50 SCCM, gas pressure of 2 Pa, and RF power density of 9.5 W / cm ² (2 MHz),
As shown in FIG. 1B, a via hole 3a was formed. This etching was completed when the TiON antireflection film 2 was exposed.

Then, the resist mask 4 was removed by ashing. The timing of removing the resist mask 4 is a result of taking into consideration the prevention of contamination of the processing solution used in the subsequent wet etching and the extension of the life, but it is not always necessary to remove it at this point.

Next, using a wafer as an example, NH ₄ OH: H
₂ O ₂ : H ₂ O = 1: 2: 2 (volume ratio) was immersed in a mixed solution of ammonia-hydrogen peroxide, and then, as shown in FIG.
The TiON antireflection film 2 exposed on the bottom surface of the via hole 3a was removed as shown in FIG. Although this treatment was performed at room temperature, the solution may be heated up to the boiling point if necessary to increase the etching rate.

Since this step is wet etching, it is essentially impossible for the underlying Al-1% Si layer 1 to be sputtered away to form a redeposit layer. At this time, Al-1% exposed on the bottom surface of the via hole 3
Although the surface of the Si layer 1 was slightly oxidized, the thickness of the formed surface oxide layer 1a was about 5 nm and could be easily removed by performing the reverse sputtering treatment with Ar ⁺ . The state of the wafer after removing the surface oxide layer 1a is as shown in FIG.

After this, an upper layer wiring was formed by a conventional method. This upper layer wiring is formed, for example, by a Ti layer 5 as a barrier metal on the entire surface of the wafer by a sputtering method or the like.
Is conformally deposited, and the Al-1% Si layer 6 is laminated by the high temperature sputtering method or the like so as to fill the via hole 3a and substantially flatten the wafer.
It was formed by depositing the iON antireflection film 7.
The state of the wafer at this time is shown in FIG. Here, since the redeposited layer as in the past is not formed,
No dust was generated and the coverage of the upper layer wiring was good. Further, since the TiON antireflection film 2 having a high specific resistance is removed from the bottom surface of the via hole 3a, the contact resistance of the upper wiring to the Al-1% Si layer 1 which is the lower wiring does not increase at all.

The present invention is not limited to the above-mentioned embodiment, and for example, TiON as an antireflection film is used.
Alternatively, TiN can be used. Further, the interlayer insulating film may be formed of various silicon oxide-based materials other than PSG, silicon nitride, or the like. Further, as a treatment solution for wet etching the antireflection film, in addition to the ammonia-hydrogen peroxide mixture solution, a sulfuric acid-hydrogen peroxide mixture solution, hydrogen peroxide solution, or JP-A-61-185928. The hydrogen peroxide solution containing ethylenediaminetetraacetic acid (EDTA) disclosed in US Pat.

In addition, it goes without saying that the film forming conditions of each material layer, the etching conditions, the structure of the upper layer wiring, and the like can be appropriately changed.

[0027]

As is apparent from the above description, according to the present invention, since the antireflection film having a high specific resistance is removed at the bottom surface of the connection hole, the contact resistance between the lower layer wiring and the upper layer wiring is reduced. There is no fear of increase. Further, since the antireflection film is removed by wet etching, the lower layer wiring is not sputtered or damaged during the removal.

Therefore, the present invention is extremely effective for manufacturing a semiconductor device which is designed according to a fine design rule and has a high degree of integration and high performance.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a process example to which the present invention is applied in the order of steps, (a) showing a state in which a resist mask is formed on a PSG interlayer insulating film, and (b) showing a PSG interlayer insulating film. A via hole is opened in the
With the mask removed, (c) is T at the bottom of the via hole.
The iON antireflection film was removed, and a surface oxide layer was formed on the exposed surface of the Al-1% Si layer. (d) was the surface oxide layer removed. (e) was the upper layer wiring. Represents each state.

2A and 2B are schematic cross-sectional views for explaining problems in a conventional process example, FIG. 2A is a state in which a resist mask is formed on an interlayer insulating film, and FIG. 2B is a via hole in a PSG interlayer insulating film. Is opened, (c) the antireflection film is removed, the Al-based material layer is over-etched to form a redeposited material layer, and (d) the resist mask is removed. Represent

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Al-1% Si layer (lower layer wiring) 1a ... Surface oxide layer 2 ... TiON antireflection film (lower layer side) 3 ... PSG interlayer insulating film 3a ... Via hole 4 ... Resist mask 4a ... Opening 5 ... Ti layer 6 ... Al-1% Si layer (upper layer wiring) 7 ... TiON antireflection film (upper layer side)

Claims (3)

[Claims] 1. A step of selectively etching an insulating film laminated on a lower wiring material layer coated with an antireflection film to open a connection hole, and the antireflection film exposed on the bottom surface of the connection hole. And a step of selectively removing the film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the antireflection film is composed of a titanium-based material layer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the antireflection film is removed by wet etching.