JPH0558263B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, which can easily and accurately form a fine, low-capacitance resistor suitable for semiconductor integrated circuits. The present invention relates to a method for manufacturing a semiconductor device.

[Background of the invention]

Advances in processing technology in recent years have made it possible to reduce the area occupied by transistors, which are active elements, and enable high-speed operation. Accordingly, resistors, which are essential components of integrated circuits, are desired to occupy a small area and have a small capacity.

The resistor shown in FIG. 1 is an example of a conventional low capacitance resistor. FIG. 1a shows a plan view, and FIG. 1b shows a cross-sectional structure taken along the line -'. A resistor is constituted by a silicon substrate 1 and a polycrystalline silicon layer 4 formed on a silicon oxide film 2. Silicon oxide films 3 and 5 are formed by thermal oxidation of polycrystalline silicon 4. Both ends of the resistor are connected to aluminum electrodes 6a, 6b through contact holes 7a, 7b formed by selectively etching the oxide film 5. The resistor shown in FIG. 1 is separated from the substrate 1 by the oxide film 2, and therefore has a small capacitance, but has the following drawbacks.

() To prevent the oxide films 2 and 3 from being etched, the contact hole 7 should be formed in the polycrystalline silicon region 4.
Must be formed on top. Therefore, the minimum width of the resistor is the minimum machining dimension of the contact hole and
It is determined by the mask alignment margin with the polycrystalline silicon region. Also, if the contact hole is made small,
Contact resistance increases, making it difficult to stably obtain a constant resistance value. Therefore, in order to form a resistor having a desired resistance value with high accuracy, the width of the resistor must be designed to be large. This hinders higher integration of circuits.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned conventional problems and provide a low capacitance resistor for fine integrated circuits and a method for manufacturing the same.

[Summary of the invention]

In order to achieve the above object, the present invention utilizes an etching method capable of etching Si ₃ n ₄ with a high selectivity, thereby eliminating the need for a mask alignment margin and thereby forming an extremely fine resistor.

[Embodiments of the invention]

FIG. 2 shows a first embodiment of the present invention. In this embodiment, the polycrystalline silicon and the metal electrode are connected through the opening 7 of the silicon nitride film 8. The width of the resistor 4 is determined by the mask used when patterning the polycrystalline silicon, and the length of the resistor 4 is determined by the mask used when patterning the silicon film. does not require precise alignment. Furthermore, the contact area between the metal electrode 6 and the polycrystalline silicon 4 is large, and a resistor with low contact resistance and high precision can be formed. The manufacturing method of this example will be described below. After forming a silicon oxide film 2 on a silicon substrate 1 by thermal oxidation, polycrystalline silicon is deposited on the surface. Using the patterned photoresist film as a mask, polycrystalline silicon layer 4 is etched into a predetermined shape. Thereafter, the photoresist film is removed, and a silicon dust film 8 with a thickness of 100 nm is formed on the entire surface by vapor deposition. Thereafter, using the bettered photoresist as a mask, the silicon atomized film is selectively etched by a new dry etching method described in detail below.

As is well known, dry etching of silicon or its compounds is performed using, for example, CF ₄ , CF ₄ , +
This was carried out using O ₂ , NF ₃ , SF ₆ , CHF ₃ , CF ₄ , +H ₂ and the like as reaction gases.

However, when the etching rates of Si, SiO ₂ and Si ₃ N ₄ are compared, when CF ₄ , CF ₄ , +O ₂ , NF ₃ or SF ₄ is used, the etching rate of Si is the _{highest ;} , SiO ₂ , the reaction rate decreases in this order.

In addition, CHF ₃ or CF ₄ , +
When H ₂ is used, the etching rate of SiO ₂ and Si ₃ N ₄ is higher than that of Si, but the etching rate ratio of SiO ₂ and Si ₃ N ₄ is only about 2 to 3.

Therefore, when selectively etching Si ₃ N ₄ , CF ₄ , +O ₂ or SF ₄ has been used as a reaction gas, but in this case, the underlying Si is etched because the etching rate of Si is high. In order to prevent this, an SiO ₂ film must be formed between the Si ₃ N ₄ film and the underlying Si, and since _the selectivity ratio between SiO ₂ and Si ₃ N ₄ is small, It was necessary to make the film thicker.

That is, conventionally, it has been difficult to selectively dry-etch a Si ₃ N ₄ film with a high selectivity to Si or SiO ₂ .

Therefore, in the present invention, CH _{2 ,} which has not been used in conventional dry etching, is used as a reactive gas.
Highly selective dry etching of Si ₃ N ₄ was carried out using a gas such as F ₂ and/or CH ₃ F, which contains C, H and F and has an F to H ratio of about 2 or less, as a reaction gas. For example, generally parallel plate type RIE
Using a device called (Reactive Ion Etching), a semiconductor substrate was placed on the high-frequency electrode inside the vacuum chamber via a quartz plate, and the inside of the vacuum chamber was 1×10 ^-3
After evacuation to below Torr, CH ₂ F ₂ gas was introduced to maintain the pressure at 0.03 Torr. Then the frequency
Applying 13.56MHz high frequency power to the high frequency electrode,
Plasma was generated and Si ₃ N ₄ was etched.
At this time, the high frequency power was kept at approximately 500W, but Si ₃
The etching rate ratio of N ₄ and SiO ₂ is approximately 20, and that of Si ₃ N ₄ and Si
Or the etching feed ratio with poly Si is about 25 and Si ₃
Only N ₄ was able to etch with high selection. Also Si ₃ N ₄
The etching rate is approximately 30 nm/min, and in this example, etching was performed for approximately 5 minutes, but SiO ₂ and
PolySi was hardly etched. Thereafter, aluminum is deposited and selectively etched using a patterned photoresist as a mask to obtain the structure shown in FIG.

FIG. 3 shows a second embodiment of the invention. In this example, silicon oxide film 3 was formed by selective oxidation of polycrystalline silicon. The oxide film 3 and the silicon dust film 8 constitute an electrode connection contact hole. This embodiment has a flat surface compared to the resistor shown in FIG. 2, and has a structure in which disconnection is less likely to occur when multilayer wiring is used. Figure 4 is the third
This figure shows the manufacturing process for obtaining the structure shown in the figure. The surface of a silicon substrate 1 is thermally oxidized to form a silicon oxide film 2. Thereafter, polycrystalline silicon 4, silicon dust film 8, and photoresist 9 are formed on the entire surface and patterned to obtain the structure shown in FIG. 4a. Using the photoresist 9 as a mask, the silicon nitride film 8 is selectively etched by the above-described etching method, and the photoresist is removed.
Thereafter, using the silicon dust film 8 as a mask, a silicon oxide film 3 is formed by thermal oxidation to obtain the structure shown in FIG. 4b. A photoresist 10 is applied to the entire surface and patterned to obtain the structure shown in FIG. 4c. Using the photoresist 10 as a mask, the silicon nitride film is selectively etched using the above-described etching method, and the photoresist is removed. after that,
After depositing aluminum and patterning, Figure 3
obtain the structure of

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a fine resistor can be formed without requiring a mask alignment margin.

For example, conventionally, using processing technology for mask alignment of 0.5 μm and contact hole of 2 μm, the minimum width is 3 μm.
about half of the resistance was formed.
It has become possible to form resistors with a width of 1.5 μm with high precision. Furthermore, since the process is simplified compared to conventional manufacturing methods, this point is also extremely advantageous in practical terms.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a conventional low capacitance resistor, Fig. 2 is a diagram showing a first embodiment of the present invention, Fig. 3 is a diagram showing another embodiment of the present invention, and Fig. 4 is a diagram showing the present invention. It is a process diagram showing an example of the invention. 1... Base body, 2, 3, 5... Silicon oxide film,
4... Polycrystalline silicon, 6... Metal, 7 Contact hole, 8... Silicon nitride film, 9, 10... Photoresist.

Claims (1)

[Claims] 1. On the main surface of a semiconductor substrate, a silicon oxide film,
A process of laminating and forming a polycrystalline silicon film and a silicon nitride film, and etching the unnecessary portions of the silicon nitride film using a gas containing C, H and F and having an F to H ratio of about 2 or less. A step of removing the polycrystalline silicon film by dry etching and processing it into a predetermined shape, a step of oxidizing the exposed portion of the polycrystalline silicon film, and a step of etching and removing a predetermined portion of the silicon nitride film to form an opening. a step of forming;
A method of manufacturing a semiconductor device, comprising the step of forming an electrode connected to the polycrystalline silicon film exposed through the opening. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the gas is CH ₃ F or CH ₂ F ₃ .