JPH0451050B2 - - Google Patents

Info

Publication number
JPH0451050B2
JPH0451050B2 JP59215606A JP21560684A JPH0451050B2 JP H0451050 B2 JPH0451050 B2 JP H0451050B2 JP 59215606 A JP59215606 A JP 59215606A JP 21560684 A JP21560684 A JP 21560684A JP H0451050 B2 JPH0451050 B2 JP H0451050B2
Authority
JP
Japan
Prior art keywords
film
titanium
wiring
aluminum
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59215606A
Other languages
Japanese (ja)
Other versions
JPS6193629A (en
Inventor
Hiromichi Kono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21560684A priority Critical patent/JPS6193629A/en
Publication of JPS6193629A publication Critical patent/JPS6193629A/en
Publication of JPH0451050B2 publication Critical patent/JPH0451050B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は半導体装置の製造方法にかかり、特に
金、白金等の金属配線を有する半導体集積回路の
製造歩留り及び品質の向上に有力な効果を発揮す
る半導体装置の製造方法に関するものである。
Detailed Description of the Invention (Technical Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, which is particularly effective in improving the manufacturing yield and quality of semiconductor integrated circuits having metal wiring such as gold or platinum. The present invention relates to a method for manufacturing the device.

(従来技術) 一般に、非常に高信頼性を要求される半導体装
置においては金等の貴金属を用いた金属配線が用
いられるが、この場合金等の貴金属と半導体基板
下地との接着性を確保し、かつ下層配線金属との
化学反応を防ぎ、又金等をメツキ法で被着する場
合には被着を可能とならしめるために、チタン、
白金又はそれらの多層膜等が中間層として使用さ
れる。
(Prior art) Generally, metal wiring using noble metals such as gold is used in semiconductor devices that require extremely high reliability. In addition, titanium,
Platinum or a multilayer film thereof is used as the intermediate layer.

従来このチタン膜をパターニングする方法とし
ては、(1):弗酸を含む水溶液で湿式エツチングす
る方法、(2):CF4等のプラズマ中で乾式エツチン
グする方法、(3):リフトオフ法により白金膜と一
緒にパターニングしてしまう方法等があつた。こ
のうち(1)の弗酸を含む水溶液で湿式エツチングす
る方法では半導体基板表面が弗酸に侵されにくい
材質(シリコン窒化膜等)の場合には問題ない
が、シリコン酸化膜のような弗酸に侵されやすい
材質の場合は基板表面までがエツチングされるこ
とになり、品質上好ましくないという欠点があつ
た。又、(2)のCF4等のプラズマ中で乾式エツチン
グする方法では(1)と同様に半導体基板表面にシリ
コン窒化膜等のCF4プラズマに侵されやすい材質
の部分がある時には適用できない。さらに(3)のリ
フトオフ法により白金膜と一緒にパターニングし
てしまう方法では加工精度が悪く、微細配線パタ
ーンの形成には適さないという欠点があつた。
Conventional methods for patterning this titanium film include (1) wet etching with an aqueous solution containing hydrofluoric acid, (2) dry etching in plasma such as CF 4 , and (3) platinum etching using a lift-off method. There is a method that involves patterning together with the film. Of these methods, (1) wet etching with an aqueous solution containing hydrofluoric acid poses no problem if the semiconductor substrate surface is made of a material that is difficult to be attacked by hydrofluoric acid (such as a silicon nitride film), but If the material is easily attacked by etching, the surface of the substrate will be etched, which is undesirable in terms of quality. Further, the method (2) of dry etching in plasma such as CF 4 cannot be applied when there is a material part on the semiconductor substrate surface that is easily attacked by CF 4 plasma, such as a silicon nitride film, as in (1). Furthermore, the method (3) of patterning together with the platinum film using the lift-off method had the disadvantage that processing accuracy was poor and it was not suitable for forming fine wiring patterns.

(発明の目的) 本発明は、上記のような従来技術の種々の欠点
を除き、品質及び製造留り顕著に向上させ得る半
導体装置の製造方法を提供するものである。
(Objective of the Invention) The present invention provides a method for manufacturing a semiconductor device that can significantly improve quality and production efficiency while eliminating the various drawbacks of the prior art as described above.

(発明の構成) 即ち、本発明は、半導体基板上のシリコン酸化
膜又はPSG(Phospho Silicate Glass)上に被着
したチタン又はチタン化合物の皮膜をアンモニ
ア、過酸化水素又は両者の混合物水溶液によつて
除去することを特徴とした半導体装置の製造方法
である。
(Structure of the Invention) That is, the present invention provides a coating of titanium or a titanium compound deposited on a silicon oxide film or PSG (Phospho Silicate Glass) on a semiconductor substrate using ammonia, hydrogen peroxide, or an aqueous solution of a mixture of the two. This is a method of manufacturing a semiconductor device characterized by removing.

(作用) 本発明によれば、半導体基板表面がシリコン酸
化膜、PSG、シリコン窒化膜いずれであつても
これらの物質をほとんど侵すことなくチタン等の
加工が出来、しかも微細配線パターンの形成が可
能となる。
(Function) According to the present invention, even if the surface of a semiconductor substrate is a silicon oxide film, PSG, or silicon nitride film, titanium, etc. can be processed without almost corroding these materials, and it is also possible to form fine wiring patterns. becomes.

(実施例) 次に本発明の実施例を工程順に説明する。第1
図〜第5図は本発明をアルミニウムから成る下層
配線とTi−Pt−Auから成る上層配線を有する二
層配線半導体集積回路に適用した場合の断面図で
ある。
(Example) Next, an example of the present invention will be described in order of steps. 1st
5 to 5 are cross-sectional views when the present invention is applied to a two-layer wiring semiconductor integrated circuit having a lower layer wiring made of aluminum and an upper layer wiring made of Ti--Pt--Au.

第1図において、周知の方法により不純物拡
散・酸化等と絶縁膜の開孔の終了した半導体基板
1上にアルミニウムから成る下層配線2及びシリ
コン酸化膜から成る層間絶縁膜3が設けられてい
る。このような半導体基板に通常の方法で1,2
層間貫通孔4を形成した後、チタン膜5、アルミ
ニウム膜6を蒸着法等で被着する(第2図)。さ
らに通常の写真食刻技術により、配線として残さ
ない部分にフオトレジスタ7を形成した後、アル
ミニウム膜6を選択的にエツチングし、この上か
らスパツタ法等でチタン・白金膜を被着する(第
3図)。然る後にリフトオフ法により、フオトレ
ジスト7及びアルミニウム膜61の残存する部分
のチタン・白金膜を除去し、白金上に金膜10を
メツキ法等で被着し、アルミニウム膜6をリン酸
等で除去する(第4図)。この後、不要となつた
チタン膜51アンモニア水と過酸化水素水の混合
液で除去する(第5図)。本発明ではこのエツチ
ングに弗酸を含む薬品を用いないため、層間絶縁
膜3は殆どエツチングされることはない。そのた
め後工程で半導体基板全面にアルミニウムのエツ
チングを行う様な場合にでも下層配線2が侵され
ることは殆んどなく、又、素子の信頼性も高く保
つことができる。以上は本発明を金配線を含む2
層配線半導体集積回路に適用した場合の方法を述
べたが、チタン又はチタン化合物を含むその他の
構造の半導体装置にも同様に実施できることは明
らかである。
In FIG. 1, a lower wiring 2 made of aluminum and an interlayer insulating film 3 made of a silicon oxide film are provided on a semiconductor substrate 1 which has undergone impurity diffusion, oxidation, etc. and opening of an insulating film by a well-known method. On such a semiconductor substrate, 1 or 2
After forming the interlayer through hole 4, a titanium film 5 and an aluminum film 6 are deposited by vapor deposition or the like (FIG. 2). Furthermore, after a photoresistor 7 is formed in the portion not to be left as wiring using ordinary photolithography technology, the aluminum film 6 is selectively etched, and a titanium/platinum film is deposited on top of this by sputtering or the like. Figure 3). Thereafter, the titanium/platinum film on the remaining parts of the photoresist 7 and the aluminum film 61 is removed by a lift-off method, the gold film 10 is deposited on the platinum by a plating method, and the aluminum film 6 is coated with phosphoric acid or the like. Remove (Figure 4). Thereafter, the unnecessary titanium film 51 is removed with a mixture of ammonia water and hydrogen peroxide water (FIG. 5). In the present invention, since a chemical containing hydrofluoric acid is not used for this etching, the interlayer insulating film 3 is hardly etched. Therefore, even when aluminum is etched over the entire surface of the semiconductor substrate in a later step, the lower wiring 2 is hardly attacked, and the reliability of the device can be maintained high. The above describes the present invention in two parts including gold wiring.
Although the method has been described when applied to a layer wiring semiconductor integrated circuit, it is clear that the method can be similarly applied to semiconductor devices having other structures containing titanium or titanium compounds.

(発明の効果) 以上説明したように、本発明によれば金・白金
等の金属配線を含む半導体装置を高い品質で歩留
りよく製造することができる。
(Effects of the Invention) As described above, according to the present invention, a semiconductor device including metal wiring such as gold or platinum can be manufactured with high quality and high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第5図は、本発明の実施例を製造工
程順に示した断面図である。 尚、図において、1……半導体基板、2……下
層配線、3……層間絶縁膜、4……貫通孔、5…
…チタン膜、6……アルミニウム膜、7……フオ
トレジスト膜、8……チタン膜、9……白金膜、
10……金膜、である。
1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. In the figure, 1...semiconductor substrate, 2...lower layer wiring, 3...interlayer insulating film, 4...through hole, 5...
...Titanium film, 6...Aluminum film, 7...Photoresist film, 8...Titanium film, 9...Platinum film,
10...Gold film.

Claims (1)

【特許請求の範囲】[Claims] 1 チタンを含む上層配線と、シリコン酸化膜、
PSG、シリコン窒化膜のいずれかから成る層間
絶縁膜と、アルミニウム又はアルミニウム合金か
ら成る下層配線とを有する半導体装置において、
前記下層配線の少なくとも一部を覆うように形成
された部分の前記層間絶縁膜上に延在する前記チ
タンを弗酸を含まない過酸化水素とアンモニアと
混合水溶液のみでエツチングすることを特徴とす
る半導体装置の製造方法。
1 Upper layer wiring containing titanium, silicon oxide film,
In a semiconductor device having an interlayer insulating film made of either PSG or silicon nitride film, and lower layer wiring made of aluminum or aluminum alloy,
The titanium extending on the interlayer insulating film in a portion formed to cover at least a portion of the lower wiring is etched using only an aqueous solution containing hydrogen peroxide and ammonia that does not contain hydrofluoric acid. A method for manufacturing a semiconductor device.
JP21560684A 1984-10-15 1984-10-15 Manufacture of semiconductor device Granted JPS6193629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21560684A JPS6193629A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21560684A JPS6193629A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6193629A JPS6193629A (en) 1986-05-12
JPH0451050B2 true JPH0451050B2 (en) 1992-08-18

Family

ID=16675211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21560684A Granted JPS6193629A (en) 1984-10-15 1984-10-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6193629A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19915348B4 (en) * 1999-04-06 2019-06-27 Schaeffler Technologies AG & Co. KG bearings
JP4577095B2 (en) * 2005-06-03 2010-11-10 東ソー株式会社 Etching composition for metal titanium and etching method using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5198957A (en) * 1975-02-26 1976-08-31
JPS55138235A (en) * 1979-04-13 1980-10-28 Toshiba Corp Manufacture of titanic etching solution and semiconductor device using this etching solution

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5198957A (en) * 1975-02-26 1976-08-31
JPS55138235A (en) * 1979-04-13 1980-10-28 Toshiba Corp Manufacture of titanic etching solution and semiconductor device using this etching solution

Also Published As

Publication number Publication date
JPS6193629A (en) 1986-05-12

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