JP2702010B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for forming a multilayer wiring layer of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, aluminum two-layer wiring technology has been widely used mainly for ASICs such as gate arrays in response to high integration and high speed of MOS integrated circuits.

FIGS. 3A to 3D and 4E and 4F are cross-sectional views of a semiconductor device showing a conventional process of forming a two-layer aluminum wiring. In forming a two-layer wiring of a semiconductor element formed on a single semiconductor substrate 1, a wiring metal film is first formed on a silicon oxide film 2 formed on the semiconductor substrate 1 as shown in FIG. After the formation of the aluminum alloy film 3 as a mask, a first-layer metal wiring is formed using a resist as a mask by reactive ion etching. Next, FIG.
B, the oxide film 4 is formed by using the plasma CVD method.
Is grown and flattened using an inorganic coating film (SOG) 5 as shown in FIG. 3C, and then, as shown in FIG. 3D, a PSG film (Phosph
o-Silicate Glass (phosphorus glass film) 6
Is grown to form an interlayer insulating film. Next, in order to form a via hole as an interlayer connection hole, as shown in FIG. 4E, using the resist 7 as a mask, the PSG film 6 as an interlayer insulating film and the plasma oxidation are formed by reactive ion etching. The film 4 is etched. Further, after removing the resist 7 and removing the alumina film on the surface of the aluminum alloy film 3 by RF sputtering in the interlayer connection hole, as shown in FIG. 4F, an aluminum alloy film 8 as a wiring metal film is formed. A desired two-layer aluminum wiring pattern is formed by forming a second-layer metal wiring by reactive ion etching using a resist as a mask and a resist as a mask.

[0004]

In the above-mentioned conventional configuration,
In the miniaturized multilayer wiring, the aspect ratio of the interlayer connection hole becomes large, and when depositing the wiring metal film thereon, it is difficult to uniformly deposit the wiring metal film in the interlayer connection hole. There has been a problem that the disconnection of the wiring at the end of the hole or the thickness of the wiring metal film becomes thin, and the reliability is easily degraded due to electromigration or stress migration, resulting in poor yield.

The present invention solves the above-mentioned conventional problems. In a miniaturized multilayer wiring, the step coverage of a wiring metal film at the end of an interlayer connection hole having a large aspect ratio is improved to improve connection reliability. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving the yield.

[0006]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention is directed to a method of forming a metal multilayer wiring layer of a semiconductor device, wherein a plasma oxide film is formed on a first metal film pattern. Forming an inorganic coating film on the plasma oxide film and planarizing the same; and forming 2.5% by weight on the plasma oxide film and the inorganic coating film.
Forming a BSG film having a boron concentration of about 5.0% by weight, forming a resist mask on the interlayer insulating film composed of the plasma oxide film, the inorganic coating film and the BSG film, and using the resist mask as a mask Performing wet etching of the BSG film, and subsequently dry etching the remaining interlayer insulating film to form an interlayer connection hole, and connecting the first layer metal film pattern via the interlayer connection hole. Forming a second metal film on the BSG film.

[0007]

[0008]

With the above arrangement, a BSG film is formed on a plasma oxide film as an interlayer insulating film of a metal multilayer wiring.
When the interlayer connection hole is formed by wet-etching the film, a slope-shaped taper is formed at the end of the interlayer connection hole, instead of a bowl-like curved shape as in the conventional case where the PSG film is wet-etched. Therefore, the step coverage of the second-layer metal film is improved, the reliability of the fine two-layer metal wiring is improved, and the yield is easily improved. Also,
Since the boron concentration in the BSG film is 2.5% by weight to 5.0% by weight, a clean slope-shaped taper is formed at the end of the interlayer connection hole when wet etching is performed. Further, since the thickness of the second metal film is formed to be larger than the thickness of the second metal wiring interlayer insulating film, the step coverage of the second metal film is ensured.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. It is to be noted that components having the same functions and effects as those of the conventional example are denoted by the same reference numerals.

FIGS. 1A to 1D and 2E to 2G are cross-sectional views of a semiconductor device showing a process of forming a two-layer aluminum wiring according to an embodiment of the present invention. First, as shown in FIG.
A silicon oxide film 2 is formed on a semiconductor substrate 1 on which a predetermined region is formed by an ordinary method, and an aluminum film having a thickness of 0.8 μm and containing 1% Si by weight is formed on the silicon oxide film 2. An alloy film 3 is formed to form a pattern.
Next, as shown in FIG. 1B, a plasma oxide film 4 is grown to a thickness of 300 nm by a plasma CVD method, and then, as shown in FIG. 1C, an inorganic coating film 5 is formed by a spin coating method, and annealed. Vitrification is performed and flattened. The film thickness is about 190 nm on a flat surface. Further, as shown in FIG. 1D, the boron concentration is about 2.5% by weight to about 5.0% by weight using an SiH ₄ —B ₂ H ₆ —O ₂ system gas using an atmospheric pressure CVD method. BSG film (BoronSilicate Gl
as; boron glass film) 11 is grown to 400 nm. The plasma oxide film 4 and the BSG film 11 form an interlayer insulating film.

Next, in order to form an interlayer connection hole in the interlayer insulating film, a pattern is formed using a photoresist 7. Then, after forming a resist pattern on the resist 7, as shown in FIG. 2E, wet etching is performed for about 7 minutes with 20: 1 buffered hydrofluoric acid.
As shown in (1), the remaining interlayer insulating film is dry-etched by reactive ion etching, the resist is removed, and an interlayer connection hole 12 is formed.

Further, after removing the alumina film on the surface of the aluminum alloy film 3 in the interlayer connection hole 12 by RF sputtering, the film thickness becomes 1.0 μm as shown in FIG.
m, aluminum alloy film 13 containing 1% by weight of Si
Is formed so that this film thickness is greater than the film thickness of the interlayer insulating film, and a second layer of metal wiring is formed using a resist as a mask by a reactive ion etching method. A two-layer aluminum wiring pattern is formed.

[0013] Here, as shown in FIGS.
When the G film 11 is wet-etched, the aluminum alloy film 13 as a wiring metal film does not have a curved shape as in the case where the PSG film 6 is wet-etched, but is formed at the end of the interlayer connection hole 12. With a slope-shaped taper,
The aspect ratio of the interlayer connection hole 12 is reduced. At this time,
If the boron concentration in the BSG film is less than 2.5% by weight,
When wet-etched, the interlayer connection holes 12 have a curved shape and do not have a beautiful slope-shaped taper. Therefore, the boron concentration in the BSG film is 2.5% by weight.
If it is 5.0% by weight, a slope-shaped clean taper is formed at the end of the interlayer connection hole 12. Further, if the thickness of the aluminum alloy film 13, which is the second metal film, is small, the step coverage of the aluminum alloy film 13 is deteriorated. If it is formed thicker, the step coverage of the aluminum alloy film 13 is ensured.

As described above, after the wiring patterning of the first aluminum alloy film 3 on the semiconductor substrate 1, the plasma oxide film 4 is grown as an interlayer film, flattened by the inorganic coating film 5, and then subjected to the normal pressure CVD method. A BSG film 11 is grown to form an interlayer insulating film, then an interlayer connection hole 12 is formed by wet etching and dry etching, and the wiring of the second layer aluminum alloy film 13 is patterned to form a two-layer metal wiring. When forming an aluminum alloy film 13 which is a wiring metal on the BSG film 11, a slope-shaped taper is attached to the entrance end of the interlayer connection hole 12 to reduce the aspect ratio of the interlayer connection hole 12. A metal film can be uniformly deposited in the interlayer connection hole 12, and the step coverage of the aluminum alloy film 13, which is the second layer metal film, is improved to improve connection reliability. Are allowed, it is possible to achieve a yield improvement of the fine-layer metal interconnection.

[0015]

As described above, according to the present invention, a slope-shaped taper can be formed at the end of the interlayer connection hole by wet-etching the BSG film, which is a two-layer metal wiring interlayer insulating film, and the interlayer insulating film can be tapered. The aspect ratio of the connection hole can be reduced, so that the step coverage of the second-layer metal film is improved, the connection reliability is improved, and the yield of fine two-layer metal wiring can be improved. is there.

[Brief description of the drawings]

1A to 1D are cross-sectional views of a semiconductor device showing a step of forming a two-layer aluminum wiring according to one embodiment of the present invention.

FIG. 2E to FIG. 2G show the second embodiment of the present invention following FIG. 1D.
FIG. 10 is a cross-sectional view of the semiconductor device illustrating a step of forming a layer aluminum wiring.

3A to 3D are cross-sectional views of a semiconductor device showing a conventional two-layer aluminum wiring forming process.

FIGS. 4E and 4F are cross-sectional views of the semiconductor device showing a conventional two-layer aluminum wiring forming process following FIG. 3D.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3, 13 Aluminum alloy film 4 Plasma oxide film 5 Inorganic coating film 7 Resist 11 BSG film 12 Interlayer connection hole

Claims (1)

(57) [Claims] 1. A method for forming a metal multilayer wiring layer of a semiconductor device.
A plasma oxide film on the first metal film pattern
Forming an inorganic coating film on the plasma oxide film
Forming and planarizing, the plasma oxide film and
2.5% to 5.0% by weight of borohydride on the inorganic coating film
Forming a BSG film having a plasma concentration;
A layer comprising an oxide film, the inorganic coating film and the BSG film
Forming a resist mask on the inter-insulating film;
Perform wet etching of the BSG film using the mask as a mask.
Then, dry etch the remaining interlayer insulating film
Forming a connection hole; and forming the connection hole through the interlayer connection hole.
The second metal film connected to the first metal film pattern
Forming on the BSG film.
Method of manufacturing a semiconductor device that.