JPS6060750A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a contact hole with no overhang by etching a first thin film in a contact region and coating the peripheral section of the contact region with a second resist mask. CONSTITUTION:An Si nitride film 9 is etched while using a photo-resist 10 in a contact section as a mask. The resist 10 is removed. A second photo-resist 11 is patterned, and SiO2 8 is etched. An overhang is not generated on the lower side of the Si nitride 9 because the resist 11 is formed on the side inner than the end of the etched Si nitride 9. The resist 11 is removed, and tantalum oxide 12 is evaporated from the upper section of a contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a capacitor suitable for realizing a large-scale integrated circuit (LSI).

[Background of the invention]

In LSI, especially dynamic memory and bipolar memory, the area of the capacitor has been reduced as the degree of integration has improved, but the capacitance of the capacitor is still limited due to circuit operation conditions such as preventing malfunction due to alpha rays. The limit cannot be reduced (%
960. Japanese Patent Publication No. 53-97343).

However, conventional LS with dynamic memory as a representative example
Thermal oxidation silicon has been used as a dielectric material for I capacitors, but as the area of the capacitor decreases, the thickness of the oxide film must be made thinner, making it difficult to ensure a sufficient yield. be. Therefore, there is an increasing demand for dielectric materials for capacitors having a high dielectric constant, such as thermally oxidized silicon. Attempts have been made to use transition metal oxides such as silicon nitride and tantalum oxide as the new capacitor dielectric materials mentioned above, but these require mass productivity and reproducibility necessary for the LSI manufacturing process. In this case, it is necessary to deposit the above-mentioned dielectric material by vapor phase growth (CVD) or sputtering.

As shown in the cross-sectional view of FIG. 1(a), the LSI capacitor is made by forming a contact hole in a portion covered with the second insulating film 2 and the first insulating film M3 on the conductive substrate L. Often formed and created.

When forming a capacitor on the area shown in FIG. 1(a) using the conductive substrate 1 as one electrode, a 7-photoresist 4 is formed by patterning as shown in FIG. 1(1)) to form the first insulating The first insulating film is selectively etched with an etching method having a high etching rate, and then the second insulating film is etched with a second etching method having a high etching rate with respect to the second insulating film. is the conventional method.

When the above-mentioned etching is performed, the second insulating film 2 is etched to the bottom of the first insulating film 3 around the contact hole as shown in FIG. 1(b), resulting in a so-called overhang I.
produces Ia.

Next, as shown in FIG. 1(C), the resist 4 is removed,
The capacitor dielectric material 5 is formed by CVD, sputtering, or the like. At that time, the dielectric material 5 is not formed in the overhang part a, or is extremely thin. Therefore, when a metal film or the like is deposited next as the upper electrode 6, the upper electrode 6 also enters the overhang part, and the electrode 6 and board 1
The yield of capacitors decreases due to short-circuiting.

As a result, when a capacitor is formed by forming a contact hole in an insulating film that is looser than two or more layers, overhang tends to occur, which can cause the dielectric to break and cause a breakdown voltage failure in the capacitor. There were many. Further, regarding the electrode on the upper contact hole, there are also disadvantages in that the wiring material is easily broken at the overhang portion, resulting in disconnection.

[Purpose of the invention]

An object of the present invention is to prevent the occurrence of overhang during the formation of the contact holes, and to manufacture a semiconductor device that does not cause a decrease in yield due to breakage of the electrode wiring material or the capacitor film.

[Summary of the invention]

The concept of the present invention is to pattern a first resist mask in a contact region covered with a thin film consisting of two or more layers, to etch the first thin film, and to remove the first resist mask. A second resist mask is formed so as to cover the periphery of the contact region, and the second thin film is etched to form a contact hole without overhang, and an electrode wiring material or capacitor is deposited on the top of the contact hole. The purpose is to prevent breakage of the insulating film.

[Embodiments of the invention]

Hereinafter, the concept of the present invention will be explained in detail with reference to Examples.

FIG. 2 shows a method for manufacturing a capacitor according to the present invention using a cross-sectional view.

As shown in FIG. 2(a), the surface of the 84 substrate 7 doped with a high concentration of impurities with a trench specific resistance of 0.03Ω or less was oxidized in dry 02 gas at 1000C for 30 minutes (film thickness 33Ω).
Silicon oxide 8 with a thickness of 8 nm was formed. Next, a silicon nitride film 9 with a thickness of 120 nm is deposited by the CVD method, and the surface is activated to prevent the photoresist from peeling off.
Coat using a 38m spin rotary coater. Thereafter, exposure is performed using a contact exposure type photoaligner (Cob, manufactured by ILT), and development is performed in a usual manner to form a photoresist pattern 10 of the contact portion.

Using the photoresist 10 as a mask, the silicon nitride film 9 was etched using an IPC type dry etching device manufactured by Tokyo Ohka Co., Ltd. The reaction residue is CF containing 5% of 02.
4 gases, gas pressure during plasma discharge is 0.6 to
rr, the power was 200W″″C. The above-mentioned etching was completed in about 3 to 4 minutes, but over-etching was performed for 30 seconds after the interference color on the entire surface of the wafer disappeared.

As a result, as shown in FIG. 2(b), silicon nitride 9
A side etch of about 150 nm was generated on the lower side of the periphery of the resist 10. At this time, the underlying silicon oxide film 8 is hardly etched. Next, the resist 10 is removed by a known method.

Subsequently, as shown in FIG. 2(C), a second photoresist 11 is patterned, and the silicon oxide 8 is etched for about 40 seconds using an etching solution with a hydrogen fluoride solution:ammonium fluoride solution ratio of 6. do. As a result of this etching, the silicon oxide 8 at the bottom of the second resist 11 is etched by about 4
Qnm side etching is performed, but since the second resist 11 is formed 1 μm inside from the edge of the etched silicon nitride 9, no overhang occurs below the silicon nitride 9.

Please note that this 1 μm interval takes into consideration the alignment accuracy of the photo aligner! I decided.

As shown in FIG. 2(d), after removing the resist 11, oxidized mental 12, which has good characteristics as a high dielectric constant material, was sputtered from above the contact hole as a capacitor dielectric. Mo2B was deposited as the top electrode and processed by conventional photolithography methods. MO can be easily etched with an etching solution containing phosphoric acid.

Hereinafter, the characteristics of a capacitor formed by the method of the present invention will be compared with those of a capacitor formed by the conventional method shown in the prior art section.

FIG. 3(a) shows the current-voltage characteristics of a capacitor formed by the method of the present invention, and FIG. 3(b) shows the current-voltage characteristics of a capacitor formed by the above-mentioned conventional method. It can be seen that in the capacitor shown in FIG. 3(a), there is almost no variation in the measured values of some capacitors, and a capacitor with good reproducibility is formed. On the other hand, Fig. 3Φ
In the capacitor formed by the conventional method shown in ), the current density is large and varies widely depending on the measurement sample, so the reliability is too low as an LSI capacitor.

Therefore, when using the contact hole without overbank according to the present invention, 600 mm from the top of the contact hole is used.
What film thickness does Ta1ls have? It can be seen that no breakage occurs even when the material is deposited by sputtering.

On the other hand, the thickness of the upper electrode of the contact hole is the usual L
In the SI process, the thickness is about 0.2 to 1.0 μm, so there is no fear of breakage.

It should be noted that if silicon nitride 9 and silicon oxide 8 are simultaneously etched using a dry etching method using a method other than the present invention, for example, as shown in FIG. In the LSI manufacturing process, a defect layer was formed by plasma on the surface of S+7 after etching, and Si
The surface of #Si7 may be contaminated and it becomes necessary to clean the surface of #Si7. When cleaning, an aqueous solution containing hydrofluoric acid is often used, but at that time, the silicon oxide 8 is often etched, resulting in an overhang.

〔Effect of the invention〕

According to the present invention, when forming a contact hole in a region covered with two or more layers of thin films, it is possible to form a contact hole without overhang, so that a dielectric thin film for a capacitor and an upper electrode can be formed without a step break. This has the effect of significantly improving the yield of LSI.

[Brief explanation of drawings]

Figures 1 (a), (b), and (C) are cross-sectional views showing the conventional capacitor formation process; Figures 2 (a) and (b)
, (C), (d) are cross-sectional views showing the manufacturing process of the capacitor according to the present invention, FIG. 3(a) is the current-voltage characteristic of the capacitor in one embodiment of the present invention, and FIG. 3(b) is
shows the current-voltage characteristics of a capacitor produced by a conventional process. DESCRIPTION OF SYMBOLS 1... Conductive substrate, 2... Second insulating film, 3...
1st R film, 4... Photoresist, 5... Dielectric material, 6... Electrode, 7... Sr substrate, 8... Silicon oxide, 9... Silicon 9ide, 10 ...Photoresist, 11...Second photoresist, 12...
Tantalum oxide, 13 oxide / Yen (a> / (b) 2 Figure (υ) (b) [=- <C) "3 (ill) foot CV) (Tono mo tile <v)

Claims (1)

[Claims] 1. In a semiconductor device in which a first thin film/a second thin film/a conductive substrate are laminated, a first resist mask is formed on the first thin film by patterning the first resist mask; The first thin film is etched, the first resist mask is removed, and the second thin film is etched to cover the vicinity of the edge of the first thin film on the second thin film remaining after the etching. 1. A method of manufacturing a semiconductor device, comprising patterning a resist mask and etching the second thin film to form a step portion or a contact hole without geobar hang. 2. In the manufacturing method according to claim 1, an insulating film is deposited from above the formed contact hole, and then an electrode is formed on the insulating film to form a capacitor. Method of manufacturing the device. 3. In the manufacturing method according to claim 2, the insulating film is formed of at least a monoxide selected from the group consisting of transition metals such as tantalum, niobium, vanadium, titanium, zirconium, and hafnium. A method for manufacturing a semiconductor device, characterized in that: