JPS63293859A - Multilayer interconnection structure and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent interconnections formed on the sidewalls of projections of an underlying layer from being peeled off without deteriorating adhesive strength at the sidewalls even if the interconnections have a very small width, by bonding the interconnections to the underlying insulating film principally at the sidewall regions of the interconnections. CONSTITUTION:The surface of a substrate 10 except its electrode extracting region is coated with an underlying insulating film 20 the surface of which is projected in a predetermined manner. A first conductor layer 30 is adhered on the surface insulating film 20, and is treated such that it is left only on the sidewalls of the projections of the insulating film 20, whereby first interconnection layers 30' are produced. An interlayer insulating film 40 is formed. The part of the film 40 where connection is to be carried out is removed by etching to form a contact hole 50 there. A second interconnection layer 60 is provided on the insulating film 40. The bottom and the sidewalls of the interconnections 30' are thus bonded to the insulating film 20 with sufficient bonding strength. Accordingly, the interconnections 30' can be prevented from being peeled off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure such as a semiconductor integrated circuit, particularly a multilayer wiring structure having two or more layers of wiring, and a method for manufacturing the same.

[Conventional technology]

Conventional semiconductor integrated circuits, particularly wiring structures, are made by forming an insulating film 2 of 5iOz or the like on a silicon substrate lo on which active elements (not shown) such as transistors are formed, as shown in FIG.
0 by a vapor phase growth method or the like, the portions (not shown) necessary for connection between the substrate 10 and the first wiring conductor layer 3o formed on the first insulating film 20 thereon are known. After that, a first conductor layer 30 of aluminum or the like is formed on the entire surface, and unnecessary portions of the conductor film are removed using photolithography and etching techniques to form the desired first layer. A pattern for the wiring 30 has been obtained. Next, in order to obtain two or more wiring layers on this first wiring layer 30, a second insulating film 40 made of 5iOz or the like is deposited thereon using the method described above or the high frequency sputtering method. After that, the insulating film of the contact portion 50 necessary for connection with the second layer wiring 60 formed thereon is selectively removed, and a conductive layer of aluminum or the like is then deposited on the entire surface using a high frequency sputtering method or the like. However, the desired second layer wiring pattern 60 was obtained by a well-known method. Note that before depositing the second circumferential trench film, a sputter cleaning process is usually performed to clean the surface of the first layer wiring 30 exposed to the contact portion. This treatment is for removing a nonconductor layer such as an oxide film layer formed on the surface of the first layer wiring 30 and improving the electrical conduction characteristics between the first layer wiring 30 and the second layer wiring 60. .

In addition, as a conventional manufacturing method for wiring structures, a method that enables the formation of extremely fine wiring has been published in Japanese Patent Application Laid-Open No. 61-14.
There is a known example described in No. 1140. In this method, a resist processed to a predetermined size is provided on a substrate, a conductive layer is attached to the entire surface, and then the conductive layer other than the side wall portion of the resist film is removed.
Furthermore, the resist film is also removed to obtain wiring at desired set intervals.

[The interlayer point that the invention attempts to solve]

The above-mentioned conventional technology has the drawback that the following problem occurs when attempting to create a wiring pattern in the submicron region or even finer than that.

In other words, if the width of the first M wiring becomes narrow as described above.

The bonding surface between the wiring and the underlying insulating film becomes smaller and the adhesive strength decreases, causing the wiring pattern to peel off or fall. The wiring formation method shown in the above-mentioned Japanese Patent Application Laid-open No. 6]-141140 forms the wiring on the side wall of the resist 1-, which enables the formation of a fine pattern. No consideration is given to the problem of the wiring peeling off or falling down after removal. This problem becomes more pronounced as the height of the wiring increases8 (as the asbestos ratio increases). Therefore, in the method described above, even if the wiring width can be narrowed, it is difficult to increase the width of J'7, and the resistance of the wiring increases significantly.

Furthermore, the deposition of the wiring material film must be carried out at a substrate temperature within the range of heat resistance of the resist, which is also disadvantageous in terms of film adhesion.

Furthermore, in the prior art described above, if a misalignment of the mask occurs during the process of forming a contact hole in the five-layer insulating film, the contact 1 is formed deviating from the first layer wiring pattern. In the sputter cleaning method, only the upper surface of the first layer wiring exposed in the contact hole is usually cleaned, so in this case, the contact area is always smaller than the desired area.
Contact resistance will increase. In order to avoid this problem, conventionally, masks have been designed with sufficient allowance for alignment between the first layer wiring and the contact hole. However, this method of increasing the alignment margin hinders the reduction of the wiring pitch and poses a major problem in improving the degree of integration of integrated circuits. Especially with narrow and thick wiring like the present invention,
The area of connection with the upper layer wiring becomes significantly smaller, which is disadvantageous.

[Means for solving problems]

Among the above objectives, the formation of a fine wiring pattern with a large aspect ratio is achieved by using the portion of the conductor layer formed on the base insulating film having a step, which adheres to the side wall of the base step, as a wiring pattern. Ru. Further, if the present technology is adopted, it becomes possible to arrange a wiring pattern in a direction different from the main plane direction of the substrate, that is, in the direction of the side wall of the wiring, by combining two or more types of conductor materials. Therefore, if this technology is used to create a structure in which a material that can be selectively etched by gas etching in gas plasma or reactive gas is deposited on the sidewall of the lower layer wiring, the upper layer wiring can be coated over the contact hole. It becomes possible to clean the upper surface and the side wall surface, which are the hazy surfaces of the lower layer wiring, with gas plasma before contacting the contacts, thereby realizing a contact having good conduction characteristics.

[Effect]

Among the above-mentioned means, the wiring formed on the side wall portion of the base step and the base insulating film are bonded to each other mainly in the side wall region of the wiring. Therefore, even if the width of one wire becomes fine, the adhesion of the side wall portion will not deteriorate, and the wire will not peel off or fall down. Note that this effect works more effectively as the height of the wiring increases, that is, as the asbestos ratio of the wiring increases.

Further, the above means can achieve a combination of two or more types of conductors or compound materials in the direction of the sidewall of the wiring. On the other hand, dry etching using neutral radicals in gas plasma or gas etching in a reactive gas atmosphere is also suitable for etching side walls of wiring patterns. Therefore, by selecting a material that can be removed by etching the side wall of the underlying wiring in the gaseous atmosphere, the upper surface and side wall surface of the first layer wiring exposed in the contact hole can be cleaned using the above-mentioned method. It becomes easier to do so.

〔Example〕

The present invention will be explained in detail below using examples.

Example 1 FIGS. 1(a) to 1(d) are schematic cross-sectional views showing an example of the wiring structure and manufacturing process of the present invention.

As shown in FIG. 1(a), a silicon substrate 10 on which elements (not shown) such as transistors and resistors are built.
A silicon dioxide film 20 covering the area other than the electrode lead-out portion and having predetermined uneven steps is formed thereon, and then a first circumferential trench layer 30 made of aluminum is deposited over the entire surface.

Here, the silicon dioxide film mentioned above is exposed to N at a temperature of 800°C.
20.

This film was deposited by the CVL method using N2+SiH4 (4%) as a reaction gas. The step was formed by a well-known photolithography technique and a dry etching method using CF4 as an etching gas, and the depth of the groove was about 2 μm. In addition, the aluminum film is triisobutylaluminum (T
It was formed by the LPCVD method using IBAr, ) as a raw material. 7
The flow rate of I' I BA I is 50 SCCM, the substrate temperature is 250° C., and the pressure is 0.5 Torr. 10
An AM film of about 1 μm was formed by deposition for 1 minute. In addition, AQ
As a treatment before depositing the film, this silicon substrate was subjected to T i CQ at a substrate temperature of 250°C, a pressure of 0, and 2 Torr.
4 atmosphere for about 1 minute.

Next, as shown in FIG. 6(b), processing was performed under conditions such that only the AQ film on the step sidewall of the base insulating film remained, and the single processing that formed the first layer wiring 30 was performed using anisotropic dry etching. The etching gas was a mixture of BCQs and 30% CCQ&, and the pressure was 0.
It was conducted under the conditions of orr.

Next, as shown in FIG. 4C, an interlayer insulating film 40 made of polyimide resin is formed to a thickness of about 3 μm, and then predetermined portions that will become connections between the conductor layers are removed by etching. A contact hole 50 was provided in the.

The polyimide resin adopted on the actual flow side is a commercially available resin.
IQ (manufactured by Hitachi Chemical Co., Ltd.).Before forming the polyimide resin, an AQ chelate solution was applied to the substrate in order to improve the adhesion between the polyimide resin and the substrate.
The coating was transferred and then heat treated to form a film of the AQ chelate compound. Thereafter, the polyimide described above was applied onto the substrate by a spin coating method, and heat treatment was performed to volatilize the solvent and polymerize and harden the resin. Further, contact holes in polyimide resin were formed using well-known photolithography technology and plasma etching technology using 02 gas.

Next, as shown in FIG. 1(d), a second layer wiring 60 was formed. This wiring was deposited by a well-known sputtering method and processed using well-known photolithography and etching techniques. In this embodiment, a well-known sputter cleaning process is used to clean the surface of the lower wiring.

In this embodiment, the bottom and sidewall surfaces of the first layer wiring 30 are always adhered to the base insulating film 20, and the adhesive force between the first layer wiring and the base has sufficient strength.

Therefore, the first layer wiring may peel off during manufacturing.

No more sagging problems. In addition, in this example, 1
We achieved the first M wiring with a width of approximately 1 μm and a height of approximately 2 μm, but
Furthermore, the same effect was obtained when forming wiring with a large aspect ratio.

Note that this embodiment is an example of a two-layer wiring structure.

It goes without saying that the present invention can be applied to arbitrary lower layer wiring and upper layer wiring even in the case of a multilayer wiring structure having more than that.

Embodiment 2 FIGS. 2(a) to 2(d) are schematic cross-sectional views showing another embodiment of the wiring structure and manufacturing process of the present invention. This embodiment differs greatly from the previous embodiment 1 in that the contact hole connecting the conductor layers is shifted from the first wiring. Further, the underlying insulating film material, the structure of the first layer wiring, the method of forming the second M wiring, and especially the cleaning treatment before deposition are different.

Other structures and manufacturing steps are the same as in Example 1.

First, as shown in FIG. 2(a), on a silicon substrate lO,
A silicon dioxide film 21 with a thickness of approximately 1 μm and a polyimide resin film 22 having predetermined uneven steps are formed. These films were formed by the same method as shown in Example 1, with the silicon dioxide film being formed by the CVD method and the polyimide film being formed by the spin coating method. The processing of the polyimide film was also carried out in Example 1 above.
As in the case of 02 plasma, the shape of the groove width was 2 μm. Then silicon 31. Aluminum 32. A first circumferential trench layer consisting of a three-layer structure of silicon 33 is deposited over the entire surface. The silicon films 31 and 33 were each formed to a thickness of 20 Onm by plasma CVD. For this deposition, the mixed gas of SSiH430SCC and HzlSCCM was maintained at a pressure of 0.3 Torr, and the substrate temperature was 3.
50℃ 1 frequency 13.56MHy, 0.2W/c+m
Plasma discharge was generated using a high-frequency power of 0.0%.Aluminum [32] was formed by LPCVD using TIBAL as the main raw material in the same manner as in Example 1.
A thickness of 6 μm was deposited.

Next, processing is carried out under conditions such that only the stepped sidewall portions of the three-layer conductive layer remain, as shown in FIG. 4(b).

First PR wirings 31, 32, and 33 were formed. Next, the same figure (
As shown in c), as in Example 1, an interlayer insulating film 40 made of polyimide resin was formed to a thickness of about 3 μm, and then predetermined contact holes 50 were formed to serve as connections between conductor layers.

In this example, the contact hole is shifted from above the first layer wiring pattern, and a part of the upper surface and a part of the side wall surface of the first layer AQ wiring are exposed in the contact hole.

Next, as shown in FIG. 2(d), a second layer wiring 6o was formed. The details are described below. The substrate after forming contact holes as shown in FIG. 3(c) is placed in a sputtering apparatus having a plasma generation mechanism. First, SFe gas was introduced and the pressure was set to 0, I Torr, and then the frequency of 13.56 MIIz, 0, 4 W/cr was applied to the substrate.
a'' is applied to the first contact hole 50.
The silicon film 31 on the side wall portion of the layer Jul wiring 32 was removed by etching. After that, the inside of the vacuum container is evacuated once, and A
After introducing r gas and carrying out the same cleaning as in the case of SFe gas as described above, an AM film of about 1 μm was deposited by a normal sputtering method. Thereafter, the AQ film was patterned using a conventional photolithography technique and dry etching method to form a second layer wiring 60.

According to this embodiment, even if the contact hole is formed offset from the top of the first layer wiring, the contact surface between the top surface and side wall surface of the first layer wiring exposed in the contact hole and the second layer wiring is It exhibits extremely good conduction characteristics and is effective in reducing contact resistance.

In this example, silicon was used as the sidewall material of the first layer wiring, but other materials such as molybdenum and tungsten may be used as long as they can be removed by etching with neutral radicals in gas plasma. However, it shows similar effects.

Further, the sidewall material formed on the lower wiring is not limited to a conductive RTX material, and any material that does not contain oxygen, that is, a material that does not oxidize the surface of the wiring material, will have the same effect as this embodiment. Note that SiN formed by plasma CV IJ method
Good results were also obtained when the membrane was used as the sidewall material.

Further, in this embodiment, the first
Although all of the silicon film 31 on the surface of the layer wiring was removed by etching, it is not necessarily necessary to remove all of the silicon layer, and if a heat treatment step is performed later, the etching amount may be sufficient to remove only a portion of the surface.

In addition, in this example, S
Although silicon was removed by plasma etching using Fe gas, a similar effect was obtained by etching using a gas containing fluorine while irradiating ultraviolet rays.

Furthermore, a method using hydrogen plasma was also effective for etching silicon.

Furthermore, in this embodiment, a structure is adopted in which silicon layers are attached to both side walls of the first layer wiring. However, even when the silicon layer is provided only within one side wall of the first layer wiring, the same effect can be obtained, although there are some restrictions on the latitude in designing the layout of the contact holes. In this embodiment, a two-layer wiring structure is used as an example, but it goes without saying that the present invention can be applied to arbitrary lower-layer wiring and upper-layer wiring even when creating a multi-layer wiring structure.

〔Effect of the invention〕

According to the present invention, fine wiring and wiring with a large aspect ratio can be stably provided without the wiring being bent or peeled off when the wiring is formed. In addition, in the interlayer connection part of a multilayer wiring structure, it is possible to obtain a contact with good conductivity between the upper layer wiring and the upper surface and side wall surface of the lower layer wiring, so misalignment between the contact hole and the lower layer wiring can be tolerated. can do. Therefore, the present invention makes it possible to reduce the designed wiring pitch of an integrated circuit, and is effective in improving the degree of integration.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view showing one embodiment of the wiring structure of the present invention and its manufacturing process, FIG. 2 is a schematic cross-sectional view showing another embodiment, and FIG. It is a cross-sectional schematic diagram. 10... Silicon substrate, 20, 21. 22... Base insulating film, 30, 31, 32, 33... First Fl wiring. 40... Interlayer insulating film, 50... Contact hole, 60
...Second layer wiring. Nest/I! 1 (ku) (b, 1 2nd ward 3rd offender

Claims (1)

[Claims] 1. On the substrate, a lower insulating film, a first layer wiring, an interlayer insulating film,
In a multilayer wiring in which second layer wiring is sequentially formed, at least one layer of wiring among the first layer wiring or the second or higher layer wiring is arranged in a direction different from the main plane direction of the substrate.
It consists of a structure that combines more than one type of conductive material, or in the case of two or more types of compound materials such as insulators, and at the connection between wiring layers, at least a part of the surface or side surface of the lower layer wiring is connected to the upper layer wiring. A multilayer wiring structure characterized by being in contact with. 2. Among the constituent materials of the first-layer wiring or lower-layer wiring, materials provided in the outermost region such as silicon, tungsten, their compounds, or their nitrogen compounds can be used to remove neutral radicals in gas plasma or The multilayer wiring structure according to claim 1, wherein the multilayer wiring structure can be removed by etching (hereinafter referred to as vapor phase etching method) using a reactive group in a gas. 3. (a) forming a lower insulating film having a predetermined step on the surface of the substrate; (b) forming a layer of two or more materials containing at least one conductive material on the entire surface of the lower insulating film including the step; (c) forming a lower layer interconnect and an upper layer interconnect at a predetermined location by removing two or more types of conductive materials in areas other than the step portion of the lower layer insulating film to form a lower layer interconnect having a predetermined pattern; (d) cleaning the surface of the lower layer wiring exposed in the connection hole; (e) forming an upper layer wiring having a predetermined pattern. 1. A method for manufacturing a multilayer wiring structure, comprising at least the following. 4. The step of cleaning the surface of the lower wiring is performed by reactive gas plasma or gas etching in a reactive gas atmosphere under conditions that allow etching not only the upper surface but also the side surfaces of the wiring. 4. A method of manufacturing a multilayer wiring structure according to claim 3, comprising: