JPH02168625A - Multilayer wiring structure body and its manufacture - Google Patents
Multilayer wiring structure body and its manufactureInfo
- Publication number
- JPH02168625A JPH02168625A JP28186288A JP28186288A JPH02168625A JP H02168625 A JPH02168625 A JP H02168625A JP 28186288 A JP28186288 A JP 28186288A JP 28186288 A JP28186288 A JP 28186288A JP H02168625 A JPH02168625 A JP H02168625A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gold
- wiring
- forming
- pillar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010931 gold Substances 0.000 claims abstract description 136
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 135
- 229910052737 gold Inorganic materials 0.000 claims abstract description 135
- 239000010410 layer Substances 0.000 claims abstract description 44
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 38
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 37
- 239000010937 tungsten Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229920001721 polyimide Polymers 0.000 claims abstract description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000011248 coating agent Substances 0.000 claims abstract description 15
- 238000000576 coating method Methods 0.000 claims abstract description 15
- 238000004544 sputter deposition Methods 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000011733 molybdenum Substances 0.000 claims abstract description 10
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 48
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- 238000009713 electroplating Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 abstract description 9
- 239000000126 substance Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 154
- 239000010936 titanium Substances 0.000 description 25
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 20
- 229910052719 titanium Inorganic materials 0.000 description 20
- 238000005530 etching Methods 0.000 description 16
- 239000007789 gas Substances 0.000 description 14
- 239000010409 thin film Substances 0.000 description 14
- 238000001020 plasma etching Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000010884 ion-beam technique Methods 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層金属配線構造体及びその製造方法に関し
、特に、各層配線間に金の接続柱を有する金配線、又は
、タングステン膜又は、モリブデン膜で被覆された金の
接続柱と金配線を有する高信頼性多層微細金配線構造体
及び、その製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer metal wiring structure and a method for manufacturing the same, and in particular, to a multilayer metal wiring structure and a method for manufacturing the same. The present invention relates to a highly reliable multilayer fine gold wiring structure having gold connection posts and gold wiring coated with a molybdenum film, and a method for manufacturing the same.
従来、この種の各層配線間に接続柱を有する多層配線技
術として、例えばＡｎ配線の場合には、第５図に示すよ
うに、まず、基板５０１上にＡ［配線となる第１のＡｕ
膜（Ｃｕ含有）５０２．ＡＡ模膜エツチング時バリアと
なる第１のＷ膜（Ｔｉ含有）５０３．Ａｕ２柱となる第
２のＡｉ膜（Ｃｕ含有）５０４．Ａｆｆｌ膜エツチング
時のバリアとなる第２のＷ膜（Ｔｉ含有）５０５を連続
的にスパッタ形成する（第５図（ａ））。Conventionally, as a multilayer wiring technology having connection pillars between wiring layers of this kind, for example, in the case of An wiring, as shown in FIG.
Membrane (Cu-containing) 502. First W film (containing Ti) 503. serves as a barrier during AA pattern etching. Second Ai film (Cu-containing) 504, which becomes two Au pillars. A second W film (containing Ti) 505, which serves as a barrier during etching of the Affl film, is continuously formed by sputtering (FIG. 5(a)).
次に、Ａ１柱５０６となる部分のみを残すべく、フォト
エツチング技術を用いて、第２のＷ膜（Ｔｉ含有）５０
５と第２のＡＩ！膜３０４を選択的、にエツチング除、
去する（第６図（ｂ））。続イテ、Ａｆｆｌ配線５０７
となる部分を残すために、フォトエツチング技術を用い
て、第１のＷ膜（Ｔｉ含有）５０３゜第１のＡＪ２膜５
０２を選択的にエツチング除去することによってＡＡ柱
５０Ｂを有するＡＡ配線５０７が形成される（第５図（
Ｃ））。層間絶縁膜形成と平坦化は、第５図（ｄ）に示
すようにプラズマ化学気相成長シリコン酸化膜５０８と
形成後、フォトレジスト膜５０９を形成し、ＡＩｌ柱上
の部分に開口を設け（第５図（ｅ））、Ａ７柱上のシリ
コン酸化膜をエツチング除去し、ＡＡ柱の上部を露出さ
せる（第５図（ｆ））。さらに、以上の工程をくり返す
ことにより、２層以上の多層ＡＡ配線を形成する方法が
ある（Ｖ−ＭＩＣＣｏｎｆ、 Ｐｒｏｃ、 １９８６
Ｊｕｒｅ９−１０．Ｐ４５０〜４５６）。Next, in order to leave only the portion that will become the A1 pillar 506, a second W film (Ti-containing) 50 is etched using photoetching technology.
5 and the second AI! selectively etching the film 304;
(Fig. 6(b)). Continuation, Affl wiring 507
In order to leave a portion where
02 is selectively etched away, an AA wiring 507 having an AA pillar 50B is formed (see FIG. 5).
C)). Formation and planarization of the interlayer insulating film are performed by forming a silicon oxide film 508 by plasma chemical vapor deposition, forming a photoresist film 509, and making an opening above the Al pillar (as shown in FIG. 5(d)). In FIG. 5(e)), the silicon oxide film on the A7 pillar is removed by etching to expose the upper part of the AA pillar (FIG. 5(f)). Furthermore, there is a method of forming multilayer AA wiring with two or more layers by repeating the above steps (V-MICConf, Proc, 1986
Jure9-10. P450-456).
一方、ＡＪ２配線では、Ａ、Ｉ２ヒロックが発生しやす
く、エレクトロマイグレーション耐性が悪い等の問題が
あることから、バイポーラＬＳＩ等の高電流で使用する
デバイスでは、層間膜としてプラズマ化学気相成長法に
よるシリコン窒化膜とシリコン酸化膜の２層構造を用い
た、２層金メッキ配線が検討されている（Ｓｏｌｉｄ
５ｔａｔｅ Ｔｅｃｈｎｏｌｏｇｙ。On the other hand, AJ2 wiring tends to generate A and I2 hillocks and has problems such as poor electromigration resistance. Therefore, in devices used at high currents such as bipolar LSI, plasma chemical vapor deposition is used as an interlayer film. Two-layer gold-plated wiring using a two-layer structure of silicon nitride film and silicon oxide film is being considered (Solid
5tate Technology.
１２．１９８３．Ｐ１３７）。12.1983. P137).
しかしながら、上述した従来の技術では、Ａｆｌ配線に
おいては、以下のような問題点がある。まず、第１に工
程数が多く複雑になり、高歩留りが望めない。第２に、
Ａβ柱の形成をドライエツチングで行っているが、その
制御性は悪く、微細なＡρ柱の形成は望めず、高密度化
が難しい。さらに、層間膜として用いているプラズマ化
学気相成長シリコン酸化膜は、平坦性が悪いことから、
レジスト膜で平坦化パターニングし、金属柱上部のシリ
コン酸化膜をエツチング除去するため、パターニング時
に、わずかな目金せずれが生じると、平坦性が極端に悪
い部分が発生し、歩留りが低下するという問題がある。However, the above-mentioned conventional technology has the following problems in Afl wiring. First of all, the number of steps is large and complicated, and high yield cannot be expected. Second,
Dry etching is used to form Aβ pillars, but the controllability is poor and formation of fine Aρ pillars cannot be expected, making it difficult to achieve high density. Furthermore, the plasma chemical vapor deposition silicon oxide film used as the interlayer film has poor flatness.
Because planarization is performed using a resist film and the silicon oxide film on the top of the metal pillar is removed by etching, if a slight misalignment of the metal plate occurs during patterning, there will be areas with extremely poor flatness, resulting in a decrease in yield. There's a problem.
また、前述した従来の２層の層間膜構造を有する金メッ
キ配線においては、層間膜がプラズマ化学気相成長法に
よるシリコン窒化膜とシリコン酸化膜の２層構造である
ことからその平坦性は悪く、微細化したときに高歩留り
が得られないという問題がある。Furthermore, in the conventional gold-plated wiring having a two-layer interlayer film structure as described above, the interlayer film has a two-layer structure of a silicon nitride film and a silicon oxide film produced by plasma chemical vapor deposition, so its flatness is poor. There is a problem that a high yield cannot be obtained when miniaturized.
本発明の目的は、上記の問題点を解消した、すなわち、
平坦性に優れ、高歩留り、高信頼性の金メッキ柱を有す
る多層微細金配線構造体及び、その製造方法を提供する
ことにある。The object of the present invention is to solve the above problems, namely:
It is an object of the present invention to provide a multilayer fine gold wiring structure having gold-plated pillars with excellent flatness, high yield, and high reliability, and a method for manufacturing the same.
本発明の高信頼性多層微細金配線構造体は、メッキ法で
形成した金配線と、各層配線間を電気的に接続するため
の、メッキ法で形成した金柱又は、金配線と金柱の表面
が、選択的に形成されたタングステン膜又は、モリブデ
ン膜で覆われた金メッキ配線を有し、さらに、層間絶縁
膜としてポリイミド膜、シリコン含有ポリイミド膜又は
有機シリカ膜等の有機塗布膜、又は、下層に、ブラズマ
化学気相成長法、あるいは、スパッタ法により形成され
た、シリコン窒化膜、又は、シリコン酸化膜をもつ有機
塗布膜を有している。The highly reliable multilayer fine gold wiring structure of the present invention includes gold pillars formed by plating, or a combination of gold wiring and gold pillars, for electrically connecting between gold wiring formed by plating and each layer wiring. The surface has gold-plated wiring covered with a selectively formed tungsten film or molybdenum film, and an organic coating film such as a polyimide film, a silicon-containing polyimide film, or an organic silica film as an interlayer insulating film, or The lower layer has an organic coating film having a silicon nitride film or a silicon oxide film formed by plasma chemical vapor deposition or sputtering.
さらに、本発明の高信頼性多層微細金配線構造体の製造
方法は、素子基板上に絶縁膜を形成後、第１のバリアメ
タルとして、チタン含有タングステン膜、又は、チタン
膜とチタン含有タングステン膜の２層膜をスパッタ法に
より形成する工程と、さらに、厚さ５００〜１０００人
の金薄膜をスパッタ法により形成する工程と、第１のフ
ォトレジスト膜を形成・パターニングする工程と、電解
メッキ法により第１の金配線を形成する工程と、ＣＦ
４等のフッ素系のガスを用いる反応性イオンエツチング
、又は、紫外光を照射することにより、第１のフォトレ
ジスト膜表面を硬化せしめる工程と、次に、第１の金配
線を第１のフォトレジスト膜上に第２のフォトレジスト
膜を形成・パターニングすることにより、第１の金配線
と、第２の金配線との間の電気的導通をとる部分に第１
の開口を設ける工程と、続いて、電解メッキ法により第
１の開口部に金を析出せしめ、金柱を形成する工程と、
熱処理により、下層金配線と金柱との接着性を向上せし
める工程と、続いて０□プラズマを用いて、第１のフォ
トレジスト膜と、第２のフォトレジスト膜を同時に灰化
せしめる工程と、イオンミリング又は、反応性イオンビ
ームエツチング等により、第１の金配線部以外の金薄膜
とバリアメタルを除去することによって、上部に金メッ
キ柱を有する金配線を形成する工程と、又は、金メッキ
柱を有する第１の金配線表面にのみに化学気相成長法に
より選択的タングステン膜又はモリブデン膜を形成する
ことによって表面にタングステン膜又はモリブデン膜を
有する、上部に金メッキ柱を有する第一の金配線を形成
する工程と、続いて、ポリイミド膜、又は、シリコン含
有ポリイミド膜、又は、有機シリカ膜等の有機塗布膜を
形成する工程、又は、下層にプラズマ化学気相成長法、
あるいは、スパッタ法により、シリコン窒化膜、又は、
シリコン酸化膜を形成した後に、有機塗布膜を形成する
工程と、該層間絶縁膜をエッチバッグせしめることによ
って、金メッキ柱上部又は、金メッキ柱上部のタングス
テン膜表面又は、モリブデン膜表面を露出せしめる工程
と、続いて、第２のバリアメタルの形成以降の工程をく
り返すことによって、第２の金配線を形成する工程と、
さらに同様な工程により多層化された、金配線を形成す
る工程とを有している。Furthermore, in the method of manufacturing a highly reliable multilayer fine gold wiring structure of the present invention, after forming an insulating film on an element substrate, a titanium-containing tungsten film, or a titanium film and a titanium-containing tungsten film are used as the first barrier metal. A step of forming a two-layer film by sputtering, a step of forming a thin gold film with a thickness of 500 to 1000 by sputtering, a step of forming and patterning a first photoresist film, and an electrolytic plating method. a step of forming a first gold wiring by CF
A step of hardening the surface of the first photoresist film by reactive ion etching using a fluorine-based gas such as No. 4 or by irradiating with ultraviolet light; By forming and patterning a second photoresist film on the resist film, a first photoresist film is formed on a portion that establishes electrical continuity between the first gold wiring and the second gold wiring.
a step of forming an opening, followed by a step of depositing gold in the first opening by electrolytic plating to form a gold pillar;
A step of improving the adhesion between the lower gold wiring and the gold pillar by heat treatment, followed by a step of simultaneously ashing the first photoresist film and the second photoresist film using 0□ plasma, A process of forming a gold wiring having a gold-plated pillar on the top by removing the gold thin film and barrier metal other than the first gold wiring part by ion milling or reactive ion beam etching, or forming a gold-plated pillar on the top of the gold wiring. By selectively forming a tungsten film or a molybdenum film only on the surface of the first gold wiring by chemical vapor deposition, a first gold wiring having a tungsten film or a molybdenum film on the surface and having a gold-plated pillar on the top thereof is formed. and then a step of forming an organic coating film such as a polyimide film, a silicon-containing polyimide film, or an organic silica film, or a plasma chemical vapor deposition method on the lower layer,
Alternatively, a silicon nitride film or
After forming the silicon oxide film, a step of forming an organic coating film, and a step of exposing the top of the gold plating pillar or the surface of the tungsten film or the molybdenum film on the top of the gold plating pillar by etching back the interlayer insulating film. , followed by a step of forming a second gold wiring by repeating the steps after forming the second barrier metal;
Furthermore, the method includes a step of forming multilayered gold wiring through similar steps.
すなわち、本発明は下層金配線形成時に金メッキのマス
クとなるフォトレジスト膜を、メッキ後に除去すること
なく、該フォトレジスト膜表面を、ＣＦ４を用いる反応
性イオンエツチングにより、もしくは紫外光を照射する
ことにより硬化させた後に、該フォトレジスト膜と金配
線上フォトレジスト膜を形成・パターニングし、下層金
配線上に開口を設け、再び金メッキを行うことによって
、下層金配線上に金メッキ柱を形成し、０□プラズマ処
理により、フォトレジスト膜を完全に除去した後に、金
配線部以外の金薄膜、バリアメタルを除去することによ
って、上部に金メッキ柱を有する第１の金配線、又は金
配線と金メッキ柱の表面に選択的にタングステン膜又は
、モリブデン膜を形成し、ポリイミド樹脂膜、又は、シ
リコン含有ポリイミド膜、又は、有機シリカ膜等の塗布
膜、又は、下層にプラズマ化学気相成長法、あるいは、
スパッタ法により、シリコン窒化膜、又は、シリコン酸
化膜を有する該塗布膜を形成し、エッチバックせしめる
ことによって金メッキ柱上部又は、該金メッキ柱上部又
は、該金メッキ柱上部のタングステン膜、又は、モリブ
デン膜の表面を露出せしめ、第２の金配線を形成する。That is, the present invention enables the surface of the photoresist film to be subjected to reactive ion etching using CF4 or irradiated with ultraviolet light without removing the photoresist film that serves as a mask for gold plating when forming the lower layer gold wiring after plating. After curing, form and pattern the photoresist film and the photoresist film on the gold wiring, provide an opening on the lower gold wiring, and perform gold plating again to form a gold-plated pillar on the lower gold wiring, 0□ After the photoresist film is completely removed by plasma treatment, the gold thin film and barrier metal other than the gold wiring portion are removed to form the first gold wiring having the gold-plated pillar on the top, or the gold wiring and the gold-plated pillar. A tungsten film or a molybdenum film is selectively formed on the surface, and a coating film such as a polyimide resin film, a silicon-containing polyimide film, or an organic silica film is formed, or a plasma chemical vapor deposition method is applied to the lower layer, or
By forming a coating film having a silicon nitride film or a silicon oxide film by a sputtering method and etching it back, a tungsten film or a molybdenum film is formed on the top of the gold-plated pillar or on the top of the gold-plated pillar. A second gold wiring is formed by exposing the surface of the metal.
さらに同様な工程により、多層微細金配線を形成するも
のである。Furthermore, a similar process is used to form multilayer fine gold wiring.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の第１の実施例である、２層金配線構
造体の製造方法の工程断面図である。FIG. 1 is a process sectional view of a method for manufacturing a two-layer gold wiring structure, which is a first embodiment of the present invention.
まず、第１図（ａ）に示すように素子基板１０１上に、
開０１０３を有する絶縁膜１０２を形成し、続いて第１
図（ｂ）に示すように厚さ約１５００人のチタン含有タ
ングステン膜１０４．厚さ約５００人の金薄膜１０５を
スパッタ法により形成し、第１図（Ｃ）に示すように厚
さ約１．５μｍのフォトレジスト膜１０６を形成、パタ
ーニングし、金配線を形成する部分のフォトレジスト膜
１０６を除去する。First, as shown in FIG. 1(a), on the element substrate 101,
An insulating film 102 having an opening 0103 is formed, and then a first insulating film 102 is formed.
As shown in Figure (b), a titanium-containing tungsten film 104 with a thickness of approximately 1500 mm. A thin gold film 105 with a thickness of approximately 500 mm is formed by sputtering, and as shown in FIG. Photoresist film 106 is removed.
次に、第１図（ｄ）に示すように電解メッキ法により、
厚さ１μｍの第１の金メッキ配線１０７を形成する。続
いて、ＣＦ ４ガス流量を３０ＳＣＣＭ。Next, as shown in Figure 1(d), by electrolytic plating,
A first gold-plated wiring 107 with a thickness of 1 μm is formed. Subsequently, the CF4 gas flow rate was increased to 30SCCM.
圧力５Ｐａ、高周波電力４００Ｗなる条件で、１０分間
反応性イオンエツチングを行い、第１図（ｅ）に示すよ
うに、フォトレジスト膜１０６を約０．５μｍの厚さ分
だけエッチバック除去すると同時にフォトレジスト膜１
０６の表面に硬化層１０８を形成する。続いて、第１図
（「）に示すように再び、厚さ約１．５μｍのフォトレ
ジスト膜１０９を形成・パターニングし、第１と第２の
金配線の電気的導通をとるための金柱１１０を電界メッ
キ法により高さ約１μｍで形成する。次に、第１の金配
線１０７と、金柱１１０との接着性向上のための熱処理
を２００℃で３０分間、窒素ガス雰囲気中で行う。続い
て、０２プラズマにより、フォトレジスト膜１０６，１
０８，１０９を同時に灰化除去し、第１図（ｇ）に示す
構造を得る。次に第１図（ｈ）に示すように、イオンミ
リング法により、金メッキ配線のない部分の金薄膜１０
５と、チタン含有タングステン膜１０４を除去すること
により、金柱を有する第１の金配線が形成される。Reactive ion etching was performed for 10 minutes under the conditions of a pressure of 5 Pa and a high frequency power of 400 W, and as shown in FIG. Resist film 1
A hardened layer 108 is formed on the surface of 06. Subsequently, as shown in FIG. 1 ( ), a photoresist film 109 with a thickness of about 1.5 μm is again formed and patterned to form a gold pillar for electrically connecting the first and second gold wirings. 110 is formed with a height of about 1 μm by electroplating. Next, heat treatment is performed at 200° C. for 30 minutes in a nitrogen gas atmosphere to improve the adhesion between the first gold wiring 107 and the gold pillar 110. .Subsequently, photoresist films 106, 1 are formed using 02 plasma.
08 and 109 are simultaneously incinerated and removed to obtain the structure shown in FIG. 1(g). Next, as shown in FIG. 1(h), the thin gold film 10 in the area where there is no gold-plated wiring is formed by ion milling.
5 and by removing the titanium-containing tungsten film 104, a first gold wiring having gold pillars is formed.
次に、上記形成された金柱を有する第１の金配線上に、
第１図（ｉ）に示すように、ポリイミド膜１１１を厚さ
約２μｍで形成し、ＣＦ、ガス流量５ＳＣＣＭ、 ０２
ガス流量３０ＳＣＣＭ、圧力６Ｐａ、高周波電力３００
Ｗなる条件で、約５分間反応性イオンエツチングにより
全面、エッチバックを行い、金柱１１０の表面が現れる
ようにする。次に、第１図（Ｄに示すように、厚さ約１
５００人のチタン含有タングステン膜１１２．厚さ約５
００人の金薄膜１１３をスパッタ法により形成し、第１
図（ｋ）に示すように厚さ約１．５μｍのフォトレジス
ト膜１１４を形成・パターニングし、第２の金配線を形
成する部分のフォトレジスト膜１１４を除去する。続い
て、電界メッキ法により、厚さ約１μｍの第２の金配線
１１５を形成し、次にフォトレジスト膜１１４を除去し
、第１図（１）の構造を得る。続いて、第２の金配線１
１５のない部分の金薄膜１１３と、チタン含有タングス
テン膜１１２を、イオンミリング法により除去すること
によって、第１図（ｍ）に示すように２層金配線構造体
が形成される。Next, on the first gold wiring having the gold pillars formed above,
As shown in FIG. 1(i), a polyimide film 111 is formed with a thickness of about 2 μm, CF, gas flow rate 5SCCM, 02
Gas flow rate 30SCCM, pressure 6Pa, high frequency power 300
The entire surface is etched back by reactive ion etching for about 5 minutes under W conditions to expose the surface of the gold pillars 110. Next, as shown in Figure 1 (D), the thickness is about 1
500 titanium-containing tungsten films 112. Thickness approx. 5
A gold thin film 113 of 0.00000000000000000000000000000000000000000000000 thin film 113 is formed by sputtering method.
As shown in Figure (k), a photoresist film 114 having a thickness of approximately 1.5 μm is formed and patterned, and the portion of the photoresist film 114 where the second gold wiring is to be formed is removed. Next, a second gold wiring 115 having a thickness of about 1 μm is formed by electrolytic plating, and then the photoresist film 114 is removed to obtain the structure shown in FIG. 1(1). Next, the second gold wiring 1
By removing the portions of the gold thin film 113 and the titanium-containing tungsten film 112 without the portions 15 by ion milling, a two-layer gold wiring structure is formed as shown in FIG. 1(m).
形成された２層金配線構造体の直径的１μｍの金柱と、
第１．第２の金配線との電気的導通な調べたところ、金
柱１本当りの配線抵抗を含む接続抵抗は、０．１〜０．
２Ωであり、その歩留りは９５％以上であった。これは
、実用上、問題ないものであった。A gold pillar with a diameter of 1 μm in the formed two-layer gold wiring structure,
1st. When we investigated the electrical continuity with the second gold wiring, we found that the connection resistance, including the wiring resistance per gold pillar, was 0.1 to 0.
2Ω, and the yield was 95% or more. This was not a problem in practice.
次に、本発明に基づく、第２の実施例について説明する
。第２の実施例では、層間絶縁膜として、プラズマ化学
気相成長シリコン窒化膜と、ポリイミド膜の２層膜を用
いた場合の製造方法を述べる。Next, a second embodiment based on the present invention will be described. In the second embodiment, a manufacturing method will be described in which a two-layer film of a plasma chemical vapor deposition silicon nitride film and a polyimide film is used as an interlayer insulating film.
第２図（ａ）において、第１の実施例で述べた第１図（
ｈ）の工程まで終了した、すなわち、下層にチタン含有
タングステン膜を有する第１の金メッキ配線２０２．金
柱２０３が形成さｈた素子基板２０１上に、厚さ約０．
２μｍのプラズマ化学気相成長シリコン窒化膜２０４を
形成し、続いて、厚さ約２μｍのポリイミド膜２０５を
形成する（第２図（ｂ））。次に、ＣＦ、ガス流量５Ｓ
ＣＣＭ、０２ガス流量３０ＳＣＣＭ、圧力６Ｐａ、高周
波電力３００Ｗなる条件で約５分間、エッチバックした
後、ＣＦ ４ガス流量３０ＳＣＣＭ、圧力５Ｐａ、高周
波電力３００Ｗなる条件で、プラズマ化学気相成長シリ
コン窒化膜２０４をエッチバックすることにより、金柱
２０３の表面が現れるようにする（第２図（Ｃη。続い
て、第１の実施例と同様な工程により、厚さ約１５００
人の第２のチタン含有タングステン膜２０６．厚さ約５
００人の第２の金薄膜２０７をスパッタ法により形成し
く第２図（ｄ））、厚さ約１．５μｍのフォトレジスト
膜２０８を形成、パターニングし、電界メッキ法により
厚さ１．５μｍの第２の金配線２０９を形成する（第２
図（ｅ））。次にフォトレジスト膜２０８を除去し、第
２の金メッキ配線２０９の設けられていない部分の金薄
膜２０７と、チタン含有タングステン膜２０６を、イオ
ンミリング法により順次除去し、第２図（「）に示すよ
うな２層金配線構造体が形成される。In FIG. 2(a), FIG. 1 (
Step h) has been completed, that is, the first gold-plated wiring 202. has a titanium-containing tungsten film in the lower layer. The gold pillars 203 are formed on the element substrate 201 with a thickness of about 0.
A silicon nitride film 204 of 2 μm thick is formed by plasma enhanced chemical vapor deposition, and then a polyimide film 205 of about 2 μm thick is formed (FIG. 2(b)). Next, CF, gas flow rate 5S
After etching back for about 5 minutes under the conditions of CCM, 02 gas flow rate of 30 SCCM, pressure of 6 Pa, and high frequency power of 300 W, plasma chemical vapor deposition silicon nitride film 204 was etched back under the conditions of CF 4 gas flow rate of 30 SCCM, pressure of 5 Pa, and high frequency power of 300 W. By etching back the gold pillar 203, the surface of the gold pillar 203 is exposed (see FIG.
Second titanium-containing tungsten film 206. Thickness approx. 5
A second gold thin film 207 is formed by sputtering (FIG. 2(d)), a photoresist film 208 with a thickness of about 1.5 μm is formed and patterned, and a photoresist film 208 with a thickness of 1.5 μm is formed by electroplating. Forming the second gold wiring 209 (second
Figure (e)). Next, the photoresist film 208 is removed, and the gold thin film 207 and the titanium-containing tungsten film 206 in the areas where the second gold-plated wiring 209 is not provided are sequentially removed by ion milling, as shown in FIG. A two-layer gold wiring structure as shown is formed.
上記形成された２層金配線構造体は、第１の実施例で述
べたと同様に、金柱１本当りの配線抵抗を含む接続抵抗
は、０．１〜０．２Ωであり、歩留りは９５％以上であ
り、実用上、問題のないレベルであった。The two-layer gold wiring structure formed above has a connection resistance of 0.1 to 0.2Ω, including wiring resistance per gold pillar, and a yield of 95Ω, as described in the first example. % or more, which was at a level that caused no problems in practice.
第３図は、本発明の第３の実施例である金メッキ柱と第
１の金配線がタングステン膜で覆われた２層金配線構造
体の製造方法の工程断面図である。FIG. 3 is a process cross-sectional view of a method for manufacturing a two-layer gold wiring structure in which a gold-plated pillar and a first gold wiring are covered with a tungsten film, which is a third embodiment of the present invention.
第３図（ａ）に示すように、素子基板３０１上に開口３
０３を有する絶縁膜３０２を形成し、続いて、第３図（
ｂ）に示すように、厚さ約２０００人のチタン含有タン
グステン膜３０４．厚さ約５００人の金１膜３０５をス
パッタ法により形成し、第３図（ｃ）に示すように、厚
さ約１．５μｍの第１のフォトレジスト膜３０６を形成
・パターニングする。次に、第３図（ｄ）に示すように
、電解メッキ法により、厚さ約１μｍの第１の金メッキ
配線３０７を形成する。続いて、ＣＦ ｔガス流量を３
０ＳＣＣＭ、圧力５Ｐａ、高周波電力４００Ｗなる条件
で２０分間、反応性イオンエツチングを行い、第３図（
ｅ）に示すように、フォトレジスト膜３０６を約０．５
μｍの厚さだけエッチバック除去すると同時に、フォト
レジスト膜３０６表面に硬化層３０８を形成する。続い
て、第３図（ｆ）に示すように再び、厚さ約１．５μｍ
のフォトレジスト膜３０９を形成２パターニングし、第
１と第２の金配線の間の電気的導通をとるための金柱３
１０を、電解メッキにより高さ約１μｍで形成する。As shown in FIG. 3(a), an opening 3 is formed on the element substrate 301.
03 is formed, and then the insulating film 302 having a
As shown in b), a titanium-containing tungsten film 304 with a thickness of approximately 2000 mm. A gold 1 film 305 having a thickness of approximately 500 mm is formed by sputtering, and as shown in FIG. 3(c), a first photoresist film 306 having a thickness of approximately 1.5 μm is formed and patterned. Next, as shown in FIG. 3(d), a first gold-plated wiring 307 having a thickness of about 1 μm is formed by electrolytic plating. Next, increase the CF t gas flow rate to 3
Reactive ion etching was performed for 20 minutes under the conditions of 0 SCCM, pressure 5 Pa, and high frequency power 400 W.
As shown in e), the photoresist film 306 has a thickness of about 0.5
At the same time, a hardened layer 308 is formed on the surface of the photoresist film 306 while etching back a thickness of μm. Subsequently, as shown in FIG. 3(f), the thickness was again about 1.5 μm
A photoresist film 309 is formed and patterned to form a gold pillar 3 for establishing electrical continuity between the first and second gold wirings.
10 is formed with a height of about 1 μm by electrolytic plating.
次に、第１の金配線３０７と金柱３１０との接着性向上
のための熱処理を２００’Ｃで３０分間、窒素ガス雰囲
気中で行う。続いて、０２プラズマにより、フォトレジ
スト膜３０６，３０８，３０９を灰化除去し、第３図（
ｇ）に示す構造を得る。Next, heat treatment is performed at 200'C for 30 minutes in a nitrogen gas atmosphere to improve the adhesion between the first gold wiring 307 and the gold pillar 310. Subsequently, the photoresist films 306, 308, and 309 are removed by ashing using 02 plasma, and as shown in FIG.
Obtain the structure shown in g).
次に、第３図（ｈ）に示すように、反応性イオンビーム
エツチングにより、金メッキ配線３０７のない部分の金
薄膜３０５と、チタン含有タングステン膜３０４を除去
することにより、金柱３１０を有する第１の金配線が形
成される。次に、第３図（ｉ）に示すように化学気相成
長法により、第１の金配線と金柱３１０の表面に選択的
に厚さ約０．２μｍのタングステン膜３１１を形成する
。Next, as shown in FIG. 3(h), the gold thin film 305 and the titanium-containing tungsten film 304 in the areas where the gold-plated wiring 307 is not removed are removed by reactive ion beam etching. 1 gold wiring is formed. Next, as shown in FIG. 3(i), a tungsten film 311 with a thickness of about 0.2 μm is selectively formed on the surfaces of the first gold wiring and the gold pillar 310 by chemical vapor deposition.
この後、第３図（ｊ）に示すように、ポリイミド膜３１
２を厚さ約２μｍで形成し、ＣＦ、ガス流ｊｔ ５ Ｓ
ＣＣＭ、 ０２ガス流量３０ＳＣＣＭ、圧力６Ｐａ、
高周波電力３００Ｗなる条件で約５分間、反応性イオン
エツチングにより、全面エッチバックを行い、金柱３１
０上部のタングステン膜３１１の表面を露出せしめる。After this, as shown in FIG. 3(j), the polyimide film 31
2 with a thickness of about 2 μm, CF, gas flow jt 5 S
CCM, 02 gas flow rate 30SCCM, pressure 6Pa,
The entire surface was etched back by reactive ion etching for about 5 minutes under the condition of high frequency power of 300W, and the gold pillar 31 was etched back.
The surface of the tungsten film 311 above the tungsten film 311 is exposed.
次に、第３図（ｋ）に示すように、厚さ約２０００人の
チタン含有タングステン膜３１３．厚さ約５００人の金
薄膜３１４をスパッタ法により形成し、第３図（１）に
示すように厚さ約１．５μｍのフォトレジスト膜３１５
を形成・パターニングする。続いて、電解メッキ法によ
り、厚さ約１μｍの第２の金配線３１６を形成し、次に
フォトレジスト膜３１５を除去し、第３図（ｍ）の構造
を得る。この後、第２の金配線３１６のない部分の金薄
膜３１４と、チタン含有タングステン膜３１３を、反応
性イオンビームエツチングにより除去することによって
、第３図（ｎ）に示すように、２層金配線構造体が形成
される。Next, as shown in FIG. 3(k), a titanium-containing tungsten film 313 with a thickness of approximately 2000. A thin gold film 314 with a thickness of approximately 500 μm is formed by sputtering, and a photoresist film 315 with a thickness of approximately 1.5 μm is formed as shown in FIG. 3(1).
Forming and patterning. Subsequently, a second gold wiring 316 having a thickness of about 1 μm is formed by electrolytic plating, and then the photoresist film 315 is removed to obtain the structure shown in FIG. 3(m). Thereafter, the gold thin film 314 and the titanium-containing tungsten film 313 in the areas where the second gold wiring 316 is not present are removed by reactive ion beam etching to form a two-layer gold film as shown in FIG. 3(n). A wiring structure is formed.
形成された２層金配線構造体の直径的１μｍの金柱３１
０と、第１．第２の金配線との電気的導通を調べたとこ
ろ、金柱１本当りの接続抵抗（含・配線抵抗）は、０．
１〜０．２Ωであり、その歩留りは９５％以上であり、
実用上、問題のない値である。Gold pillars 31 with a diameter of 1 μm in the formed two-layer gold wiring structure
0 and 1st. When electrical continuity with the second gold wiring was examined, the connection resistance (including wiring resistance) per gold pillar was 0.
1 to 0.2Ω, the yield is 95% or more,
This is a value that poses no problem in practice.
次に、本発明に基づく、第４の実施例について説明する
。第４の実施例では、金メッキ柱と第１の金配線表面が
タングステン膜で覆われ、かつ層間絶縁膜としてプラズ
マ化学気相成長シリコン窒化膜と、ポリイミド膜の２層
膜を用いた場合の製造方法を述べる。Next, a fourth embodiment based on the present invention will be described. In the fourth embodiment, the gold-plated pillar and the first gold wiring surface are covered with a tungsten film, and a two-layer film of a plasma chemical vapor deposition silicon nitride film and a polyimide film is used as an interlayer insulating film. Describe the method.
第４図（ａ）において、第３の実施例で述べた、第３図
（ｈ）の工程まで終了した。すなわち、下層にチタン含
有タングステン膜を有する第１の金メッキ配線４０２．
金メッキ柱４０３が形成された素子基板４０１上に、第
４図（ｂ）に示すように、化学気相成長法により、第１
の金配線と、金柱の表面に選択的に厚さ約０．２μｍの
タングステン膜４０４を形成する。続いて、厚さ約０．
２μｍのプラズマ化学気相成長シリコン窒化膜４０５を
形成し、次に、厚さ約２μｍのポリイミド膜４０６を形
成する（第４図（Ｃ））。続いて、ＣＦ ４ガス流量５
Ｓ ＣＣＭ、 ０２ガス流量３０ＳＣＣＭ、圧力６Ｐ
ａ、高周波電力３００Ｗなる条件で、約５分間、エッチ
バックした後、ＣＦ４ガス流量３０ＳＣＣ！Ｍ。In FIG. 4(a), the process up to FIG. 3(h) described in the third embodiment has been completed. That is, the first gold-plated wiring 402. has a titanium-containing tungsten film in the lower layer.
As shown in FIG. 4(b), a first layer is deposited on the element substrate 401 on which the gold-plated pillars 403 are formed by chemical vapor deposition.
A tungsten film 404 with a thickness of about 0.2 μm is selectively formed on the gold wiring and the surface of the gold pillar. Next, the thickness is about 0.
A silicon nitride film 405 of 2 μm thick is formed by plasma chemical vapor deposition, and then a polyimide film 406 of about 2 μm thick is formed (FIG. 4(C)). Subsequently, CF4 gas flow rate 5
S CCM, 02 gas flow rate 30SCCM, pressure 6P
a. After etching back for about 5 minutes under the condition of high frequency power of 300W, the CF4 gas flow rate was 30SCC! M.
圧力５Ｐａ、高周波電力３００Ｗなる条件で、プラズマ
化学気相成長シリコン窒化膜をエッチバックすることに
より、金柱４０３上部のタングステン膜４０４の表面を
露出せしめる（第４図（す。続いて、第３の実施例と同
様な工程により、厚さ約２０００人の第２のチタン含有
タングステン膜４０７、厚さ５００人の第２の金薄膜４
０８をスパッタ法により形成する（第４図（ｅ））。こ
の後、厚さ約２μｍのフォトレジスト膜４０９を形成・
パターニングし、電解メッキ法により、厚さ約１．５μ
ｍの第２の金配線４１０を形成する（第４図（「水炊に
、フォトレジスト膜４０９を除去し、第２の金メッキ配
線４１０の設けられていない部分の金薄膜４０８と、チ
タン含有タングステン膜４０７を反応性イオンビームエ
ツチングにより順次、除去し、第４図（ｇ）に示すよう
な２層金配線構造体が形成される。The surface of the tungsten film 404 on the top of the gold pillar 403 is exposed by etching back the plasma chemical vapor deposition silicon nitride film under the conditions of a pressure of 5 Pa and a high frequency power of 300 W (see FIG. 4). A second titanium-containing tungsten film 407 with a thickness of approximately 2,000 thick and a second gold thin film 4 with a thickness of 500
08 is formed by sputtering (FIG. 4(e)). After this, a photoresist film 409 with a thickness of approximately 2 μm is formed.
Patterned and electrolytically plated to a thickness of approximately 1.5 μm.
Form a second gold wiring 410 of m (see FIG. 4). 407 is sequentially removed by reactive ion beam etching to form a two-layer gold wiring structure as shown in FIG. 4(g).
上記形成された２層金配線構造体は、第３の実施例で述
べたと同様に、金柱１本当りの配線抵抗を含む接続抵抗
は０．１〜０．２Ωであり、歩留りは９５％以上であり
、実用上、問題のないレベルであった。さらに、作成し
た２層配線構造体の信頼性試験を行った結果は良好であ
り、実用上、特に問題ないことがわかった。The two-layer gold wiring structure formed above has a connection resistance of 0.1 to 0.2Ω, including wiring resistance per gold pillar, and a yield of 95%. The above results were at a level that caused no problems in practical use. Furthermore, the results of a reliability test of the produced two-layer wiring structure were good, and it was found that there were no particular problems in practical use.
以上説明したように、本発明は、下層金メッキ配線形成
時に、マスクとして用いるフォトレジスト膜表面を、Ｃ
Ｆ ４等のフッ素系ガスによる反応性イオンエツチング
を行うことにより、又は、紫外光を照射することにより
硬化せしめることによって、全柱形成時に塗布形成する
フォトレジスト膜と下層フォトレジスト膜との混合が全
くなく、金柱を形成する部分の開口の下部にフォトレジ
スト膜の残査が残るという問題も、全く生じない。As explained above, in the present invention, the surface of the photoresist film used as a mask when forming the lower layer gold-plated wiring is
By performing reactive ion etching with a fluorine-based gas such as F4 or by curing by irradiating with ultraviolet light, the photoresist film that is applied during the formation of all columns and the lower photoresist film can be mixed. There is no problem of photoresist film residue remaining under the opening where the gold pillar is to be formed.
また、全配線部以外の部分にはフォトレジスト膜が残っ
ているため、表面の平坦性は高く、金配線パターンの高
さによらず、均一な金柱の形成が可能である。したがっ
て、歩留りの向上が可能となる。さらに、平坦性に優れ
ていることから、容易に多層化できるという利点も有す
るようになる。Furthermore, since the photoresist film remains on the parts other than all the wiring parts, the surface flatness is high, and uniform gold pillars can be formed regardless of the height of the gold wiring pattern. Therefore, it is possible to improve the yield. Furthermore, since it has excellent flatness, it also has the advantage of being easily multilayered.
また、従来の技術に比べて、工程数の短縮が可能となり
、量産性が高いという利点も有する。Additionally, compared to conventional techniques, it has the advantage of being able to reduce the number of steps and being highly mass-producible.
したがって、本発明は、多層配線構造体を有する、デバ
イスの製造に非常に有益である。Therefore, the present invention is very useful for manufacturing devices having multilayer wiring structures.
第１図（ａ）〜（ｍ）は、本発明に基づく第１の実施例
である２層金配線構造体の製造方法を示す工程断面図、
第２図（ａ）〜（ｆ）は、第２の実施例である２層金配
線構造体の製造方法を示す工程断面図、第３図（ａ）〜
（ｎ）は、本発明に基づく、第３の実施例である２層金
配線構造体の製造方法を示す工程断面図、第４図（ａ）
〜（ｇ）は、第４の実施例である２層金配線構造体の製
造方法を示す工程断面図、第５図（ａ）〜（「）は、従
来の金属柱を有する多層配線構造体の製造方法を示す工
程断面図である。
１０１・・・・・・素子基板、１０２・・・・・・絶縁
膜、１０３・・・・・開口、１０４，１１２・・・・・
・チタン含有タングステン膜、１０５，１１３・・・・
・・金薄膜、１０６゜１０９．１１４・・・・・・フォ
トレジスト膜、１０７・・・・・・第１の金メッキ配線
、１０８・・・・・・フォトレジスト膜表面硬化層、１
１０・・・・・・金柱、１１１・・・・・・ポリイミド
樹脂膜、１１５・・・・・・第２の金メッキ配線、２０
１・・・・・・素子基板、２０２・・・・・・第１の金
メッキ配線、２０３・・・・・・金柱、２０４・・・・
・・プラズマ化学気相成長シリコン窒化膜、２０５・・
・・・・ポリイミド膜、２０６・・・・・・第２のチタ
ン含有タングステン膜、２０７・・・・・・第２の金薄
膜、２０８・・・・・・フォトレジスト膜、２０９・・
・・・・第２の金メッキ配線、３０１・・・・・・素子
基板、３０２・・・・・・絶縁膜、３０３・・・・・・
開口、３０４，３１３・・・・・・チタン含有タングス
テン膜、３０５，３１４・・・・・・金薄膜、３０６，
３０９゜３１５・・・・・・フォトレジスト膜、３０７
・・・・・・第１の金メッキ配線、３０８・・・・・・
フォトレジスト膜表面硬化層、３１０・・・・・・金柱
、３１１・・・・・・タングステン膜、３１２・・・・
・・ポリイミド膜、３１６・・・・・・第２の金メッキ
配線、４０１・・・・・・素子基板、４０２・・・・・
・第１の金メッキ配線、４０３・・・・・・金柱、４０
４・・・・・・タングステン膜、４０５・・・・・・プ
ラズマ化学気相成長シリコン窒化膜、４０６・・・・・
・ポリイミド膜、４０７・・・・・・第２のチタン含有
タングステン膜、４０８・・・・・・第２の金薄膜、４
０９・・・・・・フォトレジスト膜、４１０・・・・・
・第２の金メッキ配線、５０１・・・・・・基板、５０
２・・・・・・第１のＡｆｆｌ膜、５０３・・・・・・
第１のＷ膜（Ｔｉ含有）、５０４・・・・・・第２のＡ
ｎ膜、５０５・・・・・・第２のＷ膜（Ｔｉ含有）、５
０６・・・・・・Ａｌ１柱、５０７・・・・・・ＡＪ２
配線、５０８・・・・・・シリコン酸化膜、５０９・・
・・・・フォトレジスト膜。
代理人 弁理士 内 原 晋
ｌθ／ −−−−＄ｂ林
ｔｏ２ −−−一ψを妹諌
／θ３ −−− Ｅυ
ｔｏＡ、１０’ｌ ／／４−− ”７．ｆ）Ｌレス）斤
丸ＩＩ／
ｔｓ
−−−−全、伎
一−−−−−汀すイぐ゛Ｅ′樹脂狭
−−−−− 慕λつ４計ノソＮヤ痒
第１ ■
第Ｚ
３てフーーーーフィ庫ジにト声（
鄭FIGS. 1(a) to 1(m) are process cross-sectional views showing a method for manufacturing a two-layer gold wiring structure according to a first embodiment of the present invention;
FIGS. 2(a) to 2(f) are process cross-sectional views showing a method for manufacturing a two-layer gold wiring structure according to the second embodiment, and FIGS. 3(a) to 3(f) are
(n) is a process cross-sectional view showing a method for manufacturing a two-layer gold wiring structure according to the third embodiment of the present invention, and FIG. 4(a)
~(g) are process cross-sectional views showing a method for manufacturing a two-layer gold wiring structure according to the fourth embodiment, and FIGS. 101... Element substrate, 102... Insulating film, 103... Opening, 104, 112...
・Titanium-containing tungsten film, 105, 113...
... Gold thin film, 106° 109.114 ... Photoresist film, 107 ... First gold-plated wiring, 108 ... Photoresist film surface hardening layer, 1
10... Gold pillar, 111... Polyimide resin film, 115... Second gold plated wiring, 20
DESCRIPTION OF SYMBOLS 1...Element board, 202...First gold-plated wiring, 203...Gold pillar, 204...
...Plasma chemical vapor deposition silicon nitride film, 205...
... Polyimide film, 206 ... Second titanium-containing tungsten film, 207 ... Second gold thin film, 208 ... Photoresist film, 209 ...
...Second gold-plated wiring, 301...Element substrate, 302...Insulating film, 303...
Opening, 304, 313...Tungsten film containing titanium, 305, 314...Gold thin film, 306,
309°315...Photoresist film, 307
...First gold-plated wiring, 308...
Photoresist film surface hardening layer, 310...Gold pillar, 311...Tungsten film, 312...
... Polyimide film, 316 ... Second gold-plated wiring, 401 ... Element substrate, 402 ...
・First gold-plated wiring, 403...Gold pillar, 40
4...Tungsten film, 405...Plasma chemical vapor deposition silicon nitride film, 406...
・Polyimide film, 407...Second titanium-containing tungsten film, 408...Second gold thin film, 4
09...Photoresist film, 410...
・Second gold-plated wiring, 501...Substrate, 50
2...First Affl film, 503...
First W film (Ti-containing), 504...Second A
n film, 505... Second W film (Ti-containing), 5
06...Al1 column, 507...AJ2
Wiring, 508...Silicon oxide film, 509...
...Photoresist film. Agent Patent Attorney Susumu Uchihara lθ/ −−−−$B Hayashi to2 −−−One ψ to Imouto/θ3 −−− Eυ toA, 10'l //4−− ”7.f) L reply) 斤Maru II / ts -----All, 1------Tails quickly E'resin narrow------ 4 total nosoN Yaitch 1st ■ Part Z 3 Fuuuufi store (Zheng)
Claims (4)
線間を電気的に接続するための金柱、又は、前記金配線
と、前記金柱表面が、選択的に形成されたタングステン
膜、又は、モリブデン膜で覆われた金配線を有し、層間
絶縁膜が、有機塗布膜、又は、下層にプラズマ化学気相
成長法、あるいは、スパッタ法によるシリコン窒化膜又
は、シリコン酸化膜を有する有機塗布膜であることを特
徴とする多層配線構造体(1) In a multilayer wiring structure using gold wiring, a gold pillar for electrically connecting each layer wiring, or a tungsten film selectively formed on the surface of the gold wiring and the gold pillar, or , has gold wiring covered with a molybdenum film, and the interlayer insulating film is an organic coating film, or an organic coating with a silicon nitride film or silicon oxide film formed by plasma chemical vapor deposition or sputtering as the lower layer. Multilayer wiring structure characterized by being a film
する工程と、該金薄膜を有する配線層上に第１のフォト
レジスト膜を形成パターニングする工程と、電解メッキ
法により第１の金配線を形成する工程と、前記第１のフ
ォトレジスト膜表面を硬化せしめる工程と、次に前記第
１の金配線と、前記第１のフォトレジスト膜上に、第２
のフォトレジスト膜を形成、パターニングし、前記第１
の金配線と該第１の金配線上に設けられる第２の金配線
との導通をとる部分に第１の開孔を設ける工程と、続い
て、電解メッキ法により、前記第１の開口部に金を析出
せしめ金柱を形成する工程と、続いて、前記第１と第２
のフォトレジスト膜を除去する工程と、続いて層間絶縁
膜として有機塗布膜を形成する工程又は、下層にプラズ
マ化学気相成長法あるいは、スパッタ法により、シリコ
ン窒化膜又は、シリコン酸化膜を形成した後に、有機塗
布膜を形成する工程とを有することを特徴とする多層配
線構造体の製造方法(2) A step of forming a wiring layer having a metal film on the surface on the element substrate, a step of forming and patterning a first photoresist film on the wiring layer having the thin gold film, and a step of forming the first photoresist film by electrolytic plating. A step of forming a gold wiring, a step of hardening the surface of the first photoresist film, and then a step of forming a second gold wiring on the first gold wiring and the first photoresist film.
A photoresist film is formed and patterned, and the first photoresist film is formed and patterned.
forming a first opening in a portion that establishes conduction between the gold wiring and the second gold wiring provided on the first gold wiring, and then forming the first opening by electrolytic plating. a step of depositing gold to form a gold pillar;
A step of removing the photoresist film, followed by a step of forming an organic coating film as an interlayer insulating film, or forming a silicon nitride film or a silicon oxide film as the lower layer by plasma chemical vapor deposition or sputtering. A method for manufacturing a multilayer wiring structure, comprising the step of subsequently forming an organic coating film.
コン含有ポリイミド膜又は有機シリカ膜であることを特
徴とする多層配線構造体(3) A multilayer wiring structure characterized in that the organic coating film according to claim 1 is a polyimide film, a silicon-containing polyimide film, or an organic silica film.
リコン含有ポリイミド膜又は有機シリカ膜であることを
特徴とする多層配線構造体の製造方法(4) A method for producing a multilayer wiring structure, wherein the organic coating film according to claim 2 is a polyimide film, a silicon-containing polyimide film, or an organic silica film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63281862A JPH07109828B2 (en) | 1988-09-14 | 1988-11-07 | Method for manufacturing multilayer wiring structure |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63-232028 | 1988-09-14 | ||
| JP23202888 | 1988-09-14 | ||
| JP63281862A JPH07109828B2 (en) | 1988-09-14 | 1988-11-07 | Method for manufacturing multilayer wiring structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02168625A true JPH02168625A (en) | 1990-06-28 |
| JPH07109828B2 JPH07109828B2 (en) | 1995-11-22 |
Family
ID=26530248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63281862A Expired - Lifetime JPH07109828B2 (en) | 1988-09-14 | 1988-11-07 | Method for manufacturing multilayer wiring structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07109828B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211144A (en) * | 1991-12-27 | 1993-08-20 | Nec Corp | Semiconductor device and its manufacture |
| JP2005159326A (en) * | 2003-11-04 | 2005-06-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153149A (en) * | 1984-01-23 | 1985-08-12 | Matsushita Electric Ind Co Ltd | Formation of multilayer interconnection |
| JPS62259459A (en) * | 1986-05-02 | 1987-11-11 | Sumitomo Electric Ind Ltd | Method for multilayer interconnection |
| JPH01208842A (en) * | 1988-02-16 | 1989-08-22 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH01211946A (en) * | 1988-02-18 | 1989-08-25 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1988
- 1988-11-07 JP JP63281862A patent/JPH07109828B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60153149A (en) * | 1984-01-23 | 1985-08-12 | Matsushita Electric Ind Co Ltd | Formation of multilayer interconnection |
| JPS62259459A (en) * | 1986-05-02 | 1987-11-11 | Sumitomo Electric Ind Ltd | Method for multilayer interconnection |
| JPH01208842A (en) * | 1988-02-16 | 1989-08-22 | Nec Corp | Manufacture of semiconductor integrated circuit device |
| JPH01211946A (en) * | 1988-02-18 | 1989-08-25 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211144A (en) * | 1991-12-27 | 1993-08-20 | Nec Corp | Semiconductor device and its manufacture |
| JP2005159326A (en) * | 2003-11-04 | 2005-06-16 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07109828B2 (en) | 1995-11-22 |
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