JPH05243217A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a highly reliable interconnection by making the interconnection fine and by improving the cross sectional shape of the interconnection, in the metal plating interconnection forming technology. CONSTITUTION:A fine resist pattern is formed with an upper resist 105 by utilizing the three-layer structure of the upper layer resist 105. The pattern is then transferred to an intermediate layer 104 and a lower resist 103 in this order by dry etching. Then, with the intermediate layer and the lower-layer resist being used as a mask, a metal plating interconnection is formed. By this method, the thickness of the resist film can be thin at the time of formation of the upper-layer resist pattern and thereby a fine pattern can be formed. Moreover, since a rectangular resist formed by dry etching is used as a plating mask, the cross sectional shape of the interconnection is rectangular. Consequently, fineness and reliability of the interconnection, can be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming fine metal plated wiring used in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor devices has increased, a technique for forming fine wiring with high reliability has become more important. At present, in the commonly used aluminum wiring, deterioration of reliability due to electromigration and stress migration has become a serious problem with miniaturization. As a method of solving this, a fine gold wiring forming technique using gold as a wiring material has been attracting attention.

In the conventional gold wiring forming method in this technique, as shown in FIG. 3A, a gold thin film 302 is first formed on the upper surface of a semiconductor substrate 301 having an element region by a sputtering method.
And then a photoresist pattern 303 is formed on the upper surface thereof by using a normal photolithography method.
A heat treatment at about 20 ° C. to 130 ° C. (hereinafter referred to as baking) is performed. After that, as shown in FIG. 3B, the gold wiring 304 is selectively formed by electrolytic plating using the photoresist pattern 303 as a mask. In this gold plating process, the gold thin film 302 serves as a power supply layer for ensuring a current path. The above-mentioned baking process is for improving the adhesion between the photoresist and gold and for preventing the deformation of the photoresist during plating. next,
The unnecessary photoresist pattern 303 is removed using an organic solvent or oxygen plasma (FIG. 3C), and as shown in FIG. 3D, wet etching using aqua regia or argon (Ar). ) And the like, the exposed portion of the gold thin film 302 is removed by sputtering using an ion beam, and the gold wirings 304 are separated from each other to complete the wiring formation process. At this time, since the gold wiring 304 is also etched at the same time, the film thickness thereof is reduced by the amount corresponding to the gold thin film 302.

[0004]

The thickness of the gold wiring is generally about 2 μm because it is necessary to secure the reliability of the wiring. Therefore, in the gold plating process, the film thickness is more than that. It is necessary to use a thick photoresist (usually about 2.5 μm or more) to separate the gold wirings. This photoresist film thickness is a film thickness used in other manufacturing processes of semiconductor devices (usually 1.0 to 1.5 μm).
It is characterized by being much thicker than.

As a result, in the conventional gold wiring forming method, in the photolithography process for forming the photoresist pattern, the resolution is lowered and the pattern cross-sectional shape is deteriorated due to the thicker film (the shape is not a rectangle but a forward taper shape). There was a problem that. Further, if the above-mentioned baking process is performed, the photoresist pattern is thermally deformed, and the sectional shape thereof is further deteriorated.

Therefore, in the conventional gold wiring forming method using such a photoresist pattern as a gold plating mask, firstly, a fine wiring pattern is not formed. Second, since the cross-sectional shape of the wiring pattern is inversely tapered, it is easy to collapse due to physical impact in the subsequent insulating film forming process between the wiring layers, and the insulating film can sufficiently cover this step. However, there is a drawback that a void is formed under the wiring pattern and the reliability of the wiring is impaired.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a metal conductive film serving as a current path for electroplating on a semiconductor substrate including an element region, and an organic film formed on the metal conductive film. A step of coating and forming a film, a step of forming an intermediate layer made of an inorganic material on the organic film, a step of applying a photoresist film on the intermediate layer and then forming a photoresist pattern, A step of selectively removing the intermediate layer by dry etching using a photoresist pattern as a mask; a step of selectively removing the organic film by dry etching using the photoresist pattern and the intermediate layer as a mask; And a step of forming a metal plating film by electrolytic plating using the organic film as a mask.

[0008]

The present invention will be described below with reference to the drawings. 1A to 1E are cross-sectional views in order of steps for explaining a method for forming a fine metal-plated wiring according to the first embodiment of the present invention.

First, as shown in FIG. 1A, a gold thin film 102 of about 30 to 100 nm (nanometer) is deposited on the upper surface of a semiconductor substrate 101 having an element region by sputtering, and a lower layer photoresist 103 is further formed on the upper surface. Is spin coated to a film thickness of about 2.5 μm. As the lower layer photoresist 103, for example, a novolac resin type photoresist such as OFPR-800 manufactured by Tokyo Ohka Kogyo Co., Ltd. or PF-7400 manufactured by Sumitomo Chemical Co., Ltd. is used, but it is not always necessary that the photoresist has photosensitivity. Without
Only the resin from which the photosensitizer has been removed may be used. Further, this film thickness may be any as long as it is equal to or larger than that of the gold wiring to be formed.

Next, after heat-treating at a temperature of about 200 ° C. for about 1 hour to cure the photoresist layer, a silica film containing silicon oxide as a main component is formed to a film thickness of 100 to 200.
spin coating is carried out to a thickness of 80 nm and heat treatment at 80 to 200 ° C. is carried out again for 2 to 3 hours to form the intermediate layer 104. After that, an upper layer photoresist is applied, exposed, and developed according to a normal photolithography method to form an upper layer resist pattern 105. At this time, the film thickness of the upper layer resist is the film thickness (2.5 μm) used in the conventional gold wiring forming technology.
(m or more) to about 0.5 μm.
In this photolithography process, the resolution is improved and the pattern cross-sectional shape close to a rectangle can be obtained when the film thickness of the photoresist is thin, and thus a finer upper layer resist pattern 105 can be obtained as compared with the conventional case.

Next, using the upper resist pattern 105 as a mask, mainly a chlorofluorocarbon gas (for example, CF ₄ , C) is used.
The intermediate layer 10 is formed by dry etching using HF ₃ ).
4 is selectively removed by etching. Subsequently, the upper layer resist pattern 105 and the intermediate layer 104 selectively formed.
Is used as an etching mask, and the lower layer resist 103 is formed by dry etching mainly containing oxygen plasma.
Are selectively removed (FIG. 1 (b)). At this time, since the upper layer resist pattern 105 is etched in oxygen plasma and disappears, the intermediate layer 104 remains as it is because it has sufficient resistance. The pattern side surface of the lower layer resist 103 is extremely steep and has a rectangular cross-sectional shape due to the characteristics of dry etching.

Thereafter, as shown in FIG. 1 (c), this sample was placed on the negative electrode side in the electrolyte solution containing sulfuric acid, sodium gold gold sulfate, and phosphoric acid as the main components according to the conventional gold plating technique. The small pieces covered with platinum are placed on the positive electrode side respectively, and gold plating is performed for about 20 minutes to form the gold wiring 106 having a film thickness of about 2 μm. The cross-sectional shape of the gold wiring 106 is rectangular rather than the reverse taper shape as in the prior art because the lower layer resist 103 that serves as a plating mask has a rectangular cross-sectional shape.

Next, the unnecessary intermediate layer 104 is removed by using hydrofluoric acid or the above-mentioned fluorocarbon gas, and the lower layer resist 103 is removed by an organic solvent or oxygen plasma (FIG. 1 (d)). ..

Finally, as shown in FIG. 1E, the gold wiring 10 is formed by wet etching using aqua regia or sputtering using an ion beam such as argon as in the conventional method.
The gold thin film 102 in the region not covered by 6 is removed to separate the gold wiring 106.

As described above, in the conventional method, since the photoresist pattern itself formed in the photolithography process is used as a mask for gold plating, it is necessary to make the thickness of the photoresist larger than that of the gold wiring. As a result, resolution and cross-sectional shape were deteriorated, and a fine pattern could not be formed. However, according to the method for forming a fine metal-plated wiring of the present invention, it is not the photoresist pattern itself but 2 Since the subsequently formed pattern is used as a gold plating mask, it is not necessary to increase the film thickness of the photoresist in the photolithography process. Therefore, a fine pattern with good resolution can be formed. Furthermore, by the dry etching method based on this fine pattern, the film thickness is thicker than the gold wiring, and
Since the second photoresist pattern having a rectangular cross-sectional shape is formed and used as a gold plating mask, rectangular fine gold wiring can be formed.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a part of a process cross-sectional view for explaining a method of forming a fine metal plated wiring according to a second embodiment of the present invention.

First, as shown in FIG. 2, a gold thin film 202 and a lower layer photoresist 203 are sequentially formed on the upper surface of a semiconductor substrate 201 having an element region by the same method as in the first embodiment, and then at about 200 ° C. Heat treatment is performed for about an hour, and the silicon layer 204 is deposited by a sputtering method so that the film thickness is about 100 to 200 nm. After that, the upper layer resist pattern 205 is formed, the silicon layer 204 and the lower layer resist 20 are formed according to the same manufacturing method as that of the first embodiment.
A gold wiring pattern is formed through the selective etching of 3, the gold plating, and the partial removal of the gold thin film 202. However, in the above steps, as a method of removing the unnecessary silicon layer 204, a mixed solution of nitric hydrofluoric acid and glacial acetic acid is used instead of hydrofluoric acid, which is different from the previous example.

In this example, a silicon layer is used as the material of the intermediate layer, but since it has sufficient resistance to the oxygen plasma used when etching the lower layer resist, it is possible to form a rectangular lower layer resist pattern. Since it can be done, there is no functional problem and the same effect as the previous example can be obtained.

[0019]

As described above, according to the present invention, the photoresist pattern formed in the photolithography process and the photoresist pattern used as the plating mask in the gold plating process are separately formed. It is not necessary to make the photoresist film thickness thicker than a predetermined gold wiring film thickness. Therefore, the film thickness can be significantly reduced as compared with the conventional one, and as a result, the resolution can be improved and a fine photoresist pattern can be formed. Further, in the gold plating step, since a photoresist pattern having a rectangular cross-sectional shape formed by dry etching based on the above-mentioned fine photoresist pattern is used as a plating mask, the cross-sectional shape of the gold wiring is different from the conventional one. It can be rectangular.

Therefore, the strength of the gold wiring against a physical impact is improved, and the step coverage of the insulating film is improved in the subsequent wiring interlayer insulating film forming step, so that no void is generated. Therefore, the present invention has an effect that it can provide a method of forming a highly reliable fine plated wiring that is strong against physical impact and has no void of an insulating film in the wiring layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a method of forming a fine metal plated wiring according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a process sectional view of a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing method of a conventional technique in the order of steps.

[Explanation of symbols]

 101, 201, 301 Semiconductor substrate 102, 202, 302 Gold thin film 103, 203 Lower layer resist 104 Intermediate layer 105, 205 Upper layer resist pattern 106, 304 Gold wiring 204 Silicon layer 303 Photoresist pattern

Claims (1)

[Claims] 1. A step of forming a metal conductive film serving as a current path for electroplating on a semiconductor substrate including an element region, a step of applying an organic film on the metal conductive film, and forming the metal conductive film on the organic film. A step of forming an intermediate layer made of an inorganic material, a step of applying a photoresist film on the intermediate layer and then forming a photoresist pattern, and selecting the intermediate layer by dry etching using the photoresist pattern as a mask. Removing step, a step of selectively removing the organic film by dry etching using the photoresist pattern and the intermediate layer as a mask, and a metal plating film is formed by electrolytic plating using at least the organic film as a mask And a step of manufacturing the semiconductor device.