JPH0897214A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To improve adhesion, barrier performance, and flatness of an aperture part like a through hole which connects a wiring of a multilayered film structure with a conducting region of a lower layer. CONSTITUTION: After a through hole 4a for connecting wirings is formed, a sticking barrier metal film 5a and a Ti film 22 are sequentially deposited. After a mask member 23a is formed in only the inside of the through hole 4a, the exposed Ti film 22a is changed into a titanium oxide film 24. The mask member 23a is eliminated, and the inner part of the through hole 4 is filled in the self alignment manner by nonelectrolytic plating. Buried Au 25 is formed, and the surface is flattened. The titanium oxide film 24 which has become unnecessary and the Ti film left below the titanium oxide film 24 are eliminated by etching, the barrier metal film is exposed, and an Au film 7c as the next layer is formed by an electrolytic plating method while the exposed barrier metal film 5a is used as a power supply path, Thereby, generation of a cavity in the through hole can be prevented, and flatness of a wiring can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a wiring forming method.

[0002]

2. Description of the Related Art When gold (hereinafter referred to as Au) is used as a wiring material for a semiconductor device for high frequencies, it is generally used as a main conductive path to prevent alloying with a base metal.
Platinum (hereinafter P
(denoted as t). Further, since the Pt film has low adhesion to an insulating film such as a silicon oxide film, titanium (hereinafter referred to as Ti) is interposed as an adhesion metal in the lower layer of the Pt film. Therefore, a wiring having a three-layer film structure of Au film / Pt film / Ti film is used. A method of forming such wiring will be described.

First, as shown in FIG. 3A, a first layer wiring 2 is formed by selectively covering an insulating film such as a field oxide film 1 on a silicon substrate. The interlayer insulating film 3a is deposited on the entire surface, and as shown in FIG. 3B, the through hole 4a is formed.
To form. Next, as shown in FIG. 3C, a Ti film and a Pt film are sequentially deposited by a sputtering method to form an adhesion / barrier metal film 5a. Next, as shown in FIG. 3D, an Au film 7a is formed by electroplating using the photoresist film 6a as a mask. Next, as shown in FIG. 3E, the photoresist film 6a is removed, and the adhesion / barrier metal film 5a in the portion not covered with the Au film 7a is removed to form the second-layer wiring 9a.

Japanese Patent Laid-Open No. 2-129945 discloses the following method.

As shown in FIG. 4A, the interlayer insulating film 3a is formed.
The through hole 4a is formed in the
As shown in (b), a buried metal 10 such as Au is formed in the through hole 4a by sufficiently filling the step. That is, the first layer wiring 2 is in contact with a diffusion layer (not shown) on the front surface of the silicon substrate, the back surface side of the silicon substrate is the cathode, the first layer wiring 2 is the conductive path, and the first layer wiring 2 is the first layer wiring. The Au plating layer is deposited by the potential difference between the exposed portion of the through hole 4a of the wiring 2 and the plating solution. After improving the smoothness of the underlying layer of the second-layer wiring to be formed next, the platinum sputtered film 5b is formed, and plating is performed by using the photoresist film 6a as a mask as shown in FIG. 4D.
The u film 7b is formed. Next, as shown in FIG.
The photoresist film 6a is removed, and the platinum sputtered film 5a located therebelow is removed to form the second layer wiring 9b.

[0006]

In the conventional example described with reference to FIG. 3, when the size of the through hole 4a for coupling the first layer wiring 2 and the second layer wiring 9a becomes 2 μm or less, FIG. As shown in e), a cavity 8a is likely to be formed in the Au film 7a of the second layer wiring 9a in the through hole 4a. For this reason,
This causes electromigration, which leads to a decrease in wiring reliability.

Further, in the case of forming a wiring in an upper layer, after the state shown in FIG. 3 (e), the interlayer insulating film 3b is deposited as shown in FIG. 5 (a), but the through hole 4a is formed.
Above, the flatness is poor and the depression 19 is formed. This depression is
This is caused by the poor smoothness of the surface of the second layer wiring in the through hole portion. Next, a through hole 4b is formed, and as shown in FIG. 5B, an Au film 7b is formed using the photoresist film 6b as a mask. Next, as shown in FIG. 5C, the photoresist film 6b and the adhesion / barrier metal film 5b thereunder are removed by etching.
There is a problem that a metal residue 21 of Ti or Pt is generated in the dent 19 part, which causes a leakage current of the wiring and causes a reduction in yield.

Such a problem can be avoided in the conventional example described with reference to FIG. However, in this case, the adhesion / barrier metal film 5b does not exist on the side surface and the bottom surface of the through hole 4a. Therefore, the adhesion between the side surface of the through hole 4a and the embedded metal 10 is difficult, the mechanical strength is low, and it is difficult to completely remove the plating solution when the embedded metal 10 is formed. I have a problem. Further, since the alloying reaction between the surface of the first layer wiring 2 and the embedded metal 10 cannot be prevented, there is almost no degree of freedom in selecting the material, which lacks generality. If the order of the formation of the buried metal 10 and the formation of the adhesion / barrier metal film 5b is replaced by the theory, the problem will not occur. However, if the measures such as using an appropriate mask are not taken, the Au film is entirely covered. Will be plated. As a method of using such a plating mask, there is an example described in JP-A-63-41050. This method is a method of forming bump electrodes. As shown in FIG. 6A, after providing the aluminum pad 11 on the insulating film 10, the protective insulating film 12 is deposited and the opening 13 is provided. Next, as shown in FIG.
A Ti film 14 is formed, and a part thereof is converted into a titanium oxide film 15 by using an anodic oxidation method or the like. Next, as shown in FIG. 6C, a photoresist film 16 having an opening 13a is formed on the aluminum pad 11, and the titanium oxide film 15 is removed using the photoresist film 16 as a mask. Next, electroless plating and T
As a result of the electroplating using the i film 14 as a power supply electrode, FIG.
As shown in (d), Au bumps 18 are formed, and the photoresist film 16 and the titanium oxide film 15 and titanium film 14 thereunder are removed. Although this method can be used for filling the through holes described above, since the opening 13a of the photoresist film 16 (mask) is formed by using the lithography technique, the opening of the mask and the through hole are not formed due to the error due to the alignment accuracy. There is a large or small difference between the above and the above, and there is a defect that the plating having the same thickness as the depth of the through hole is formed on the edge of the through hole, and therefore it cannot be applied as it is. Further, since the number of manufacturing steps is increased to form the pattern of the photoresist film and an expensive pattern projection exposure apparatus (stepper) is used, there is a disadvantage that the cost of the semiconductor device is increased accordingly.

An object of the present invention is to provide a method of manufacturing a semiconductor device having a wiring of a multilayer film structure capable of ensuring the adhesion and barrier property in the opening and the smoothness of the surface.

[0010]

A method of manufacturing a semiconductor device according to the present invention comprises a step of exposing a surface of a lower conductive region by providing an opening in a predetermined insulating film on a semiconductor substrate, and a step of adhering to the insulating film. The adhesion metal film and the barrier metal film having excellent properties are sequentially deposited to form the adhesion / barrier metal film, and the oxide is deposited on the first metal film that is an insulator to form the surface of the insulation film. A step of covering the side surface of the opening and the exposed surface of the conductive region to such an extent that the opening is not completely buried; a step of burying a mask member in the opening using an etch-back method; A step of converting the first metal film into an oxide by an oxidation treatment using a mask member as a mask; a step of removing the mask member and then filling the opening with a metal by plating; Remove the first metal film of It is that a step of forming an upper layer wiring is selectively formed to the second metal layer after exposing the barrier metal film by.

As the first metal film, Ti, Mo or T
A valve metal film such as a can be used. A resist film or an SOG film can be used as the mask member, and anodization using an electrolytic solution can be used as the oxidation treatment. Further, when an SOG film is used, plasma oxidation may be used. In addition, electroless plating is preferable for the plating.

[0012]

Since the periphery of the opening is covered with the oxide of the first metal film, the metal can be embedded only in the opening by plating using this as a mask. When a metal is embedded in this opening by electroplating, the oxide is not present on the edge of the opening where electric field concentration is likely to occur and the metal is not deposited, so that the formation of voids is unlikely to occur. When electroless plating is used, metal deposition is evenly generated, and voids are less likely to occur.

[0013]

The present invention will be described below with reference to the drawings.

FIGS. 1A to 1E are sectional views in order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1A, a first layer wiring 2 is formed by selectively covering an insulating film such as a field oxide film 1 on a silicon substrate. The structure and material of the first layer wiring 2 are not necessarily limited, but may be, for example, a three-layer structure of Au film / Pt film / Ti film. Then, it may be connected to a conductive region such as a lower wiring (not shown) or a diffusion layer (not shown) on the surface of the silicon substrate. Next, an interlayer insulating film 3a having a thickness of 1 to 1.5 μm, dimensions of 1 μm × 1 μ
A through-hole 4a of m to 1.5 μm × 1.5 μm is formed, and a Ti film having a thickness of 50 to 100 nm (flat portion) to be an adhesion / barrier metal 5a by a sputtering method and a thickness of 30 to 5 are formed.
A 0 nm (flat portion) Pt film is sequentially formed, and a Ti film 22a having a thickness of 250 to 500 nm is deposited. Subsequently, a resist having good flatness (for example, HPR204 manufactured by Fuji Hunt Co., Ltd.) is spin-coated to form the flattening film 23.

Next, reactive ion etching (RIE)
Using a gas mixture of CF ₄ and O ₂ with the equipment,
As shown in (b), the flattening film 23 is etched and left as a mask member 23a only inside the through hole 4a.

Next, the exposed field Ti film 22a is formed.
As shown in FIG. 1 (c), the titanium oxide film 2 having a thickness of 100 to 200 nm is oxidized by anodic oxidation.
4 is formed. As a result, Ti inside the through hole 4a
Since the film 22a is masked by the mask member 23a, it is not oxidized, and only the Ti film other than the through holes 4a is converted into a titanium oxide film in a self-aligned manner.

Next, after removing the mask member 23a inside the through hole 4a which has become unnecessary, by peeling off with an organic solvent or the like,
Ti film 22 inside through hole 4a by electroless plating
Au plating is applied to a to form a buried Au 25 inside the through hole 4a as shown in FIG. 1 (d). It is preferable that the surface of the embedded Au 25 is substantially aligned with or slightly higher than the surface of the adhesion / barrier metal film 5a. The embedded Au 25 is preferably formed by electroless plating capable of uniform plating, but electroplating using the adhesion / barrier metal film 5a as a power supply electrode can also be used. In that case, it is preferable that the height of the mask member 23a be slightly lower so that the titanium oxide film covers the location where the electric field concentration occurs at the upper edge of the through hole 4a.

Next, a mixed gas of CF ₄ and O _S using an RIE apparatus, a Ti film remaining without being oxidized etching away some the titanium oxide film 24 which becomes unnecessary under it. This CF ₄ + O ₂ based RIE is a titanium oxide film 24.
And the etching selection ratio of the Ti film to the Pt film of the adhesion / barrier metal film 5a and the buried Au 25 is at least 5.
Since it can be 0 or more, the titanium oxide film 24 and the titanium film can be selectively removed completely. Subsequently, as shown in FIG. 1E, a photoresist film 6a is formed by a photolithography technique, and an Au film 7c having a thickness of 1 μm is electrodeposited on the exposed contact / barrier metal film 5a by electroplating.

The unnecessary photoresist film 6a is removed and removed, and the adhesion / barrier metal film 5a in the region not covered by the Au film 7c is removed by etching by an ion milling method using an argon gas or a chlorine-based gas to form a second layer. The formation of the wiring 9c is completed.

In the case of a semiconductor device having a third layer wiring,
As shown in FIG. 2A, the interlayer insulating film 3b is further deposited, the through hole 4b is formed, and the adhesion / barrier metal film 5b and the Ti film 22b are sequentially deposited.

Next, according to the procedure described above with reference to FIGS. 1A to 1E, an Au film 7d is formed using the photoresist film 6b as a mask, as shown in FIG. 2B. By removing the photoresist film 6b and the adhesion / barrier metal that are no longer needed, the third layer wiring 20b is formed as shown in FIG. 2C.

Since the through hole 4a is almost completely filled with the adhesion / barrier metal film, the titanium film and the buried Au film, the depression 19 is formed in the interlayer insulating film 3b as described with reference to FIG. Although it rarely occurs, it can be rather raised slightly, and there is almost no risk of metal residue (21 in FIG. 5C).

In this embodiment, the mask member is buried by the etch back method using a photoresist film.
Membranes can also be used. That is, for example, C ₂ H ₅
A coating solution consisting of a silanol compound such as Si (OH) ₂ and a solvent is spin-coated, the solvent is evaporated at around 100 ° C., and vitrified by heat treatment in a nitrogen atmosphere at 250 to 350 ° C. Next, etching back is performed by RIE using a mixed gas of CF ₄ and O ₂ to obtain a mask member. In this case, anodization can be used for the oxidation of the Ti film, but plasma oxidation can also be used.

Although the case where the Ti film is used as the first metal film has been described, a molybdenum (Mo) film or a tantalum (Ta) film may be used instead. In the case of Mo film, it can be easily converted into molybdenum oxide film by plasma oxidation,
Molybdenum oxide film is removed by RIE using chlorine gas
Can be achieved by

Although the wiring is taken as an example of the lower conductive region, it goes without saying that it may be a diffusion layer of the semiconductor substrate (source / drain region of FET, collector region of bipolar transistor, etc.). .

[0027]

As described above, according to the present invention, by connecting through the opening such as a through hole provided in the insulating film between the lower conductive region and the upper wiring, the connection from the opening to the outside can be achieved. Extend and cover it with a barrier metal film,
In addition, since only the inside of the opening can be well filled with the metal and the adhesion is good and the wiring having the multilayer film structure having a smooth surface on the opening can be formed, the reliability of the semiconductor device can be improved. Further, since the opening is buried in a self-aligning manner, the photolithography process is not required, and the filling failure due to the shift of the photoresist pattern can be eliminated, so that the semiconductor device can be provided at a low cost.

[Brief description of drawings]

FIG. 1 (a) to (e) for explaining one embodiment of the present invention.
FIG. 7 is a sectional view in order of the processes, which is divided into FIGS.

2A to 2C are sectional views in order of the processes, which are illustrated in FIGS.

3A to 3E are cross-sectional views in order of the processes, which are illustrated by dividing them into (a) to (e) for explaining a conventional example.

4A to 4E are cross-sectional views in order of the processes, which are illustrated by dividing them into (a) to (e) for explaining another conventional example.

FIG. 5 is a diagram (a) to FIG.
It is a process order sectional view divided and shown in (c).

6A to 6D are cross-sectional views in order of the processes, which are divided into (a) to (d) for explaining the bump forming method.

[Explanation of symbols]

 1 Field oxide film 2 First layer wiring 3a, 3b Interlayer insulating film 4a, 4b Through hole 5a, 5b Adhesion / barrier metal film 6a, 6b Photoresist film 7a, 7b, 7c, 7d Gold film 8a, 8b Cavity 9a, 9b, 9c Second layer wiring 10 Buried metal 11 Aluminum pad 12 Protective insulating film 13, 13a Opening 14 Ti film 15 Titanium oxide film 16 Photoresist film 17 Au plating layer 18 Au bump 19 Recess 20a, 20b Third layer wiring 21 Metal remaining 22a, 22b Ti film 23 Flattening film 24 Titanium oxide film 25 Buried Au

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location 9169-4M 604 B

Claims (5)

[Claims] 1. A step of forming an opening in a predetermined insulating film on a semiconductor substrate to expose a surface of a conductive region therebelow, and an adhesive metal film and a barrier metal film having excellent adhesiveness with the insulating film are sequentially formed. Deposit and form a close contact / barrier metal film,
The oxide deposits a first metal film which is an insulator, and covers the surface of the insulating film, the side surface of the opening and the exposed surface of the conductive region to such an extent that the opening is not completely filled. A step of embedding a mask member in the opening using an etch back method, a step of converting the first metal film into an oxide by an oxidation treatment using the mask member as a mask, and the mask member And then filling the opening with metal by plating, and removing the oxide and the first metal film immediately thereunder to expose the barrier metal film, and then selectively removing the second metal film. And a step of forming an upper layer wiring, the method for manufacturing a semiconductor device. 2. The manufacturing of a semiconductor device according to claim 1, wherein the first metal film is a titanium film, a molybdenum film or a tantalum film, the mask member is a resist film or an SOG film, and the oxidation treatment is performed by an anodic oxidation method. Method. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the first metal film is a molybdenum film, a titanium film, or a tantalum film, the mask member is an SOG film, and the oxidation treatment is performed by a plasma oxidation method. 4. The method of manufacturing a semiconductor device according to claim 1, wherein at least a surface portion of the conductive region is made of gold, and the second metal film is a gold film. 5. The plating is electroless plating.
2. The method for manufacturing a semiconductor device according to 2, 3, or 4.