JPH0555167A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a decrease in step coverage of a plated film ascribed to making an interlayer connecting hole small in the formation of metal wirings of a semiconductor device by electrolytically plating. CONSTITUTION:After an interlayer connecting hole 104 is opened and a first metal film 105 as a barrier metal and a second metal film 106 as a base of electrolytically plating are formed by a sputtering method, an insulating film 107 is formed by using a plasma CVD method. An insulating film 107a of a sidewall of the hole, the film 106 and an insulating film 107a of a bottom are removed, the film 106 in the bottom of the hole is exposed, and only the hole is filled in with the plated film by an electrolytically plating method. Thus, the hole 104 is electrolytically plated, and coverage of metal wirings is largely improved thereby to reduce the connecting resistance of multilayer interconnections, and to form the metal wirings such that connection of the upper and lower parts of the hole is facilitated, and which have stable characteristics and high long-term reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device by electrolytic plating.

[0002]

2. Description of the Related Art As shown in FIG. 12, a conventional method for forming a metal wiring of a semiconductor device comprises a known technique such as a CVD technique, a photolithography technique, a dry etching technique on a P-type or N-type semiconductor substrate 101. A diffusion layer 102 having a conduction mechanism different from that of the semiconductor substrate, a silicon oxide film, or PSG or BPSG in which phosphorus or boron is added to the silicon oxide film is formed on the semiconductor substrate 101 by using an ion implantation technique, a thermal diffusion technique, or the like. Interlayer insulating film 103 having a thickness of 0.5 to 1.0 μm, 0.4 to 1.
A structure including the interlayer connection hole 104 having a diameter of 0 μm is formed.

Further, for the purpose of improving heat resistance by suppressing atomic diffusion between the diffusion layer and the metal wiring formed in the upper layer and supplying a plating current at the time of plating, titanium containing 5 to 10% of titanium is added. A first metal film 105 composed of a tungsten alloy or two layers of titanium and titanium nitride is formed by a known technique D.I. C. Using a magnetron sputtering method, with a film forming power of 1.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr, 0.05 to 0.2 μm
With a thickness of 100 μm, formed on the interlayer insulating film 103 and the diffusion layer 102. Subsequently, for the purpose of protecting the surface of the first metal film 105 from a plating solution when forming metal wiring by a plating method, improving adhesion, and supplying a plating current, a first metal film made of gold, platinum, palladium, or the like is used. 1 metal film 106 by D. C. Film-forming power of 0.5 to 1 using the magnetron sputtering method.
Under the conditions of 0 kW and a film forming pressure of 2 to 10 mTorr, 0.
It is formed on the first metal film 105 with a thickness of 01 to 0.1 μm.

Further, as shown in FIG. 13, a wiring forming mask 109 made of a positive type photoresist is selectively formed on the second metal film 106 with a thickness of 1.0 to 2.0 μm by using a photolithography technique. Then, by using an electrolytic gold plating solution composed of sodium gold sulfate, sulfuric acid, phosphoric acid, etc., electricity is supplied by using the first metal film 106 as a cathode and platinum or a mesh electrode formed by coating platinum on titanium as an anode.
Electrolytic gold plating is performed under conditions of a plating temperature of 60 ° C. and a current density of 1 to 4 mA / cm ² , and a fourth metal film 110 made of gold and having a low electric resistance is selected to a thickness of 0.5 to 2.0 μm. And then the wiring forming mask film 109 is removed using an organic solvent. The fourth metal film 110 is formed for the purpose of reducing the electric resistance of the entire wiring.

Subsequently, as shown in FIG. 14, the first lower metal layer 110 is used as an etching mask by a milling method using argon gas as a source and a reactive ion etching method using CF ₄ and SF ₆ as etching gases. Metal film 1
05 and the unnecessary portion of the second metal film 106 are removed to form the metal wiring of the semiconductor integrated circuit device including the first metal film layer 105, the second metal film 106, and the fourth metal film 110. ..

[0006]

The above-described conventional method for forming metal wiring of a semiconductor device has the following drawbacks.

With the miniaturization of the interlayer connection hole, it becomes difficult for the gold plating solution to enter and the growth of the plated metal film from the bottom of the connection hole is hindered, so that the step coverage of the gold plating film is lowered and the interlayer connection resistance value is increased. It is difficult to obtain stable and good electric characteristics of metal wiring and high long-term reliability because disconnection easily occurs due to electromigration or stress migration. Therefore, it becomes difficult to obtain a semiconductor device having high long-term reliability and stable characteristics, and a high yield in the manufacturing process cannot be realized.

[0008]

A method of forming a metal wiring according to the present invention comprises a step of forming an interlayer connecting hole in an interlayer insulating film having a diffusion layer or a wiring as a lower layer, and a first metal film on the interlayer insulating film. And a step of forming a second metal film, a step of forming an insulating film on the second metal film, a step of removing the insulating film and the second metal film existing on the side wall portion of the interlayer connection hole, and a bottom portion of the interlayer connection hole. Removing the insulating film present in the substrate, electrolytically plating and selectively burying only the interlayer connection hole with the third metal film, removing the insulating film, and forming a wiring on the second metal film. A step of forming a mask film for use, a step of performing electroplating and selectively forming wiring by the fourth metal film,
There is a step of forming metal wiring by removing only unnecessary portions of the first metal film and the second metal film.

Further, following the step of selectively burying only the interlayer connection hole portion with the third metal film, a wiring forming mask film is formed on the insulating film, and only the insulating film existing in the wiring forming region is removed. Forming step, a step of selectively forming a wiring by the fourth metal film by electrolytic plating, a step of removing the wiring forming mask film and the insulating film, a first metal film and a second metal film
A step of removing only an unnecessary portion of the metal film to form a metal wiring may be included.

In the means described above, since the base film of the plated metal film is exposed only at the bottom of the interlayer connection hole and the plated metal film grows in one direction from the bottom toward the opening, the step difference of the interlayer connection is caused. It has the effect of greatly improving the coverage.

[0011]

The present invention will be described below with reference to the drawings.

As shown in FIG. 1, a semiconductor is formed on a P-type or N-type semiconductor substrate 101 by using known techniques such as CVD technique, photolithography technique, dry etching technique, ion implantation technique, and thermal diffusion technique. On the substrate 101, the diffusion layer 10 having a conductive mechanism different from that of the semiconductor substrate.
2. A silicon oxide film or an interlayer insulating film 103 having a thickness of 0.5 to 1.0 μm and made of PSG or BPSG in which phosphorus or boron is added to the silicon oxide film, 0.4 to
A structure composed of interlayer connection holes 104 having a diameter of 1.0 μm is formed.

Further, for the purpose of improving heat resistance by suppressing atomic diffusion between the diffusion layer and the metal wiring formed in the upper layer and supplying a plating current at the time of plating, titanium containing 5 to 10% of titanium is added. A second metal film 105 composed of a tungsten alloy or two layers of titanium and titanium nitride is formed by a known technique D.I. C. Using a magnetron sputtering method, with a film forming power of 1.0 to 5.0 kW and a film forming pressure of 2 to 10 mTorr, 0.05 to 0.2 μm
With a thickness of 100 μm, formed on the interlayer insulating film 103 and the diffusion layer 102. Subsequently, for the purpose of protecting the surface of the first metal film 105 from a plating solution when forming metal wiring by a plating method, improving adhesion, and supplying a plating current, a first metal film made of gold, platinum, palladium, or the like is used. 2 metal film 106, and C. Film-forming power of 0.5 to 1 using the magnetron sputtering method.
Under the conditions of 0 kW and a film forming pressure of 2 to 10 mTorr, 0.
It is formed on the first metal film 105 with a thickness of 01 to 0.1 μm.

Subsequently, as shown in FIG. 2, a plasma CVD method is used with SiH ₄ , N ₂ O, NH ₄ , N _2, etc. as a source gas, with an RF power of 0.5 to 1.0 kW and a film forming pressure of 0. Under the conditions of 1 to 10 Torr, the insulating film 107 made of a silicon oxide film, a silicon nitride film, or the like is formed into 0.1 to. It is formed with a thickness of 5 μm. As shown in FIG.
Insulating film sidewall portion 107 formed by plasma CVD method
Utilizing the fact that a is thinner than the flat portion and has a poor film quality, isotropic insulation is performed in a solution such as hydrofluoric acid, buffered hydrofluoric acid or hot phosphoric acid to selectively insulate The film side wall portion 107a is removed. As shown in FIG.
In the step of filling the connection hole with the plated metal film, the side wall portion of the connection hole of the second metal film 106 is removed with aqua regia in order to prevent the growth from the side wall. Further, as shown in FIG. 5, the insulating film at the upper end portion of the interlayer connection hole has an overhang shape, and the fact that the insulating film bottom portion is thinner than the flat portion is utilized,
By performing anisotropic dry etching using ₄ , SF ₆ or the like as an etching gas, only the insulating film bottom portion 107b is removed, and the second metal film 106 at the bottom portion of the connection hole is exposed.

Subsequently, as shown in FIG. 6, the second metal film 10 is formed.
6 is a cathode, and a metal electrode plate in which the surface of a mesh-shaped titanium plate is coated with platinum is used as an anode. By applying a bias between them and energizing them, the third metal film 108 is removed from above the second metal film 106 at the bottom of the fine interlayer connection hole in which the insulating film 107 does not exist.
Grow in one direction toward the opening with a thickness of 5 to 1.0 μm. At this time, by changing the plating conditions such as the plating temperature, the energization amount, the applied voltage value and the applied waveform, it is possible to control the embedding amount and the embedding shape of the third metal film 108 in the fine interlayer connection hole. The standard plating conditions are a temperature of 60 ° C. and a current density of 1 to 4 mA / cm ² .

Subsequently, as shown in FIG. 7, the insulating film 107 is entirely removed, and a photoresist, a photolithography technique, and a dry etching technique, which are known techniques, are used to remove photoresist.
A wiring forming mask 109 composed of a silicon oxide film, a silicon nitride film, or the like is selectively formed on the second metal film 106 with a thickness of 0.5 to 2.0 μm, and the same as the third metal film 108. The fourth metal film 11 is formed using the electrolytic plating method.
0 is the second metal film 1 without the wiring formation mask 109
06 and selectively on the third metal film 108 from 0.5 to 0.5
It is formed with a thickness of 1.0 μm.

Subsequently, as shown in FIG. 8, the wiring forming mask 109 is removed by a known method such as a peeling method using an organic solvent or an ashing method using oxygen plasma, and the fourth metal film 110 is further etched. Mask, SF ₆ , C
Etching back is performed by using a known dry etching method using F ₄ , CCl ₄ , BCl ₃ or the like as an etching gas to remove unnecessary portions of the first metal film 105 and the second metal film to remove the first metal film. Film 105, second metal film 106,
A metal wiring composed of the third metal film 108 and the fourth metal film 110 is formed.

In such a method of forming a metal wiring, the underlying film of the plated metal film is exposed only at the bottom of the interlayer connection hole, and the plated metal film grows in one direction from the bottom to the opening. It is possible to bury the connection hole flat with a plated metal film, which has a lower connection resistance than before,
A wiring structure having high reliability and in which the upper and lower connection holes can be easily connected can be obtained.

It goes without saying that the method for forming metal wiring of a semiconductor device of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar.

Next, another embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 9, the diffusion layer 102, the silicon oxide film, or the silicon oxide film having a conductive mechanism different from that of the semiconductor substrate is formed on the semiconductor substrate 101 by using the same technique and material as those in the first embodiment. Thickness of 0.5 ~ composed of PSG and BPSG to which boron or boron is added
A structure including an interlayer insulating film 103 having a thickness of 1.0 μm, an interlayer connecting hole 104 having a diameter of 0.4 to 1.0 μm, a first metal film 105 and a second metal film 106 is formed, and then the insulating film 1 is formed.
07, the insulating film side wall portion 107a and the second metal film 10 are formed.
After selectively removing the side wall portion and the insulating film bottom portion 107b of No. 6, the third metal film 108 is formed by electrolytic plating to the same thickness as in the first embodiment.

Then, as shown in FIG. 10, the insulating film 107 is formed.
Forming the wiring forming mask film 108 without removing
The insulating film in the wiring formation portion is removed by dry etching, and the exposed first metal film layer 105 is electroplated to form 0.5.
A third metal film 109 having a thickness of 1.0 μm is formed. On this occasion,
Since the photolithography process is performed not on the first metal film layer 105 but on the insulating film 107, the influence of reflection from the second metal film 106 during exposure is reduced, and a good wiring shape can be obtained. Become.

Further, as shown in FIG. 11, the wiring forming mask film 109 is removed by a known method such as a peeling method using an organic solvent or an ashing method using oxygen plasma to entirely cover the insulating film 106. Ion milling method using Ar as a milling source after removal, CF ₄ , SF ₆ , C
Etching back is performed using a known dry etching method using F ₄ or the like as an etching gas to remove unnecessary portions of the first metal film 105 and the second metal film 106,
First metal film layer 105, second metal film 106, third metal film 1
A metal wiring composed of 08 and the fourth metal film 110 is formed.

In such a method of forming a metal wiring, the base film of the plated metal film is exposed only at the bottom of the interlayer connection hole, and the plated metal film grows in one direction from the bottom to the opening. It is possible to bury the connection hole flat with a plated metal film, which has a lower connection resistance than before,
A wiring structure having high reliability and in which the upper and lower connection holes can be easily connected can be obtained.

It goes without saying that the metal wiring forming method for a semiconductor device of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar.

15 to 17 show still another embodiment. As shown in FIG. 15, on a P-type or N-type semiconductor substrate 201, a known CVD technique,
The semiconductor substrate 20 is formed by using photolithography technology, dry etching technology, ion implantation technology, thermal diffusion technology and the like.
A diffusion layer 202 having a conductive mechanism different from that of the semiconductor substrate, a silicon oxide film, or PSG or BPSG in which phosphorus or boron is added to the silicon oxide film, and having a thickness of 0.5 to 1.0 μm. The interlayer insulating films 203, 0.
A structure composed of interlayer connection holes 204 having a diameter of 4 to 1.0 μm is formed.

Further, for the purpose of improving heat resistance by suppressing atomic diffusion between the diffusion layer and the metal wiring formed on the upper layer and supplying a plating current during plating, titanium containing 5 to 10% of titanium is added. The second metal film 205 made of a tungsten alloy is formed by the known technique D.I. C. Using the magnetron sputtering method, the film forming power is 1.0 to 5.0 kW, the film forming pressure is 2 to 10 mTorr, the thickness is 0.05 to 0.2 μm, and the interlayer insulating film 20 is formed.
3, formed on the diffusion layer 202. Next, improvement in adhesion when forming metal wiring in the interlayer connection hole by plating,
For the purpose of supplying a plating current, gold having a sputtering rate higher than that of the first metal film 205 was used as the second metal film 206.
C. Deposition power 0.5 using magnetron sputtering
It is formed on the first metal film 205 with a thickness of 0.01 to 0.1 μm under the conditions of ˜1.0 kW and film forming pressure of 2 to 10 mTorr.

Subsequently, as shown in FIG. 16, the first metal film 1 is formed.
05 and the sputtering rate difference between the second metal film 106,
By performing ion milling, the second metal film 206 outside the interlayer connection hole is removed. At this time, the argon gas is obliquely incident on the substrate so that the second portion at the bottom of the connection hole is exposed.
The metal film 206 is not removed.

Subsequently, as shown in FIG. 17, the second metal film 2
06 is a cathode, and a metal electrode plate in which platinum is coated on the surface of a mesh-shaped titanium plate is used as an anode, and is brought into contact with an electrolytic gold plating solution composed of, for example, gold sulfite kept at a constant temperature of about 60 ° C. By applying a bias and energizing in the meantime, the third metal film 208 is grown from the second metal film 206 on the inner wall of the interlayer connection hole toward the center of the connection hole. At this time, the first metal film serves as a plating current path, and
The metal film 206 has a function as an adhesion layer with the plated metal. Further, by changing the plating conditions such as the plating temperature, the energization amount, the applied voltage value and the applied waveform, the embedding amount and the embedding shape of the third metal film 208 in the fine interlayer connection hole can be controlled. Plating condition is temperature 3
The current density is 0 to 60 ° C. and the current density is 1 to 4 mA / cm ² . After the interlayer connection hole 204 is filled with the third metal film 106 in this way, an upper layer wiring is formed using a known technique.

In such a method for forming a metal wiring, since the underlying film of the plated metal film is exposed only on the inner wall portion of the interlayer connection hole and there is no upper layer wiring, the overhang of the upper layer wiring at the opening of the connection hole is caused. Unaffected by the growth of the sword. Therefore, it becomes possible to bury the interlayer connection hole flat with the plated metal film without generating voids, and it is possible to obtain a wiring structure with lower connection resistance, higher reliability, and easier connection of the upper and lower connection holes than before. ..

It goes without saying that the method for forming metal wiring of a semiconductor device of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar.

Next, another embodiment of the present invention will be described with reference to FIG.
-It will be described with reference to FIG.

As shown in FIG. 18, the diffusion layer 202 having a conductive mechanism different from that of the semiconductor substrate, the silicon acid or the silicon oxide film is formed on the semiconductor substrate 201 by using the same method and material as those of the first embodiment. Thickness of 0.5 ~ composed of PSG and BPSG to which boron or boron is added
A structure including an interlayer insulating film 203 having a thickness of 1.0 μm, an interlayer connecting hole 104 having a diameter of 0.4 to 1.0 μm, a first metal film 205 and a second metal film 206 is formed. Furthermore, using a plasma CVD method, SiH ₄ , N ₂ O, NH ₄ , N ₂
RF power 0.5-1.0k
Under the conditions of W and a film forming pressure of 0.1 to 1.0 torr, the insulating film 207 made of a silicon oxide film is formed to 0.1 to 0.1
It is formed with a thickness of 0.5 μm.

Next, as shown in FIG. 19, the insulating film 207a inside the fine interlayer connection hole is thinner than the flat portion and the film quality is sparse. Remove with buffered hydrofluoric acid.

Subsequently, as shown in FIG. 20, a third metal film 208 having a thickness of 0.5 to 1.0 μm is formed on the second metal film layer 205 exposed only inside the interlayer connection hole by electrolytic plating.
Then, the insulating film 207 is entirely removed. After the interlayer connection hole 204 is filled with the third metal film 206 in this way, an upper layer wiring is formed by using a known technique.

In such a metal wiring forming method, since the underlying film of the plated metal film is exposed only on the inner wall portion of the interlayer connection hole and there is no upper layer wiring, the overhang of the upper layer wiring at the opening of the connection hole is caused. Unaffected by the growth of the sword. Therefore, it becomes possible to bury the inter-layer connection hole evenly with the plated metal film, and the connection resistance is lower than in the past.
A wiring structure having high reliability and in which the upper and lower connection holes can be easily connected can be obtained.

It goes without saying that the method for forming metal wiring of a semiconductor device of the present invention is applicable regardless of the type of semiconductor integrated circuit device such as moss or bipolar.

[0038]

As described above, according to the method of forming a metal wiring of a semiconductor device of the present invention, since the interlayer connection hole can be buried evenly by the plated metal film, the connection resistance in the multilayer wiring can be reduced, This has the effect of forming a metal wiring with stable characteristics and high long-term reliability, in which the connection holes can be easily connected vertically.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing another part of the process of one embodiment.

FIG. 3 is a cross-sectional view showing still another part of the process of one embodiment.

FIG. 4 is a cross-sectional view showing still another part of the process of one embodiment.

FIG. 5 is a cross-sectional view showing still another part of the process of one embodiment.

FIG. 6 is a cross-sectional view showing still another part of the process of one example.

FIG. 7 is a cross-sectional view showing still another part of the process of one embodiment.

FIG. 8 is a cross-sectional view showing still another part of the process of one example.

FIG. 9 is a cross-sectional view showing a part of the process of another embodiment.

FIG. 10 is a cross-sectional view showing another part of the process of another embodiment.

FIG. 11 is a cross-sectional view showing still another part of the process of another embodiment.

FIG. 12 is a cross-sectional view showing a part of a conventional process.

FIG. 13 is a cross-sectional view showing another part of the conventional process.

FIG. 14 is a cross-sectional view showing still another part of the conventional process.

FIG. 15 is a cross-sectional view showing a part of the process of yet another embodiment.

FIG. 16 is a cross-sectional view showing another part of the process of this embodiment.

FIG. 17 is a cross-sectional view showing still another part of the process of this embodiment.

FIG. 18 is a cross-sectional view showing a part of the process of yet another embodiment.

FIG. 19 is a cross-sectional view showing another part of the process of this example.

FIG. 20 is a cross-sectional view showing still another part of the process of this embodiment.

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device in which a metal wiring of a semiconductor device is formed by electrolytic plating, a step of forming an interlayer connecting hole in an interlayer insulating film having a diffusion layer or a wiring as a lower layer, and the interlayer insulating film. A step of forming a first metal film as a barrier metal thereon, and a step of forming a second metal film as a base of plating metal on the first metal film;
Forming an insulating film on the second metal film, removing the insulating film and the second metal film existing on the side wall of the interlayer connection hole, and removing the insulating film existing on the bottom of the interlayer connection hole. A step of performing an electrolytic plating and selectively burying only the interlayer connection hole portion with a third metal film, a step of removing the insulating film, and a wiring forming mask film on the second metal film. A step of selectively forming wiring with a fourth metal film by electrolytic plating, a step of removing the wiring forming mask film, and removing only unnecessary portions of the first metal film and the second metal film to remove metal. A method of manufacturing a semiconductor device, comprising: forming a wiring. 2. A method of manufacturing a semiconductor device in which a metal wiring of a semiconductor device is formed by electrolytic plating, a step of forming an interlayer connecting hole in an interlayer insulating film having a diffusion layer or a wiring as a lower layer, and the interlayer insulating film. A step of forming a first metal film as a barrier metal thereon, and a step of forming a second metal film as a base of plating metal on the first metal film;
Forming an insulating film on the second metal film, removing the insulating film and the second metal film existing on the side wall of the interlayer connection hole, and removing the insulating film existing on the bottom of the interlayer connection hole. And a step of selectively burying only the interlayer connection hole portion with a third metal film by electrolytic plating, forming a wiring forming mask film on the insulating film, and forming the insulating film in the wiring forming region. A step of removing only the above, a step of performing electrolytic plating and selectively forming a wiring by the fourth metal film,
Manufacture of a semiconductor device including a step of removing a wiring forming mask film and the insulating film, and a step of removing only unnecessary portions of the first metal film and the second metal film to form a metal wiring. Method. 3. A step of forming an interlayer connection hole in an interlayer insulating film having a diffusion layer or a wiring as a lower layer; a step of forming a first metal film as a barrier metal on the interlayer insulating film; Second as a base of plated metal on metal film
A step of forming a metal film, and a step of removing the second metal film in the flat portion or leaving the insulating film in the flat portion to expose the second metal film only in a part or the whole inside of the interlayer connection hole. A method of manufacturing a semiconductor device, comprising: a step of performing electrolytic plating to selectively bury only an interlayer connection hole portion with a third metal film; and a step of forming an upper layer wiring.