JPH05211144A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent increase of contact hole resistance of an upper layer wiring connected with a lower layer wiring via an aperture part of an interlayer insulating film, and short circuit between adjacent wirings. CONSTITUTION:By forming a silicon oxide film 9 on the side wall of an aperture part formed in a polyimide based resin insulating film 7 on a lower layer wiring, it is avoided that a TiW film 10 arranged under the upper layer wiring connected with the lower wiring comes directly into contact, in the aperture part 8, with the polyimide based resin insulating film 7 being an organic interlayer insulating film. Thereby it is prevented that the TiW film 10 is oxidized by moisture from the polyimide based resin insulating film 7, volume expansion is generated, and imperfect contact and short circuit between adjacent wirings are caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having multi-layer wiring and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional semiconductor device is shown in FIG.
The insulating film 2 provided on the semiconductor substrate 1 having a diffusion layer is selectively etched to form a contact hole 3, and a refractory metal film 4 such as TiW or W as a barrier metal is formed on the surface including the contact hole 3. An aluminum film 5 is sequentially deposited and patterned to form a lower layer wiring. Next, the polyimide resin insulating film 7 is applied to the surface including the lower layer wiring to flatten the surface, and the polyimide resin insulating film 7 is selectively etched to form an opening on the lower layer wiring. Next, the TiW film 10 and the aluminum film 11 are formed on the surface including the opening.
Are sequentially deposited and patterned to form an upper layer wiring connected to the lower layer wiring.

[0003]

In this conventional semiconductor device, a refractory metal film under the upper wiring is formed on the side wall of the opening for connecting to the upper wiring provided in the organic interlayer insulating film on the lower wiring. Since the organic interlayer insulating film is directly in contact with the organic interlayer insulating film, the moisture in the organic interlayer insulating film reacts with the refractory metal film in a heat treatment in a later step to form an oxide of the refractory metal, resulting in a resistance. There is a problem that the height becomes high and the refractory metal film on the side wall and bottom of the opening expands, resulting in higher resistance of the wiring in the opening and poor contact. This increase in resistance becomes more remarkable as the diameter of the opening portion becomes smaller.

Further, since the side surface of the lower layer wiring and the lower surface of the upper layer wiring are also in direct contact with the organic interlayer insulating film, refractory metal or the like is oxidized as a reaction of moisture in the organic interlayer insulating film in a heat treatment in a later process. However, there is a problem in that a short circuit occurs between adjacent wirings or an increase in wiring resistance is caused due to the occurrence of the expansion or volume expansion.

[0005]

The semiconductor device of the present invention comprises:
Lower layer wiring provided on a semiconductor substrate, an organic interlayer insulating film provided on a surface including the lower layer wiring, an opening portion for connecting an upper layer wiring provided in the organic interlayer insulating film on the lower layer wiring, and the opening. An inorganic insulating film provided on the side wall of the opening and an upper layer wiring provided in connection with the lower layer wiring of the opening.

A first method of manufacturing a semiconductor device according to the present invention is
A step of selectively forming a lower layer wiring on an insulating film provided on a semiconductor substrate, and an organic interlayer insulating film whose upper surface is flattened by applying a polyimide resin film to the surface including the lower layer wiring by a spin coating method. A step of forming, a step of selectively anisotropically etching the organic interlayer insulating film to form an opening portion reaching the lower wiring, and a step of depositing an inorganic insulating film on the surface including the opening portion and etching back. A step of exposing the upper surface of the lower layer wiring leaving an inorganic insulating film only on the sidewall of the opening, and a high melting point metal film or a high melting point metal silicide film and a high conductivity film on the surface including the opening. And a metal film are sequentially laminated and patterned to form an upper layer wiring electrically connected to the lower layer wiring of the opening.

A second method of manufacturing a semiconductor device according to the present invention is
A step of sequentially depositing a refractory metal film or refractory metal silicide film and a metal film of high conductivity on an insulating film provided on a semiconductor substrate to form a first conductor layer having a laminated structure; A step of selectively forming a second conductor layer having a lower wiring forming pattern on the first conductor layer by an electroplating method using the first conductor layer as a feeding layer; and on the second conductor layer A step of selectively forming a third conductor layer for connecting upper wiring by an electroplating method; and a step of etching and removing the first conductor layer using the second conductive layer as a mask by an ion milling method. And a step of depositing an inorganic insulating film on the entire surface and etching back to leave the inorganic insulating film only on the side walls of the lower wiring and the third conductor layer. , On the surface including the lower wiring and the third conductor layer, Applying a polyimide resin film by a coating method to form an organic interlayer insulating film having a flattened upper surface, and then etching back the organic interlayer insulating film to expose the upper surface of the third conductor layer; A high-melting-point metal film or a high-melting-point metal silicide film and a high-conductivity metal film are sequentially deposited on the surface including the third conductor layer and patterned to form an upper layer wiring connected to the lower layer wiring through the third conductor layer. And a step of forming.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a contact hole 3 is formed by selectively etching an insulating film 2 provided on a semiconductor substrate 1 provided with a diffusion layer.
A refractory metal film 4 of Ti, W, Mo or the like and an aluminum film 5 are sequentially deposited and provided on the surface including as a metal for preventing electro-migration and a barrier metal. Next, a photoresist film 6 is applied on the aluminum film 5 and patterned to form a mask for wiring formation.

Next, as shown in FIG. 1B, the aluminum film 5 and the refractory metal film 4 are sequentially anisotropically etched using the photoresist film 6 as a mask to form a lower wiring. Next, after removing the photoresist film 6, a polyimide resin insulating film 7 is applied to the surface including the lower wiring to planarize the surface, and the polyimide resin insulating film 7 is selectively etched to reach the lower wiring. The opening 8 is formed. Next, a silicon oxide film 9 is deposited on the surface including the openings 8.

Next, as shown in FIG. 1C, the silicon oxide film 9 is etched back to remove the silicon oxide film 9 in the flat portion while leaving the silicon oxide film 9 only on the side surface of the opening 8. , Expose the surface of the lower wiring. Here, by depositing a silicon oxide film on the polyimide resin film 7 before forming the opening portion 8, a silicon oxide film is deposited on the polyimide resin insulating film 7 after the silicon oxide film 9 is etched back. Can be left alone. Next, a TiW film 10 and an aluminum film 11 are sequentially deposited and provided on the surface including the opening portion 8, and then the aluminum film 11 and the TiW film 10 are selectively and sequentially etched to form a lower layer wiring of the opening portion 8. An upper layer wiring connected to is formed.

Here, instead of the refractory metal film 4, MoSi,
A high-melting-point metal silicide film such as WSi may be used.
Instead of the film 10, Ti, W, TiN, Mo, MoSi, W
A Si film or the like may be used. Further, instead of the silicon oxide film 9, a silicon nitride film or a silicon oxynitride film may be used.

As described above, in this embodiment, since the inorganic insulating film is formed on the side wall of the opening portion 8, the polyimide resin insulating film is formed on the refractory metal film (or refractory metal silicide film) in the opening portion. Does not come into direct contact with each other, and moisture or the like in the polyimide-based resin insulating film is removed from the high-melting-point metal film in the opening 8 in a heat treatment in a subsequent step, for example, a heat treatment of the polyimide-based resin insulating film or an alloy of the upper wiring. Alternatively, it is possible to prevent the refractory metal film or the refractory metal silicide film in the opening 8 from expanding in volume or increasing in resistance without causing a reaction such as oxidation with the refractory metal silicide film. ..

2 (a)-(c) and FIG. 3 (a),
6B is a sectional view of the semiconductor chip in the order of steps for explaining the manufacturing method according to the second embodiment of the present invention. FIG.

As shown in FIG. 2A, similarly to the first embodiment, the insulating film 2 provided on the semiconductor substrate 1 is selectively etched to form a contact hole 3, and the contact hole 3 is formed.
A TiW film 12, a Pt film 13, and an Au film 14 are sequentially deposited and formed on the surface including, and a photoresist film 6 having a wiring forming pattern is selectively formed on the Au film 14.

Next, as shown in FIG. 2B, the Au film 14, the Pt film 13, and the T film are formed using the photoresist film 6 as a mask.
The i film 12 is sequentially anisotropically etched to form a lower layer wiring, the photoresist film 6 is removed, and then a silicon oxide film 15 is deposited on the surface including the lower layer wiring.

Next, as shown in FIG. 2C, the silicon oxide film 15 is etched back by anisotropic etching to leave the silicon oxide film 15 only on the side wall of the lower wiring. The etching back step of the silicon oxide film 15 may be omitted, and the upper surface of the lower wiring can be protected. Next, the polyimide-based resin insulating film 7 is thickly formed on the surface including the lower layer wiring to flatten the surface, and then the silicon oxide film 16 is deposited on the polyimide-based resin insulating film 7.

Next, as shown in FIG. 3A, the silicon oxide film 16 and the polyimide resin insulating film 7 are selectively and sequentially etched to form an opening 8 reaching the lower wiring. Next, a silicon oxide film 9 is deposited on the surface including the opening 8 and etched back, and the silicon oxide film 9 on the flat portion is removed while leaving the silicon oxide film 9 only on the side wall of the opening 8.
The upper surface of the lower wiring is exposed.

Next, as shown in FIG. 3B, the opening 8
The TiW film 17, the Pt film 18, and the Au film 19 are sequentially deposited on the surface including the Au film 19, the Pt film 18, the TiW film 17,
The silicon oxide film 16 is selectively anisotropically etched in order to form an upper wiring that is connected to the lower wiring of the opening 8.

Here, instead of the TiW films 12 and 17, T
A high melting point metal film such as i, W, TiN, Mo, MoSi, WSi or a high melting point metal silicide film may be used.
An Au film may be used instead of the films 13 and 18. Also,
An aluminum film, an aluminum alloy film, a gold alloy film, or the like may be used instead of the Au films 14 and 19, and a silicon nitride film may be used instead of the silicon oxide films 9, 15, and 16.

In this embodiment, since the side surfaces of the upper layer wiring and the lower layer wiring are covered with the inorganic insulating film, the refractory metal films of the lower layer wiring and the upper layer wiring do not come into contact with the polyimide resin insulating film, and the polyimide resin There is an advantage that reaction with moisture contained in the insulating film can be avoided.

4A to 4C and 5A to 5C.
(C) is sectional drawing of the semiconductor chip shown in order of process for demonstrating the manufacturing method of the 3rd Example of this invention.

As shown in FIG. 4A, the insulating film 2 provided on the semiconductor substrate 1 is selectively etched to form contact holes 3, and the TiW film 12 and Pt are formed on the surface including the contact holes 3. The film 13 is sequentially deposited and formed. Then P
A photoresist film 20 is applied on the t film 13 and patterned to form a mask having a groove for wiring formation.
Next, with the photoresist film 20 as a mask, the TiW film 12
And Pt film 13 as a power supply layer by an electroplating method.
The film 14 is formed.

Next, as shown in FIG. 4B, after the photoresist film 20 is removed, a photoresist film 21 is applied to the surface including the Au film 14 and patterned to form the Au film 1.
An opening portion reaching the upper surface of No. 4 is formed.

Next, as shown in FIG. 4C, the TiW film 12 and the Pt film 1 are formed using the photoresist film 21 as a mask.
3 and the Au film 14 as a power feeding layer on the Au film 14.
The film 22 is formed. Next, after removing the photoresist film 21, the Pt film 13 and the TiW film 12 are sequentially etched and removed by ion milling using the Au film 14 as a mask to form a lower wiring and a conductor layer for connecting the upper wiring.

Next, as shown in FIG. 5A, a silicon oxide film 15 is deposited on the surface including the lower wiring and the Au film 22 and etched back to form the side surface of the lower wiring and the Au film 2.
The silicon oxide film 15 in the flat portion is removed while leaving the silicon oxide film 15 only on the side surfaces of the second surface. Next, the lower wiring and A
The polyimide resin insulating film 7 is applied to the surface including the u film 22 by a spin coating method to flatten the upper surface.

Next, as shown in FIG. 5B, the polyimide resin insulating film 7 is etched back so that the upper surface of the Au film 22 is just exposed. Next, the silicon oxide film 1 is formed on the surface of the polyimide resin insulating film 7 including the Au film 22.
6 is deposited and patterned to expose the upper surface of the Au film 22.

Next, as shown in FIG. 5C, the Au film 2
TiW film 17, Pt film 18, Au film 19 on the surface including 2
Is sequentially deposited, and then the Au film 19, the Pt film 18, the TiW film 17, and the silicon oxide film 16 are selectively anisotropically etched in order to form an upper wiring that is connected to the lower wiring.

[0030]

As described above, according to the present invention, the inorganic insulating film is provided on the side wall of the opening for wiring connection provided in the organic interlayer insulating film, so that the refractory metal film or the refractory metal of the upper wiring can be formed. The effect of preventing contact between the silicide film and the organic interlayer insulating film and preventing contact failure and increase in wiring resistance due to the reaction of water in the organic insulating film with the high melting point metal or the high melting point metal silicide is provided. Have.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to a first embodiment of the present invention.

2A to 2D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

3A to 3D are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

4A to 4C are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to a third embodiment of the present invention.

5A to 5D are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 Contact hole 4 High melting point metal film 5,11 Aluminum film 6,20,21 Photoresist film 7 Polyimide resin insulating film 8 Opening part 9,15,16 Silicon oxide film 10,12,17 TiW film 13,18 Pt film 14,19,22 Au film

Claims (7)

[Claims] 1. A lower layer wiring provided on a semiconductor substrate, an organic interlayer insulating film provided on a surface including the lower layer wiring, and an opening portion for connecting an upper layer wiring provided in the organic interlayer insulating film on the lower layer wiring. A semiconductor device comprising: an inorganic insulating film provided on a side wall of the opening; and an upper layer wiring provided in connection with a lower layer wiring of the opening. 2. The semiconductor device according to claim 1, wherein the upper layer wiring is composed of a conductor layer having a multi-layer structure having a refractory metal film or a refractory metal silicide film as at least the lowermost layer. 3. The lower wiring comprises a multi-layered conductor layer having a refractory metal film or a refractory metal silicide film below, and an inorganic insulating film provided so as to cover at least a side surface of the lower wiring. The semiconductor device according to claim 1 or 2. 4. The semiconductor device according to claim 1, wherein the organic interlayer insulating film is a polyimide resin film. 5. A step of selectively forming a lower layer wiring on an insulating film provided on a semiconductor substrate, and a polyimide resin film is applied to the surface including the lower layer wiring by a spin coating method to planarize the upper surface. A step of forming an organic interlayer insulating film, a step of selectively anisotropically etching the organic interlayer insulating film to form an opening reaching the lower wiring, and an inorganic insulating film on the surface including the opening. A step of depositing and etching back to expose the upper surface of the lower layer wiring leaving an inorganic insulating film only on the side wall of the opening, and a refractory metal film or a refractory metal silicide film on the surface including the opening. And a metal film having a high conductivity are sequentially laminated and patterned to form an upper layer wiring electrically connected to the lower layer wiring of the opening portion, and a method for manufacturing a semiconductor device. 6. The lower wiring comprises a conductor layer having a multi-layer structure having a refractory metal film or a refractory metal silicide film below, and a step of coating at least a side surface of the lower wiring with an inorganic insulating film. Item 6. A method of manufacturing a semiconductor device according to item 5. 7. A first conductor layer having a laminated structure is formed by sequentially depositing a refractory metal film or refractory metal silicide film and a metal film having high conductivity on an insulating film provided on a semiconductor substrate. And a step of selectively forming a second conductor layer having a lower wiring forming pattern on the first conductor layer by electroplating using the first conductor layer as a power supply layer, and the second A step of selectively forming a third conductor layer for connecting upper wiring on the conductor layer by an electroplating method, and etching and removing the first conductor layer using the second conductive layer as a mask by an ion milling method Then, a step of forming a lower layer wiring having a laminated structure of the first and second conductor layers, and an inorganic insulating film is deposited on the entire surface and etched back to form the inorganic insulation only on the side walls of the lower layer wiring and the third conductor layer. The step of leaving the film, the lower wiring and the third conductor layer A step of applying a polyimide resin film by spin coating or the like to the surface including the above to form an organic interlayer insulating film having a flattened upper surface, and then etching back the organic interlayer insulating film to expose the upper surface of the third conductor layer. And the third
A high-melting-point metal film or a high-melting-point metal silicide film and a high-conductivity metal film are sequentially laminated on the surface including the conductor layer and patterned to form an upper layer wiring connected to the lower layer wiring via the third conductor layer. A method of manufacturing a semiconductor device, comprising: