JPH02121350A - Formation of multilayer interconnection - Google Patents

Formation of multilayer interconnection

Info

Publication number
JPH02121350A
JPH02121350A JP27328888A JP27328888A JPH02121350A JP H02121350 A JPH02121350 A JP H02121350A JP 27328888 A JP27328888 A JP 27328888A JP 27328888 A JP27328888 A JP 27328888A JP H02121350 A JPH02121350 A JP H02121350A
Authority
JP
Japan
Prior art keywords
film
polyimide film
forming
polyimide
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27328888A
Other languages
Japanese (ja)
Inventor
Ken Ogura
謙 小椋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP27328888A priority Critical patent/JPH02121350A/en
Publication of JPH02121350A publication Critical patent/JPH02121350A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent foreign substances from generating at the time of dry etching of a metal layer for upper-layer wiring conductor formation use in the forming method of a multilayer interconnection using a polyimide film as an interlayer insulating film by a method wherein a film of a kind different from the kinds of the polyimide film and the metal layer is interposed between the polyimide film and the metal layer. CONSTITUTION:First-layer wiring conductors 25, which are connected to electrode parts of a circuit element 22 through contact holes 24 and consist of Al, are formed on an SiO2 insulating film 23. Then, a polyimide film 26 is formed on the whole surface of the film 23 on a substrate 21 as an interlayer insulating film. After that, an exposure and a developing are performed on said film 26 and a through hole 27 to lead to the conductor 25 is formed in the film 26. After that, after a cure of the film 26 is conducted, a tungsten film 28, for example, is deposited on the whole surface of the film 26 including the whole surface of the hole 27 as a first interposing film. After that, an Al film 29 is formed on the whole surface of the film 28 as a metal layer for second-layer wiring conductor formation use. After that, a patterning is performed on the film 29 by a normal photolitho method and the film 29 is etched by a dry etching method. Thereby, a second-layer wiring conductor 29a is formed on the film 29.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は、半導体集積回路における多層配線の形成方
法に係り、詳しくは、眉間絶縁膜としてポリイミド膜を
用いた多層配線の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming multilayer wiring in a semiconductor integrated circuit, and more particularly to a method for forming multilayer wiring using a polyimide film as an insulating film between the eyebrows.

(従来の技術) 眉間絶縁膜にポリイミド膜を用いた、半導体集積回路に
おける従来の多層配線形成方法としては、特開昭61−
230337号公報に開示されるものがある。その方法
を第2図を参照して説明すると、1は半導体基板であり
、この基板1上の表面部に回路素子2を作り、その表面
をSiJ等の絶縁膜3で覆った後、回路素子の電極4に
接続する第」層の配線導体5を形成し、しかる後PIQ
(日立化成1株)商゛標)のプレポリマーを塗布し最終
的には300℃以上の温度で不活性雰囲気中で加熱硬化
し、第1の高分子樹脂絶縁膜であるPIQ1116を形
成する0次に、PIQ膜6の所定の位置に開口を設けた
後、第2層の配線導体7を形成する0次に、感光剤入り
のポリイミドプレポリマーを塗布し、85℃30分のプ
リベーグを行ない、感光性高分子樹脂膜8を形成する0
次に、通常のUv光による露光、N−メチル−2−ピロ
リドンと水の混合現像液により未露光部(開口部)のポ
リイミドポリマーを除去し、開口部9を形成し、最終的
に350°C130分、窒素雰囲気で加熱硬化させる。
(Prior art) A conventional method for forming multilayer wiring in a semiconductor integrated circuit using a polyimide film as an insulating film between the eyebrows is disclosed in Japanese Patent Application Laid-Open No. 61-1999.
There is one disclosed in Japanese Patent No. 230337. The method will be explained with reference to FIG. 2. 1 is a semiconductor substrate, a circuit element 2 is formed on the surface of this substrate 1, the surface is covered with an insulating film 3 such as SiJ, and then the circuit element is The wiring conductor 5 of the 2nd layer is formed to be connected to the electrode 4 of the PIQ.
(Hitachi Chemical 1 Co., Ltd.) prepolymer is coated and finally cured by heating in an inert atmosphere at a temperature of 300°C or higher to form the first polymer resin insulating film, PIQ1116. Next, after forming an opening at a predetermined position in the PIQ film 6, a polyimide prepolymer containing a photosensitive agent is applied to form the second layer wiring conductor 7, and prebaking is performed at 85°C for 30 minutes. , 0 to form the photosensitive polymer resin film 8
Next, the polyimide polymer in the unexposed areas (openings) is removed by exposure to normal UV light and a mixed developer of N-methyl-2-pyrrolidone and water to form openings 9, and finally 350° Cured by heating in a nitrogen atmosphere for 130 minutes.

その後、第3層の配線導体10を形成する。このように
、ポリイミド膜の形成、スルーホール開口、配線導体の
形成を繰り返せば、何層でも多層配線形成が可能である
Thereafter, a third layer of wiring conductor 10 is formed. In this way, by repeating the formation of the polyimide film, the opening of through holes, and the formation of wiring conductors, it is possible to form multilayer wiring in any number of layers.

(発明が解決しようとする課題) しかるに、以上述べた従来の方法では、デザインレベル
が1.2pmレベルでの設計される半導体集積回路にな
ると、満足すべき多層配線、延いては半導体集積回路を
得るこことができなかった。その理由は、1.2 tr
mレベルでの極く細い配線導体5゜7.10を形成する
には、該配線導体形成用M膜のエンチングにドライエツ
チングを必要とするからである。ドライエツチングによ
りポリイミド膜(PIQ膜6.感光性高分子樹脂膜8)
上のM膜をエツチングすると、エツチング終了後の露出
ポリイミド膜上に残渣状異物が堆積する。この堆積異物
により信転性不良などが生じることになる。
(Problems to be Solved by the Invention) However, with the conventional methods described above, when a semiconductor integrated circuit is designed at a design level of 1.2 pm, it is difficult to achieve satisfactory multilayer interconnection and even semiconductor integrated circuits. I couldn't get it. The reason is 1.2 tr
This is because in order to form an extremely thin wiring conductor of 5° 7.10 mm at the m level, dry etching is required to etch the M film for forming the wiring conductor. Polyimide film (PIQ film 6. Photosensitive polymer resin film 8) by dry etching
When the upper M film is etched, residual foreign matter is deposited on the exposed polyimide film after etching. This accumulated foreign matter causes poor reliability and the like.

前記異物は頑固であり、洗浄薬品では除去できない。ま
た、異物発生は、ポリイミド膜がA/膜の下側に形成さ
れている場合のみに生じる。ポリイミド膜が無い場合に
は、このような現象が発生することはない。また、ポリ
イミド膜をM膜の下側に形成するのとは逆に、M膜の上
に形成した場合にも異物は発生しない。
The foreign matter is stubborn and cannot be removed by cleaning chemicals. Further, foreign matter generation occurs only when the polyimide film is formed under the A/film. If there is no polyimide film, this phenomenon will not occur. Moreover, no foreign matter is generated when the polyimide film is formed on the M film, as opposed to when the polyimide film is formed on the M film.

異物発生の理由は明確ではないが、A/膜エツチングの
最終段階でポリイミド膜表面が露出した時に、ポリイミ
ド膜がスパッタリングされてM原子と結合した後、ポリ
イミド膜上に再付着するものと考えられる。
The reason for the generation of foreign matter is not clear, but it is thought that when the surface of the polyimide film is exposed in the final stage of A/film etching, the polyimide film is sputtered, combines with M atoms, and then re-deposit on the polyimide film. .

この対策として、M膜のドライエンチングを途中で止め
て、残りのA/膜をウエントエッグすることで、異物発
生は防止できる。
As a countermeasure against this, the generation of foreign matter can be prevented by stopping the dry etching of the M film midway and wet-egging the remaining A/film.

しかし、この方法は、プロセスドライ化に反し、かつ工
程が煩雑になり、好ましくない。
However, this method is not preferable because it is contrary to process drying and the steps are complicated.

この発明は、以上述べた、ポリイミド膜を層間絶縁膜と
して用いる方法での配線導体形成用金属層ドライエンチ
ング時の異物発生の問題点を除去し、良好な多層配線を
形成することができる多層配線の形成方法を提供するこ
とを目的とする。
The present invention eliminates the problem of foreign matter generation during dry etching of a metal layer for forming a wiring conductor in the method using a polyimide film as an interlayer insulating film, and makes it possible to form a good multilayer wiring. The purpose of this invention is to provide a method for forming wiring.

(課題を解決するための手段) この発明は、ポリイミド膜を眉間絶縁膜として用いた多
層配線の形成方法において、ポリイミド膜上に直接上層
配線導体形成用金属層を形成せず、ポリイミド膜と上層
配線導体形成用金属層間に、これらとは別種の膜を介在
させるようにしたものである。
(Means for Solving the Problems) This invention provides a method for forming multilayer wiring using a polyimide film as an insulating film between the eyebrows. A film of a different type from these is interposed between metal layers for forming wiring conductors.

(作 用) 上記別種の膜が介在されていると、上層配線導体形成用
金属層ドライエツチング時、上記介在膜がエツチングス
トッパーの役目を果し、その下のポリイミド膜の露出は
ない。したがって、上層配線導体形成用金属層ドライエ
ツチング時の異物発生はない。
(Function) When the different type of film is interposed, the intervening film serves as an etching stopper during dry etching of the metal layer for forming the upper wiring conductor, and the underlying polyimide film is not exposed. Therefore, no foreign matter is generated during dry etching of the metal layer for forming upper layer wiring conductors.

(実施例) 以下この発明の一実施例を第1図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.

まず第1図(a)に示すように、半導体基板21に回路
素子22を形成後、基板21の表面上に5in2からな
る絶縁膜23を形成し、この絶縁膜23にコンタクトホ
ール24を開花後、該コンタクトホール24を通して回
路素子22の電極部に接続されるMからなる第1層配線
環体25を前記絶縁膜23上に形成する。
First, as shown in FIG. 1(a), after forming a circuit element 22 on a semiconductor substrate 21, an insulating film 23 of 5 in 2 is formed on the surface of the substrate 21, and a contact hole 24 is formed in this insulating film 23. A first layer wiring ring body 25 made of M is formed on the insulating film 23 to be connected to the electrode portion of the circuit element 22 through the contact hole 24 .

次に、前記第1層配線環体25を覆うように基板21上
の全面に第1図(b)に示すように、層間絶縁膜として
ポリイミド膜26を形成する。このポリイミド膜26は
、感光性ポリイミドプレポリマー液を300Orpmで
基板21上に回転塗布し、80°C20分のボストベー
クを行うことにより形成される。
Next, a polyimide film 26 is formed as an interlayer insulating film on the entire surface of the substrate 21 so as to cover the first layer wiring ring 25, as shown in FIG. 1(b). This polyimide film 26 is formed by spin-coating a photosensitive polyimide prepolymer solution onto the substrate 21 at 300 rpm and performing a post bake at 80° C. for 20 minutes.

その後、該ポリイミド膜26に対する露光、現像を行い
、前記第1層配線環体25に通じるスルーホール27を
第1図(c)に示すようにポリイミド膜26に形成する
Thereafter, the polyimide film 26 is exposed to light and developed to form a through hole 27 communicating with the first layer wiring ring 25 in the polyimide film 26 as shown in FIG. 1(c).

その後100°C,200°C,350’C各1時間の
ポリイミド膜26のキュアを行った後、同第1図(c)
に示すように、第1の介在膜としてタングステン(W)
膜28を厚さ1500人に、前記スルーホール27を含
むポリイミド膜26の全面に堆積させる。
After that, the polyimide film 26 was cured at 100°C, 200°C, and 350'C for 1 hour each, as shown in Fig. 1(c).
As shown in , tungsten (W) is used as the first intervening film.
A film 28 is deposited to a thickness of 1500 nm over the entire surface of the polyimide film 26 including the through holes 27.

その後、タングステン膜28上の全面に第2層配線環体
形成用金属層として第1図(d)に示すようにM膜29
を形成する。
Thereafter, as shown in FIG. 1(d), an M film 29 is formed on the entire surface of the tungsten film 28 as a metal layer for forming a second layer wiring ring.
form.

その後、M膜29上に通常のホトリソ法でレジストパタ
ーンを形成し、このレジストパターンをマスクとして、
かつエツチングガスとしてBCl3を用いて、M膜29
をドライエンチング法でエツチングし第1図(e)に示
すようにパターニングすることにより、第2層配線環体
29aを形成する。
After that, a resist pattern is formed on the M film 29 by normal photolithography, and this resist pattern is used as a mask.
And using BCl3 as an etching gas, the M film 29 is
A second layer wiring ring body 29a is formed by etching using a dry etching method and patterning as shown in FIG. 1(e).

この時、タングステン膜28はエンチングストンバーと
して作用し、残り、よって、その下のポリイミド膜26
は露出しない。したがって、従来の前記M膜のエンチン
グ紡了時、ポリイミド膜が露出し、スパンタされ、その
結果、残渣状異物が露出ポリイミド膜上に堆積するとい
う悪現象が見られたが、この一実施例の方法ではそのよ
うなことがなく、異物の発生はない。
At this time, the tungsten film 28 acts as an etching stone bar and remains, so that the underlying polyimide film 26
is not exposed. Therefore, when the conventional M film was etched and spun, the polyimide film was exposed and sputtered, resulting in an adverse phenomenon in which residual foreign matter was deposited on the exposed polyimide film. This method does not cause such problems and no foreign matter is generated.

その後、CF、をエンチングガスとしたドライエツチン
グにより、第1図(flに示すように、タングステン膜
28を第2層配線環体29aと同一パターンにエツチン
グする。この同一パターンにエツチングされたタングス
テン膜28を介して第2層配vA導体29aは、スルー
ホール27で第1層配線環体25と接続される。
Thereafter, by dry etching using CF as an etching gas, the tungsten film 28 is etched into the same pattern as the second layer wiring ring 29a, as shown in FIG. The second layer wiring conductor 29a is connected to the first layer wiring ring body 25 through the through hole 27.

その後、第2層配線環体29aを覆うように全面に第1
図(g)に示すごとくポリイミド膜30を第2の眉間絶
縁膜として形成する。このポリイミド膜30の形成方法
は、前回のポリイミド膜26の形成方法と同一である。
After that, the first layer is applied to the entire surface so as to cover the second layer wiring ring body 29a.
As shown in Figure (g), a polyimide film 30 is formed as a second glabellar insulating film. The method for forming this polyimide film 30 is the same as the method for forming the polyimide film 26 previously.

その後、ポリイミド膜30上に、同図に示すように、第
2の介在膜としてアモルファスシリコン膜31を厚さ1
500人に形成し、続いて同図に示すように、アモルフ
ァスシリコン膜31とポリイミド膜30に、第2層配線
環体29aに通じるスルーホール32を形成する。
Thereafter, as shown in the figure, an amorphous silicon film 31 is formed as a second intervening film on the polyimide film 30 to a thickness of 1.
Then, as shown in the figure, a through hole 32 communicating with the second layer wiring ring body 29a is formed in the amorphous silicon film 31 and the polyimide film 30.

その後、M膜の全面形成と該M膜のドライエツチングに
より、前記スルーホール32を通して第2層配線環体2
9aに接続される第3石配線環体33を第1図(ロ)に
示すようにポリイミド膜3oおよびアモルファスシリコ
ン膜31上に形成する。
Thereafter, by forming an M film on the entire surface and dry etching the M film, the second layer wiring ring 2 is passed through the through hole 32.
A third stone wiring ring body 33 connected to 9a is formed on the polyimide film 3o and the amorphous silicon film 31 as shown in FIG. 1(b).

この時、アモルファスシリコン膜31は、M膜エンチン
グのエツチングストッパとして作用し、残り、したがっ
て、その下のポリイミド膜3oの露出が防止されるので
、今回も前回のM膜29のエンチング時と同様に異物の
発生がない。
At this time, the amorphous silicon film 31 acts as an etching stopper for the M film etching and remains, thus preventing the underlying polyimide film 3o from being exposed. No foreign matter is generated.

その後、CZF&+O□をエツチングガスとしたドライ
エツチングにより、第1図(i)に示すようにアモルフ
ァスシリコン膜31を第3層配線環体33と同一パター
ンにエツチングする。以上で多層配線が完成する。
Thereafter, by dry etching using CZF&+O□ as an etching gas, the amorphous silicon film 31 is etched into the same pattern as the third layer wiring ring 33, as shown in FIG. 1(i). With the above steps, multilayer wiring is completed.

なお、上記一実施例では、介在膜としてタングステン膜
およびアモルファスシリコン膜を用いたが、チタン(T
i) 、 ニッケル(Ni)、銅(cu)、 クロム(
cr)、金(Au)なども介在膜として用いることがで
きる。また、上述材料の複合膜を介在膜とすることもで
きる。また、介在膜の厚さは100人〜2000人以内
が適当であり、具体的には、一実施例のタングステン膜
1500人、アモルファスシリコン膜1500人の外、
Niの場合は500人厚、Cuの場合は800人厚Cr
の場合はl000人厚と人厚。
In the above example, a tungsten film and an amorphous silicon film were used as the intervening film, but titanium (T
i), nickel (Ni), copper (cu), chromium (
cr), gold (Au), etc. can also be used as the intervening film. Moreover, a composite film of the above-mentioned materials can also be used as an intervening film. In addition, the thickness of the intervening film is suitably between 100 and 2000. Specifically, in addition to the tungsten film of 1500 and the amorphous silicon film of 1500,
500 people thickness for Ni, 800 people thickness Cr for Cu
In the case of 1000 people thickness and person thickness.

また、上記一実施例では、配線導体を/u 100!膜
で形成したが、AZ −1,5χSi、 Al−1,0
χSi、AZ −5iCuなどで形成してもよく、勿論
、その場合にも、この発明によれば、ドライエツチング
時の異物の発生を防止できる。
Further, in the above embodiment, the wiring conductor is /u 100! Although it was formed with a film, AZ-1,5χSi, Al-1,0
It may be formed of .chi.Si, AZ-5iCu, or the like, and of course, even in that case, according to the present invention, generation of foreign matter during dry etching can be prevented.

また、ポリイミド膜は感光性ポリイミド膜を用いたが、
非感光性ポリイミド膜であってもよい。
In addition, a photosensitive polyimide film was used as the polyimide film, but
It may also be a non-photosensitive polyimide film.

(発明の効果) 以上詳述したように、この発明の方法によれば、ポリイ
ミド膜と上層配線導体形成用金属層間に、これらとは別
種の膜を介在させて、上層配線導体形成用金属層ドライ
エツチング時のポリイミド膜の露出を前記介在膜で防止
するようにしたので、前記ドライエツチングに伴う異物
がポリイミド膜上に付着するのを防止できる。したがっ
て、信転性不良が発生せず、良好な多層配線、延いては
半導体集積回路を製造できる。また、この発明によれば
、プロセスドライ化を崩さず、工程を簡素化し得る。
(Effects of the Invention) As detailed above, according to the method of the present invention, a film of a different type from these is interposed between the polyimide film and the metal layer for forming the upper layer wiring conductor. Since the intervening film prevents the polyimide film from being exposed during dry etching, it is possible to prevent foreign matter from adhering to the polyimide film during the dry etching. Therefore, defective reliability does not occur, and good multilayer wiring and, by extension, semiconductor integrated circuits can be manufactured. Further, according to the present invention, the process can be simplified without compromising the process dryness.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の多層配線の形成方法の一実施例を示
す工程断面図、第2図は従来の多層配線形成方法を示す
断面図である。 21・・・半導体基板、25・・・第1N配線導体、2
6・・・ポリイミド膜、28・・・タングステン膜、2
9・・・M膜、29a・・・第2N配線導体、30・・
・ポリイミド膜、31・・・アモルファスシリコン膜、
33・・・第1N配線導体。 本発明一実施例の工程断面図 第1図 21:半導体基板 25:第1層配線溝体 26:ポリイミド膜 28汐ングステン膜 29:Af膜 29c:第2層配線溝体 30:ポリイミド膜 31:アモルファスシリコン膜 33=第3層配線導体 本発明−実施例の工程断面図 従来の形へ゛方法を示す断面図 第2
FIG. 1 is a process sectional view showing an embodiment of the method for forming a multilayer wiring according to the present invention, and FIG. 2 is a sectional view showing a conventional method for forming a multilayer wiring. 21... Semiconductor substrate, 25... 1st N wiring conductor, 2
6... Polyimide film, 28... Tungsten film, 2
9... M film, 29a... 2nd N wiring conductor, 30...
・Polyimide film, 31... amorphous silicon film,
33... 1st N wiring conductor. Process sectional view of one embodiment of the present invention FIG. 1 21: Semiconductor substrate 25: First layer wiring trench 26: Polyimide film 28 Shio-Tungsten film 29: Af film 29c: Second layer wiring trench 30: Polyimide film 31: Amorphous silicon film 33 = 3rd layer wiring conductor Process cross-sectional diagram of the present invention-embodiment Second cross-sectional diagram showing the conventional method

Claims (1)

【特許請求の範囲】 (a)下層配線導体を形成した半導体基板上に層間絶縁
膜としてポリイミド膜を形成する工程と、(b)そのポ
リイミド膜上に、該ポリイミド膜および上層配線導体形
成用金属層とは別種の膜を形成する工程と、 (c)その膜上に、前記上層配線導体形成用金属層を形
成する工程と、 (d)その金属層をドライエッチングでパターニングす
ることにより上層配線導体を形成する工程と(e)その
後、上層配線導体と同一パターンに前記別種の膜をエッ
チングする工程とを具備してなる多層配線の形成方法。
[Scope of Claims] (a) A step of forming a polyimide film as an interlayer insulating film on a semiconductor substrate on which a lower layer wiring conductor has been formed; (b) A step of forming a polyimide film and a metal for forming an upper layer wiring conductor on the polyimide film. (c) forming the metal layer for forming the upper layer wiring conductor on the film; (d) forming the upper layer wiring by patterning the metal layer by dry etching. A method for forming a multilayer interconnection comprising the steps of: forming a conductor; and (e) etching the different type of film in the same pattern as the upper layer interconnection conductor.
JP27328888A 1988-10-31 1988-10-31 Formation of multilayer interconnection Pending JPH02121350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27328888A JPH02121350A (en) 1988-10-31 1988-10-31 Formation of multilayer interconnection

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27328888A JPH02121350A (en) 1988-10-31 1988-10-31 Formation of multilayer interconnection

Publications (1)

Publication Number Publication Date
JPH02121350A true JPH02121350A (en) 1990-05-09

Family

ID=17525763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27328888A Pending JPH02121350A (en) 1988-10-31 1988-10-31 Formation of multilayer interconnection

Country Status (1)

Country Link
JP (1) JPH02121350A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211144A (en) * 1991-12-27 1993-08-20 Nec Corp Semiconductor device and its manufacture
JPH0660804A (en) * 1992-04-14 1994-03-04 Micron Technol Inc Spacer, for field emission display, manufactured by self-aligned high-energy corrosion
US6686675B2 (en) 1998-08-05 2004-02-03 Murata Manufacturing Co., Ltd. Electronic device and method for producing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211144A (en) * 1991-12-27 1993-08-20 Nec Corp Semiconductor device and its manufacture
JPH0660804A (en) * 1992-04-14 1994-03-04 Micron Technol Inc Spacer, for field emission display, manufactured by self-aligned high-energy corrosion
US6686675B2 (en) 1998-08-05 2004-02-03 Murata Manufacturing Co., Ltd. Electronic device and method for producing the same

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