JPS6083350A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS6083350A
JPS6083350A JP58191473A JP19147383A JPS6083350A JP S6083350 A JPS6083350 A JP S6083350A JP 58191473 A JP58191473 A JP 58191473A JP 19147383 A JP19147383 A JP 19147383A JP S6083350 A JPS6083350 A JP S6083350A
Authority
JP
Japan
Prior art keywords
film
bump
integrated circuit
forming
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58191473A
Other languages
Japanese (ja)
Inventor
Katsuhiko Yabe
矢部 勝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58191473A priority Critical patent/JPS6083350A/en
Publication of JPS6083350A publication Critical patent/JPS6083350A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

PURPOSE:To prevent the peeling of a bump by forming the thin first bump and forming a protective polyimide film. CONSTITUTION:A Ti film 1, a Pt film 2 and an Au first bump 3 are formed on an insulating film 5 on the surface of an integrated circuit. A polyimide film 6 is applied. A Pd film 7 is shaped on the whole surface through sputtering. A photo- resist film 8 is patterned to form an opening section 10. The film 7 is removed while using the film 8 as a mask. A second bump 4 is formed through electrolytic Au plating while using the film 7 as an electrode. The films 8, 7 are removed.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は集積回路の製造方法に関し、特に外部端子であ
る電極用金バンプを有する集積回路の製造方法に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing an integrated circuit having gold bumps for electrodes serving as external terminals.

〔従来技術〕[Prior art]

従来、集積回路の電極用Auバンプ及び表面保護用のポ
リイミド被膜の形成は、第1図〜第3図に示す如〈実施
されている。
Conventionally, the formation of Au bumps for electrodes of integrated circuits and polyimide coatings for surface protection has been carried out as shown in FIGS. 1 to 3.

第1図はウェーハ上に第1バンプ並びに第2バンプの形
成された集積回路製造工程の断面図、第2図は表面保護
とバンプのはがれ防止のためにポリイミド被膜を形成し
た集積回路の平面図、第3図は第2図のA−A’断面図
である0 第1図に示すように、拡散、絶縁膜形成、配線工程の終
了したウェーハの絶縁膜5の上に接着層であるTi膜1
、バリヤ層であるpt模膜2全付た後その上に第1バン
プ3、第2バンプ4をAuメッキで形成する。
Figure 1 is a cross-sectional view of an integrated circuit manufacturing process in which first and second bumps are formed on a wafer, and Figure 2 is a plan view of an integrated circuit in which a polyimide film is formed to protect the surface and prevent bumps from peeling off. , FIG. 3 is a cross-sectional view taken along the line A-A' in FIG. 2. As shown in FIG. Membrane 1
After the PT pattern film 2 serving as a barrier layer is completely deposited, the first bump 3 and the second bump 4 are formed thereon by Au plating.

次いで、第2図、第3図に示すエラに表面保護並びにバ
ンプのはがれ防止の九めポリイミド被膜6を形成する。
Next, a polyimide coating 6 is formed on the gills shown in FIGS. 2 and 3 to protect the surface and prevent the bumps from peeling off.

ポリイミド被膜はウェーッ・上にポリイミド被膜を翅布
形成した後、露光、現像により第2バンプ4上のポリイ
ミド被膜を除去し、第1バンプ3の端部を覆うように選
択除去する0しかし、第2バンプ4の厚さは10〜25
μmと厚く異常にきつい段差のため、所望のパターン通
りの選択除去が困難で、第1バング3の端部を覆,1つ
ないばかりか、第2バンプ4以外のウェーッ・表面を露
出して形成されることが多い。
After forming a polyimide film on the wafer, the polyimide film on the second bump 4 is removed by exposure and development, and is selectively removed so as to cover the end of the first bump 3. 2 The thickness of bump 4 is 10-25
Due to the thick and abnormally tight step height of μm, it is difficult to selectively remove the bump according to the desired pattern, and the edge of the first bump 3 is covered and not only one bump is missing, but also the waviness/surface other than the second bump 4 is exposed. It is often done.

このように形成された集積回路では第1バンプ3の端部
が十分覆われていないのでポリイミド被膜6の第1の役
割であるバンプのはがれ防止の役に立たない。また第1
バンプ3及びバンプ以外のウェーハの一部が露出されて
いるので表面保護の面でも不十分であるという欠点がS
,た。
In the integrated circuit formed in this manner, the ends of the first bumps 3 are not sufficiently covered, so that the polyimide coating 6 is useless in preventing the bumps from peeling off, which is the first role. Also the first
S has the disadvantage that the bump 3 and a part of the wafer other than the bump are exposed, so the surface protection is insufficient.
,Ta.

また、この種の集積回路は高温等の過酷な条件下での信
頼性が要求されることがあり、この場合Auバンプ内に
異種金属が狭まれていることは強度劣化、電気的特性の
劣化につながることになるという欠点を有していた。
In addition, this type of integrated circuit may be required to be reliable under harsh conditions such as high temperatures, and in this case, the presence of dissimilar metals within the Au bump will lead to deterioration of strength and electrical characteristics. It had the disadvantage of leading to

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、ポリイミド被膜は
第1バンプ端部を十分覆い、バンプのはがれ防止を十分
果すと共に過酷な条件下でも信頼性の高い集積回路の製
造方法を提供することにある0 〔発明の構成〕 本発明の集積回路の製造方法は、拡散領域、絶縁膜、配
線を形成したウェーハの前記絶縁膜の上に密着層として
の第1の金属膜、バリヤ層としての第2金属膜及びAu
の第1バンプを順次形成する第1の工程と、前記第1バ
ツグの全部又は一部上に開:孔部を持つポリイミド被膜
を形成する第2の工程と、前記ポリイミド被膜の全表面
に化学薬品でエツチング可能な金属より成る第3の金属
膜を形成する第3の工程と、前記第3:の金属膜の形成
されまたウェーハ上にホトレジスト膜を全面被着し前記
ポリイミド被膜の開孔部より小さな開孔部を前記ポリイ
ミド被膜開孔部に重ねて形成する第4の工程と、前記第
3の金属膜のうち前記開孔部内の第3金属膜を工,チン
グ除去す・・る第15の工程と、前記ホトレジスト膜を
マスクとして前記第3の金属膜を電極として電解Auメ
ッキを・行な・うて第2バンプを形成する第6の工程と
、前記ホトレジスト膜をポリイミド膜を溶解しない有機
性剥離剤で剥離する第7の工程と、前記第3の金属膜を
工,チング除去する第8の工程とを含んで構成される。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an integrated circuit that eliminates the above-mentioned drawbacks, allows the polyimide film to sufficiently cover the end of the first bump, sufficiently prevents the bump from peeling off, and is highly reliable even under harsh conditions. 0 [Structure of the Invention] The method for manufacturing an integrated circuit of the present invention includes forming a first metal film as an adhesion layer and a barrier layer on the insulating film of a wafer on which a diffusion region, an insulating film, and wiring have been formed. Second metal film and Au
a first step of sequentially forming first bumps on the first bag; a second step of forming a polyimide film having holes on all or part of the first bag; a third step of forming a third metal film made of a metal that can be etched with chemicals, and depositing a photoresist film over the entire surface of the wafer where the third metal film is formed, and forming the openings in the polyimide film. a fourth step of forming a smaller aperture overlapping the polyimide coating aperture; and a step of removing the third metal film within the aperture of the third metal film by etching. a sixth step of forming a second bump by performing electrolytic Au plating using the photoresist film as a mask and the third metal film as an electrode; and a sixth step of forming a second bump by dissolving the photoresist film into a polyimide film. The method includes a seventh step of removing the third metal film using an organic remover, and an eighth step of removing the third metal film by etching.

〔実施例の説明〕[Explanation of Examples]

以下、本発明の実施例について、図面を参照して説明す
る。
Embodiments of the present invention will be described below with reference to the drawings.

第4図(a)〜(g)は本発明の一実施例を説明するた
めの工程順に示した断面図である。
FIGS. 4(a) to 4(g) are cross-sectional views shown in order of steps for explaining an embodiment of the present invention.

第4図(a)に示すように、拡散、絶縁膜及び配線工程
を終了した集積回路表面の絶縁膜5の上にバンプと絶縁
層との密着層として0.1μm厚のIf i膜1、’p
iとAuバンプのバリヤ層としてのO51μm厚のpt
膜2、及びAuの第1バンプ3を形成する。
As shown in FIG. 4(a), an If i film 1 with a thickness of 0.1 μm is placed on the insulating film 5 on the surface of the integrated circuit after completing the diffusion, insulating film and wiring process as an adhesion layer between the bumps and the insulating layer. 'p
O5 1 μm thick PT as a barrier layer between i and Au bumps.
A film 2 and a first bump 3 of Au are formed.

次に、第4図(b)に示すように1ウエーハの表面にポ
リイミド被膜を被着させ、第1バンブ3上に第2バンブ
形成用の開孔部9を形成する。このとき第1バンプ3の
端部はポリイミド被膜6により確実に覆われるように形
成する。
Next, as shown in FIG. 4(b), a polyimide film is applied to the surface of one wafer, and openings 9 for forming second bumps are formed on the first bumps 3. At this time, the ends of the first bumps 3 are formed to be reliably covered with the polyimide coating 6.

次に、第4図(C)に示すように、後の工程で化学薬品
により容易に工,チングされ、またAuメッキの電極と
して好都合な金属として1. Pd、 Ni 、 QH
からなる群から選ばれた金属として0.1μm厚のPd
膜7を全面にスバ、りにより形成する。
Next, as shown in FIG. 4(C), metals 1. Pd, Ni, QH
Pd with a thickness of 0.1 μm as a metal selected from the group consisting of
A film 7 is formed over the entire surface by sputtering.

次に、第4図(d)に示すように全表面にホトレジスト
膜8を塗布した後ポリイミド被膜6の開孔部9より小さ
な開孔部となるようポリイミド被膜の開孔部に重ねてホ
トレジスト膜8をパターニングし、ホトレジスト膜の開
孔部1oを形成する。
Next, as shown in FIG. 4(d), after coating the entire surface with a photoresist film 8, a photoresist film is applied over the openings of the polyimide film so that the openings are smaller than the openings 9 of the polyimide film 6. 8 is patterned to form an opening 1o in the photoresist film.

次に、ホトレジスト膜8をマスクとし、ウェーハを塩化
第二鉄、塩酸等にょるPdエツチング液に浸漬し、開孔
部10に露出しているPd膜を選択工、チングにより除
去する。
Next, using the photoresist film 8 as a mask, the wafer is immersed in a Pd etching solution containing ferric chloride, hydrochloric acid, etc., and the Pd film exposed in the opening 10 is removed by selective etching.

次に、第4図(e)に示すように、さきに形成したPd
膜7を電極として、開孔部1oに電解Auメ、キにより
20μm厚の第2バンプ4を形成する。
Next, as shown in FIG. 4(e), the previously formed Pd
Using the membrane 7 as an electrode, a 20 μm thick second bump 4 is formed in the opening 1o by electrolytic Au metallization.

次に、第4図(f)に示すように、ウェーハ上のホトレ
ジスト・1膜8を剥離液で剥離除去する。
Next, as shown in FIG. 4(f), the photoresist film 8 on the wafer is removed using a stripping solution.

次いで、第4図(g)に示すように、Pd膜7を塩化第
二鉄、塩酸等によるPdエツチング液で工、チング除去
する。
Next, as shown in FIG. 4(g), the Pd film 7 is removed by etching with a Pd etching solution using ferric chloride, hydrochloric acid, or the like.

以上の工程によって、電極のAuバンプ及び保護ポリイ
ミド被膜が形成できる。
Through the above steps, the Au bumps of the electrodes and the protective polyimide coating can be formed.

以上形成されたポリイミド被膜は従来のように第2バン
プ形成後でなく、薄い第1バンプ形成後に形成するので
ホトレジストのパターニングは正確に実施することがで
き、第1バンプの端部をポリイミド被膜で十分カバーす
ることができ、従って絶縁層との間でのはがれを確実に
防止することができる。また同様の理由にエリウェーハ
面も露出することがないのでポリイミド被膜の保護膜と
しての役割も十分果すことが可能である。
The polyimide film formed above is formed after the thin first bump is formed, not after the second bump is formed as in the conventional case, so the photoresist patterning can be carried out accurately, and the end of the first bump can be covered with the polyimide film. Sufficient coverage can be achieved, and therefore, peeling from the insulating layer can be reliably prevented. Further, for the same reason, since the surface of the wafer is not exposed, it can also serve as a protective film for the polyimide film.

なお、本実施例では第2バンプ形成前に第1バンプ上に
形成した第3の金属膜であるPd膜を除去した。Pd膜
が第1バンプ、第2バンプ間に介在しても本発明の目的
は達成できるが、この集積回路が高温等の過酷な条件に
さらされると機械的強度の劣化、電気的特性劣化を促進
するが本実施例では第2バンプ形成前に除去されている
ので高信頼性の集積回路とすることができる。
Note that in this example, the Pd film, which is the third metal film formed on the first bump, was removed before forming the second bump. Although the object of the present invention can be achieved even if a Pd film is interposed between the first bump and the second bump, when this integrated circuit is exposed to harsh conditions such as high temperatures, mechanical strength and electrical characteristics deteriorate. However, in this embodiment, since the bumps are removed before forming the second bumps, a highly reliable integrated circuit can be obtained.

なお、上記実施例では第1金属膜としてT1膜、第2金
属膜としてPt膜を使用し九が、これに限定されるもの
でなく第1金属膜としてはOr 、 Ni0r。
In the above embodiment, a T1 film is used as the first metal film and a Pt film is used as the second metal film, but the invention is not limited thereto, and the first metal film may be Or or Ni0r.

Ta、Mo、第2金属膜としては、Pd、Niの金属膜
が同様に適用することが出来る。 □ 〔発明の効果〕 以上説明したように、本発明によれば、バンプのはがれ
が少なく、表面保護効果が大きく、高信頼性の集積回路
を容易に製造することができる。
As the Ta, Mo, and second metal films, metal films of Pd and Ni can be similarly applied. □ [Effects of the Invention] As described above, according to the present invention, it is possible to easily manufacture a highly reliable integrated circuit with less bump peeling and a large surface protection effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のウェーハ上に第1バンプ上第2バンクの
形成された工程の集積回路の断面図、第2図は従来の表
面にポリイミド被膜の形成された集積回路の平面図、第
3図は第2図のA、−A’断面図、第4図(a)〜(g
)は本発明の一実施例を説明するための工程順に示した
断面図である。 1・・・・・・Ti膜、2・・・・・・pt膜、3・・
・・・・第1バンプ、4・・・・・・第2バンプ、5・
・・・・・絶縁膜、6・・・・・・ポリイミド被膜、7
・・・・・・Pd膜、8・・・・・・ホトレジスト膜、
9.10・・・・・・開孔部。 第l 図 凛22 図 第 4 旧
FIG. 1 is a cross-sectional view of an integrated circuit in a conventional process in which a second bank on a first bump is formed on a wafer, FIG. 2 is a plan view of a conventional integrated circuit in which a polyimide film is formed on the surface, and FIG. The figures are A and -A' cross-sectional views in Figure 2, and Figures 4 (a) to (g).
) are sectional views showing the order of steps for explaining one embodiment of the present invention. 1...Ti film, 2...PT film, 3...
...First bump, 4...Second bump, 5.
...Insulating film, 6...Polyimide coating, 7
... Pd film, 8 ... Photoresist film,
9.10... Opening part. Figure 1 Rin 22 Figure 4 Old

Claims (3)

【特許請求の範囲】[Claims] (1)拡散領域、絶縁膜、配線を形成したウェーハの前
記絶縁膜の上に密着層としての第1の金属膜、バリヤ層
としての第2金属膜及びAuの第1バンブを、順次形成
する第1の工程と、前記第1バンプの全部又は一部上に
開孔部を持つポリイミド被膜を形成する第2の工程と、
前記ポリイミド被膜の全表面に化学薬品で工、チング可
能な金属よシ成る第3の金属膜を形成する第3の工程と
、前記第3の金属膜の形成されたウェーハ上にホ、トレ
ジスト腺ヲ全面被着し前記ポリイミド被膜の開孔部より
小さな開孔部を前記ポリイミド被膜開孔部に重ねて形成
する第4の工程と、前記第3の金属膜のうち前記開孔部
内の第3金属膜を工、チング除去する第5の工程と、前
記ホトレジスト膜をマスクとして前記第3の金属膜を電
極として電解Auメ、キを行なって第2バンプを形成す
る第6の工程と、前記ホトレジスト膜をポリイミド膜を
溶解しない有機性剥離剤で剥離する第7の工程と、前記
第3の金属膜を工、チング除去する第8の工程とを含む
ことを特徴とする集積回路の製造方法。
(1) A first metal film as an adhesion layer, a second metal film as a barrier layer, and a first bump of Au are sequentially formed on the insulating film of the wafer on which the diffusion region, insulating film, and wiring have been formed. a first step, and a second step of forming a polyimide film having openings on all or part of the first bump;
A third step of forming a third metal film made of a metal that can be treated with chemicals on the entire surface of the polyimide film, and forming a resist layer on the wafer on which the third metal film is formed. a fourth step of coating the entire surface of the polyimide film and forming apertures smaller than the apertures of the polyimide film overlapping the polyimide film apertures; a fifth step of etching and removing the metal film; a sixth step of forming a second bump by performing electrolytic Au etching using the photoresist film as a mask and the third metal film as an electrode; A method for manufacturing an integrated circuit, comprising: a seventh step of removing the photoresist film with an organic remover that does not dissolve the polyimide film; and an eighth step of removing the third metal film by etching. .
(2)第1の金属膜がTi膜、第2の金属膜がpt膜で
ある特許請求の範囲第(1)項記載の集積回路の製造方
法。
(2) The method for manufacturing an integrated circuit according to claim (1), wherein the first metal film is a Ti film and the second metal film is a PT film.
(3)化学薬品でエツチング可能な金属がpa、Ni。 Ouからなる群から選ばれた金属でるる特許請求の範囲
第(1)項又は第(2)項記載の集積回路の製造方法。
(3) Metals that can be etched with chemicals are pa and Ni. A method for manufacturing an integrated circuit according to claim (1) or (2), wherein the metal is selected from the group consisting of Ou.
JP58191473A 1983-10-13 1983-10-13 Manufacture of integrated circuit Pending JPS6083350A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58191473A JPS6083350A (en) 1983-10-13 1983-10-13 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191473A JPS6083350A (en) 1983-10-13 1983-10-13 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS6083350A true JPS6083350A (en) 1985-05-11

Family

ID=16275235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58191473A Pending JPS6083350A (en) 1983-10-13 1983-10-13 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS6083350A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917231A (en) * 1997-02-17 1999-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including an insulative layer having a gap

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917231A (en) * 1997-02-17 1999-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including an insulative layer having a gap

Similar Documents

Publication Publication Date Title
US6232212B1 (en) Flip chip bump bonding
US4029562A (en) Forming feedthrough connections for multi-level interconnections metallurgy systems
JPH02253628A (en) Manufacture of semiconductor device
JPS6083350A (en) Manufacture of integrated circuit
JPH02224336A (en) Manufacture of semiconductor device
JPS6072249A (en) Manufacture of integrated circuit
JPS6336548A (en) Semiconductor device and manufacture thereof
JPH03198342A (en) Manufacture of semiconductor device
JP2751242B2 (en) Method for manufacturing semiconductor device
JPS63122248A (en) Manufacture of semiconductor device
JPS6329940A (en) Manufacture of semiconductor device
JPH06342796A (en) Forming method of bump electrode
JPH05283412A (en) Semiconductor device and its manufacture
KR100220796B1 (en) Method for making bump area
JPS5950095B2 (en) Manufacturing method of semiconductor device
JPS61141158A (en) Formation of bump electrode
JPH03110835A (en) Manufacture of semiconductor device
JPH04278543A (en) Semiconductor device and manufacture thereof
JPS5910227A (en) Semiconductor device
JPS6019661B2 (en) Electrode formation method
TWI306367B (en) Flexible wiring substrate and manufacturing method of the same
JPS61141157A (en) Manufacture of semiconductor element
JPS6070747A (en) Manufacture of semiconductor devicse
JPS5911647A (en) Semiconductor device and manufacture thereof
JPH04350940A (en) Manufacture of semiconductor device