JPS61141158A - Formation of bump electrode - Google Patents
Formation of bump electrodeInfo
- Publication number
- JPS61141158A JPS61141158A JP59263451A JP26345184A JPS61141158A JP S61141158 A JPS61141158 A JP S61141158A JP 59263451 A JP59263451 A JP 59263451A JP 26345184 A JP26345184 A JP 26345184A JP S61141158 A JPS61141158 A JP S61141158A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist films
- bump electrode
- bump electrodes
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01072—Hafnium [Hf]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体ウェハの上に下地金属層を介して設け
られるバンプ電極の形成方法に関する。The present invention relates to a method for forming bump electrodes provided on a semiconductor wafer with a base metal layer interposed therebetween.
バンプ電極は第2図に示すような構造を有し、半導体ウ
ェハ1の酸化膜2の開口部で接触するアルミニウム配線
3上にさらにプラズマCVDなどで設けられる窒化膜な
どの保護膜4の開口部で接触する、密着金属膜5とバリ
ア金属膜6の積層からなろ下地金属層の上に、例えばフ
ォトレジスト層をマスクとしての電気めっきによりバッ
フアミ極7が形成されている。このようなバンプ電極形
成後、パフファ電極7の直下以外のバリア金属膜6およ
び密着金属膜5が順次エツチングにより鎗去されるが、
この場合、バンプ電極7直下の下地金属層の儂全なエツ
チングマスクの形成が困難であり、例えば密着金属のT
I膜6エツチングの際バンプ電極直下のバリア金属のG
oが腐蝕され、金からなるバンプ電極7の表面の汚れと
なっ゛て付着し、バンプ電極の他の導体との接触面に介
在して接触不良などの原因となる。The bump electrode has a structure as shown in FIG. 2, and has an opening in a protective film 4 such as a nitride film, which is further provided by plasma CVD or the like on an aluminum wiring 3 which is in contact with an opening in an oxide film 2 of a semiconductor wafer 1. A buffer amide pole 7 is formed on a base metal layer consisting of a laminated layer of an adhesive metal film 5 and a barrier metal film 6 which are in contact with each other by, for example, electroplating using a photoresist layer as a mask. After forming such a bump electrode, the barrier metal film 6 and the adhesive metal film 5 other than directly under the puffer electrode 7 are sequentially removed by etching.
In this case, it is difficult to form a perfect etching mask for the base metal layer directly under the bump electrode 7, and for example, the T
G of the barrier metal directly under the bump electrode during etching of I film 6
The gold corrodes and adheres as dirt on the surface of the bump electrode 7 made of gold, intervening on the contact surface of the bump electrode with other conductors and causing poor contact.
本発明は、バンプ電極の形成後の下地金属層エツチング
の際所望の金属以外のバンプ電極直下の金属の腐蝕が防
止されるバンプ電極の形成方法を提供することを目的と
する。 1SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a bump electrode in which corrosion of metals directly under the bump electrode other than the desired metal is prevented during etching of the underlying metal layer after the bump electrode is formed. 1
本発明によれば、下地金属層を被着後、ほぼバンブ電極
を形成すべき領域をホトレジスト膜で、その周囲全面を
そのホトレジストと異なる化学的性質をもつ他の種類の
レジスト膜でそれぞれ被覆し、対応するホトエツチング
によりホトレジスト膜に開口部を設けた後、めっきによ
りその開口部で下地金属層に接触するバンブ電極を形成
し、次いで前記の他の種類のレジスト膜を除去した後露
出した下地金属層をエツチングにより除去することによ
って上記の目的が達成ささる。According to the present invention, after depositing the base metal layer, substantially the area where the bump electrode is to be formed is covered with a photoresist film, and the entire surrounding area is covered with another type of resist film having chemical properties different from that of the photoresist. , after forming an opening in the photoresist film by corresponding photoetching, forming a bump electrode in contact with the underlying metal layer at the opening by plating, and then removing the other types of resist films mentioned above and removing the exposed underlying metal. The above objective is achieved by etching away the layer.
第1図(al〜(e)は本発明の一実施例の工程を示し
、第2図と共通の部分には同一の符号が付されている。
シリコンウェハ1の表面に酸化膜2、AI配線3、窒化
膜4を積層後、窒化膜4の開口部でAI配線3と接する
密着金属のT1膜5.バリア金□属のC。
膜6を順次蒸着する。ついでホトエツチングによりCu
膜6のパターニングを行なう、この状態が第1図+a+
である。つづいてTi膜5と^l膜3との接触部の上方
およびその近傍にネガタイプレジスト膜8を塗布し、そ
の周囲全面にポジタイプのレジスト膜9を塗布したのち
、中央部以外に光を照射し、ネガレジスト現像液によっ
て現像することにより開口部を形成して選択めつき用マ
スクができ上がる。ポジレジスト膜9は光に照射される
がネガレジスト現像液によっては溶けないのでそのまま
残る。この状態が第1図伽)である、つづいて金の電気
めっきによりバンブ電極7を形成する (0図)。
次にアセトン等の有機溶剤でポジレジスト膜9のみを除
去すれば、ネガレジスト膜8が残る(d図)。
このネガレジスト膜8をマスクとしてHF等のエンチン
ダ液でTI膜5を除去する (e図)、これによフてバ
ンブ電極が完成する。この場合、C11膜6はネガレジ
スト膜8によって完全に覆われているから腐蝕されるこ
とがなく、バンプ電極7表面の汚れも発生しない。
上の実施例ではCu膜を予めパターニングしたが、パタ
ーニングしないでバンプ電極形成後にネガレジスト膜8
をマスクとして選択エツチングしても 1よく、
τl膜エツチング時にも表面はネガレジスト膜で覆われ
ているのでCuの溶出はごくわずかですむ。
また、上の実施例のレジストのタイプを反対にしてバン
プ電極形成領域付近にはポジレジスト、その周囲にはネ
ガレジストを用いてもよい、しかしさらに、周囲に用い
るレジスト膜に感光性を育しない耐酸性の膜で、中央部
のホトレジストの現像の際に溶けないものを用いること
もできる。1(al to e) show the steps of an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. An oxide film 2, an AI After laminating the wiring 3 and the nitride film 4, a T1 film 5 of an adhesive metal that contacts the AI wiring 3 at the opening of the nitride film 4. A C film 6 of barrier metal □ is sequentially deposited.Then, Cu is deposited by photo-etching.
This state in which the film 6 is patterned is shown in Figure 1+a+.
It is. Next, a negative type resist film 8 is applied above and in the vicinity of the contact area between the Ti film 5 and the ^l film 3, and a positive type resist film 9 is applied all over the surrounding area, and then light is irradiated to areas other than the central part. By developing with a negative resist developer, openings are formed and a mask for selective plating is completed. Although the positive resist film 9 is irradiated with light, it remains as it is because it is not dissolved by the negative resist developer. This state is shown in Figure 1 (Fig. 1).Next, bump electrodes 7 are formed by gold electroplating (Fig. 0). Next, if only the positive resist film 9 is removed using an organic solvent such as acetone, the negative resist film 8 remains (Fig. d). Using this negative resist film 8 as a mask, the TI film 5 is removed with an encinder solution such as HF (Fig. e), thereby completing a bump electrode. In this case, since the C11 film 6 is completely covered with the negative resist film 8, it will not be corroded and the surface of the bump electrode 7 will not be contaminated. In the above example, the Cu film was patterned in advance, but the negative resist film 8 was formed after forming the bump electrodes without patterning.
Even if you select and etch as a mask, 1 well,
Even during etching of the τl film, since the surface is covered with a negative resist film, the elution of Cu is minimal. Alternatively, the resist types in the above embodiment may be reversed, and a positive resist may be used near the bump electrode formation area and a negative resist may be used around the bump electrode formation area. However, in addition, the resist film used around the bump electrode formation area may not develop photosensitivity. It is also possible to use an acid-resistant film that does not dissolve during development of the photoresist in the center.
本発明は、バンブ電極の選択めっき時のマスクとしてバ
ンプ電極形成領域をホトレジスト膜で、その周囲全面を
化学的性質の興なるレジスト膜で被覆することにより、
下地金属層エツチング時にそのホトレジスト膜を残存さ
せてマスクとして用いることができ、下地金属層エツチ
ング時に望ましくない金属の腐蝕が防止され、バンブ電
極の表面の汚れが発生せず、信鯨性の高い半導体装置の
製造に極めて有効である。In the present invention, the bump electrode formation area is covered with a photoresist film as a mask during selective plating of the bump electrode, and the entire surrounding area is covered with a resist film with different chemical properties.
When etching the base metal layer, the photoresist film can be left behind and used as a mask, preventing undesirable metal corrosion during etching the base metal layer, preventing contamination on the surface of the bump electrode, and creating a highly reliable semiconductor. It is extremely effective in manufacturing devices.
第1図は本発明の一実施例の工程を順次示す要部断面図
、第2図は一般のバンブ電極の構造を示す要部断面図で
ある。
l:シリコンウェハ、3+AI配線、!:Tl膜、6+
Cu膜、7:バンブ電極、8:ネガレジスト膜、9;ポ
ジレジスト膜。
(a) (b)
(C)(d)
(e)
第2図FIG. 1 is a sectional view of a main part sequentially showing the steps of an embodiment of the present invention, and FIG. 2 is a sectional view of a main part showing the structure of a general bump electrode. l: Silicon wafer, 3+AI wiring,! : Tl film, 6+
Cu film, 7: bump electrode, 8: negative resist film, 9: positive resist film. (a) (b) (C) (d) (e) Figure 2
Claims (1)
電極を形成すべき領域をホトレジスト膜で、その周囲全
面を該ホトレジストと異なる科学的性質をもつ他の種類
のレジスト膜でそれぞれ被覆し、対応するホトエッチン
グにより前記ホトレジスト膜に開口部を設けた後、めっ
きにより該開口部で下地金属層に接触するバンプ電極を
形成し、次いで前記の他の種類のレジスト膜を除去した
後露出した下地金属層をエッチングにより除去すること
を特徴とするバンプ電極形成方法。1) After depositing the base metal layer on the semiconductor substrate, cover almost the area where the bump electrodes are to be formed with a photoresist film, and cover the entire surrounding area with another type of resist film having chemical properties different from the photoresist. After forming an opening in the photoresist film by corresponding photoetching, forming a bump electrode that contacts the base metal layer at the opening by plating, and then removing the other type of resist film and exposing it. A bump electrode forming method characterized by removing a base metal layer formed by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263451A JPS61141158A (en) | 1984-12-13 | 1984-12-13 | Formation of bump electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263451A JPS61141158A (en) | 1984-12-13 | 1984-12-13 | Formation of bump electrode |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61141158A true JPS61141158A (en) | 1986-06-28 |
Family
ID=17389691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59263451A Pending JPS61141158A (en) | 1984-12-13 | 1984-12-13 | Formation of bump electrode |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61141158A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03154339A (en) * | 1989-11-13 | 1991-07-02 | Fuji Electric Co Ltd | Etching of plating electrode film for bump electrode |
US6660625B2 (en) * | 1998-07-31 | 2003-12-09 | Industrial Technology Research Institute | Method of electroless plating copper on nitride barrier |
TWI472480B (en) * | 2011-05-31 | 2015-02-11 | Ind Tech Res Inst | Bump with nanolaminated structure, package structure of the same and method of preparing the same |
JP2017017302A (en) * | 2015-06-26 | 2017-01-19 | ▲し▼創電子股▲ふん▼有限公司 | Electronic element and manufacturing method of the same |
-
1984
- 1984-12-13 JP JP59263451A patent/JPS61141158A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03154339A (en) * | 1989-11-13 | 1991-07-02 | Fuji Electric Co Ltd | Etching of plating electrode film for bump electrode |
US6660625B2 (en) * | 1998-07-31 | 2003-12-09 | Industrial Technology Research Institute | Method of electroless plating copper on nitride barrier |
TWI472480B (en) * | 2011-05-31 | 2015-02-11 | Ind Tech Res Inst | Bump with nanolaminated structure, package structure of the same and method of preparing the same |
JP2017017302A (en) * | 2015-06-26 | 2017-01-19 | ▲し▼創電子股▲ふん▼有限公司 | Electronic element and manufacturing method of the same |
US9773746B2 (en) | 2015-06-26 | 2017-09-26 | Sitronix Technology Corp. | Electronic element and manufacturing method |
US10163769B2 (en) | 2015-06-26 | 2018-12-25 | Sitronix Technology Corp. | Manufacturing method for electronic element |
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