JPH06342796A - Forming method of bump electrode - Google Patents

Forming method of bump electrode

Info

Publication number
JPH06342796A
JPH06342796A JP14986493A JP14986493A JPH06342796A JP H06342796 A JPH06342796 A JP H06342796A JP 14986493 A JP14986493 A JP 14986493A JP 14986493 A JP14986493 A JP 14986493A JP H06342796 A JPH06342796 A JP H06342796A
Authority
JP
Japan
Prior art keywords
photoresist film
electroplating
electrode
forming
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP14986493A
Other languages
Japanese (ja)
Inventor
Yoshiro Nishimura
芳郎 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Optical Co Ltd filed Critical Olympus Optical Co Ltd
Priority to JP14986493A priority Critical patent/JPH06342796A/en
Publication of JPH06342796A publication Critical patent/JPH06342796A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

PURPOSE:To provide a method of forming a bump electrode which is high in reliability, excellent in adhesion to an electrode pad, and hardly separated from the pad. CONSTITUTION:By a wafer process, an electroplating conductive layer 4 of metal which is easily etched is formed on all the surface of a semiconductor substrate 1 where an electrode pad 2 and a surface protective film 3 are provided a first photoresist film 5 is applied, only a bump electrode forming part is removed, and a first contact hole is formed. Then, base metal layers 6, 7, and 8 are formed on the bump electrode forming part and the first photoresist film 5, a second photoresist film 9 is applied, the resist film 9 is removed to form a second contact hole slightly smaller than the first contact hole, and a bump electrode 10 is formed by electroplating. The first and the second photoresist film, 5 and 9, are removed, and then electroplating conductive layer 4 is removed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体基板上に該基
板表面の配線と外部回路との接続に用いられる突起電極
を形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming, on a semiconductor substrate, a protruding electrode used for connecting wiring on the surface of the substrate and an external circuit.

【0002】[0002]

【従来の技術】従来、半導体基板上に該基板の配線と外
部回路との接続に用いられる突起電極を形成する方法と
しては、半導体基板の突起電極形成領域以外をフォトレ
ジスト膜によって被覆して、蒸着又はスパッタリングに
よりチップ全面に金属層を形成した後、リフトオフ等の
方法によりフォトレジスト膜をエッチングして突起電極
を形成する方法や、半導体基板の突起電極形成領域以外
をフォトレジスト膜で被覆して選択的に電気メッキを行
い、フォトレジスト膜に被覆されていない領域にのみ金
属を析出させて突起電極を形成する方法などが知られて
いる。
2. Description of the Related Art Conventionally, as a method of forming a protruding electrode used for connecting the wiring of the substrate and an external circuit on a semiconductor substrate, a region other than the protruding electrode forming region of the semiconductor substrate is covered with a photoresist film, After forming a metal layer on the entire surface of the chip by vapor deposition or sputtering, a method of forming a protruding electrode by etching the photoresist film by a method such as lift-off, or by coating the area other than the protruding electrode formation region of the semiconductor substrate with the photoresist film. A method is known in which electroplating is selectively performed and metal is deposited only in a region not covered with a photoresist film to form a protruding electrode.

【0003】次に、図8に基づいて、従来の突起電極の
形成方法の一例について説明する。まず、通常のウェハ
ープロセスを経て形成された半導体基板101 の表面の所
定部分に電極パッド102 が形成され、該電極パッド102
以外の部分に表面保護膜103が形成される。次いで、表
面保護膜103 上及び電極パッド102 の表面上に、接着層
104 ,拡散防止層105 及びメッキ層106 からなる接着性
のよい突起電極下地金属層を、蒸着又はスパッタリング
により半導体基板全面に形成する。次いで、突起電極形
成部分以外の突起電極下地金属層104 ,105 ,106 をフ
ォトレジスト膜107 で被覆した後、突起電極下地金属層
104 ,105 ,106 を導電路にして電気メッキにより突起
電極108 を形成する。最後に突起電極108 をマスクとし
て、フォトレジスト膜107 及び余分の突起電極下地金属
層104 ,105 ,106 をエッチングで除去することによ
り、半導体基板への突起電極が完成する。
Next, an example of a conventional method of forming the protruding electrode will be described with reference to FIG. First, an electrode pad 102 is formed on a predetermined portion of the surface of a semiconductor substrate 101 formed through a normal wafer process.
The surface protective film 103 is formed on the other portions. Then, an adhesive layer is formed on the surface protective film 103 and the surface of the electrode pad 102.
A bump electrode base metal layer having good adhesion, which is composed of 104, the diffusion prevention layer 105 and the plating layer 106, is formed on the entire surface of the semiconductor substrate by vapor deposition or sputtering. Next, after the projection electrode base metal layers 104, 105 and 106 other than the projection electrode formation portion are covered with the photoresist film 107, the projection electrode base metal layer
A protruding electrode 108 is formed by electroplating using 104, 105 and 106 as conductive paths. Finally, by using the protruding electrode 108 as a mask, the photoresist film 107 and the extra protruding electrode underlying metal layers 104 1, 105 and 106 are removed by etching to complete the protruding electrode on the semiconductor substrate.

【0004】[0004]

【発明が解決しようとする課題】ところで、図8に示し
た従来の突起電極の形成方法において、最終工程で下地
金属層をエッチング液で除去する際、下地金属層部分は
異種金属が積層されて形成されているため、局部電池作
用によりオーバーエッチングし易く、精密なエッチング
制御が困難であり、図9の(A),(B)に示すよう
に、突起電極108 の下部までエッチングが進むことがあ
り、この場合は、突起電極108 が剥がれ易くなったり、
剥離したりする危険が生じる。
By the way, in the conventional method of forming a protruding electrode shown in FIG. 8, when the underlying metal layer is removed with an etching solution in the final step, the underlying metal layer portion is formed by laminating different metals. Since it is formed, over-etching is likely to occur due to the local cell action, and precise etching control is difficult, and as shown in FIGS. 9A and 9B, etching may proceed to the lower part of the protruding electrode 108. Yes, in this case, the protruding electrode 108 is easily peeled off,
There is a risk of peeling.

【0005】本発明は、従来の半導体基板用突起電極の
形成方法における上記問題点を解消するためになされた
もので、電極パッドとの接着性がよく剥離等のおそれが
ない信頼性の高い突起電極の形成方法を提供することを
目的とする。
The present invention has been made in order to solve the above problems in the conventional method of forming the protruding electrodes for the semiconductor substrate, and has a highly reliable projection that has good adhesiveness to the electrode pad and is not likely to peel off. It is an object to provide a method for forming an electrode.

【0006】[0006]

【課題を解決するための手段及び作用】上記問題点を解
決するため、本発明は、半導体基板の表面の所定部分に
形成された電極パッド以外の半導体基板の表面部分に表
面保護膜を形成したのち、前記電極パッド及び表面保護
膜上に電気メッキ用導電層を形成する工程と、前記電気
メッキ用導電層上に第1のフォトレジスト膜を形成する
工程と、前記電極パッド上の突起電極が形成される部分
の第1のフォトレジスト膜を除去して第1のコンタクト
ホールを形成する工程と、前記電極パッド上に形成され
た電気メッキ用導電層の露出部及び第1のフォトレジス
ト膜上に下地金属層を形成する工程と、下地金属層上に
第2のフォトレジスト膜を形成する工程と、第2のフォ
トレジスト膜を除去して前記電極パッド上に形成された
前記第1のコンタクトホール内に該第1のコンタクトホ
ールより僅かに小さい第2のコンタクトホールを形成す
る工程と、前記第2のフォトレジスト膜をマスクとして
第2のコンタクトホール内において前記電気メッキ用導
電層を導電路とする電気メッキにより、前記電極パッド
上の下地金属層上に突起電極を形成する工程と、前記第
1のフォトレジスト膜上の下地金属層を第1及び第2の
フォトレジスト膜と共に除去する工程と、前記電極パッ
ド上の下地金属層をマスクとして半導体基板表面の電気
メッキ用導電層を除去する工程とで突起電極を形成する
ものである。
In order to solve the above problems, the present invention forms a surface protective film on the surface portion of the semiconductor substrate other than the electrode pads formed on the predetermined portion of the surface of the semiconductor substrate. After that, a step of forming a conductive layer for electroplating on the electrode pad and the surface protection film, a step of forming a first photoresist film on the conductive layer for electroplating, and a step of forming a protruding electrode on the electrode pad A step of removing the first photoresist film in a portion to be formed to form a first contact hole, and an exposed portion of the electroplating conductive layer formed on the electrode pad and the first photoresist film. A step of forming a base metal layer on the base metal layer, a step of forming a second photoresist film on the base metal layer, and a step of removing the second photoresist film and forming the first contact layer on the electrode pad. Forming a second contact hole slightly smaller than the first contact hole in the through hole, and using the second photoresist film as a mask to form the conductive layer for electroplating in the second contact hole. Forming a bump electrode on the underlying metal layer on the electrode pad by electroplating, and removing the underlying metal layer on the first photoresist film together with the first and second photoresist films. And a step of removing the electroplating conductive layer on the surface of the semiconductor substrate by using the underlying metal layer on the electrode pad as a mask, thereby forming the protruding electrode.

【0007】上記突起電極形成方法においては、第1の
フォトレジスト膜の第1のコンタクトホール内に露出し
た電気メッキ用導電層上に下地金属層を形成するように
しているので、最終工程でエッチングの容易な電気メッ
キ用導電層を除去するだけでよく、エッチングの困難な
下地金属層のエッチングが不要となり、したがって簡単
な工程で信頼性の高い突起電極を形成することができ
る。
In the above-mentioned method of forming the protruding electrode, the underlying metal layer is formed on the electroplating conductive layer exposed in the first contact hole of the first photoresist film, so that the etching is performed in the final step. It is only necessary to remove the conductive layer for electroplating, which eliminates the need for etching the underlying metal layer, which is difficult to etch, and therefore a highly reliable bump electrode can be formed by a simple process.

【0008】[0008]

【実施例】次に実施例について説明する。図1〜7は、
本発明に係る突起電極の形成方法の一実施例を説明する
ための製造工程を示す図である。まず図1に示すよう
に、通常のウェハープロセスを経て形成された半導体基
板1の表面の所定部分に電極パッド2を形成し、該電極
パッド2以外の半導体基板1の表面上に表面保護膜3を
形成したのち、表面全体にAl,Ni等のエッチングの容易
な蒸着又はスパッタリングにより電気メッキ用導電層4
を形成する。次に、図2に示すように、第1のフォトレ
ジスト膜5を厚く、例えば5μm〜25μmに塗布した
後、フォトリソグラフィにより突起電極形成部分にのみ
前記電気メッキ用導電層4に達する第1のコンタクトホ
ール5aを形成する。次いで、図3に示すように、第1
のコンタクトホール5aに露出する電気メッキ用導電層
4の表面及び第1のフォトレジスト膜5の表面に、例え
ばCr,Cu,Ni,Au,Ti,W等の組み合わせで、接着層
6,拡散防止層7,メッキ層8からなる突起電極用下地
金属層を、蒸着又はスパッタリング等により形成する。
EXAMPLES Next, examples will be described. 1-7
FIG. 6 is a diagram showing a manufacturing process for explaining an example of the method for forming the protruding electrode according to the present invention. First, as shown in FIG. 1, an electrode pad 2 is formed on a predetermined portion of the surface of a semiconductor substrate 1 formed through a normal wafer process, and a surface protective film 3 is formed on the surface of the semiconductor substrate 1 other than the electrode pad 2. After the formation of Al, the conductive layer 4 for electroplating is formed on the entire surface by vapor deposition or sputtering of Al, Ni, etc., which can be easily etched.
To form. Next, as shown in FIG. 2, a first photoresist film 5 is applied to a thickness of, for example, 5 μm to 25 μm, and then the first electroconductive layer 4 for electroplating which reaches the electroplating conductive layer 4 only by the photolithography is formed. The contact hole 5a is formed. Then, as shown in FIG.
On the surface of the electroconductive layer 4 for electroplating and the surface of the first photoresist film 5 exposed in the contact hole 5a of the adhesive layer 6 with a combination of Cr, Cu, Ni, Au, Ti, W, etc. A base metal layer for the protruding electrode, which is composed of the layer 7 and the plated layer 8, is formed by vapor deposition, sputtering or the like.

【0009】次いで、図4に示すように、第2のフォト
レジスト膜9を半導体基板表面全面に塗布し、フォトリ
ソグラフィにより突起電極形成部分に前記突起電極用下
地金属層6,7,8に達する、第1のフォトレジスト膜
5の第1のコンタクトホール5aより僅かに小さい第2
のコンタクトホール9aを形成する。次に、図5に示す
ように、電気メッキ用導電層4を導電路として、下地金
属層上にAu,Ag,Cu,Pb−Sn等よりなる突起電極10を、
電気メッキにより形成する。そして突起電極10の形成
後、図6に示すように、第1及び第2のフォトレジスト
膜5,9を除去する。なお、この際、第1のフォトレジ
スト膜5の表面に形成されている不要な下地金属層6,
7,8は、第1のフォトレジスト膜5の除去時に、リフ
トオフ法により除去する。最後に、図7に示すように、
電気メッキ用導電層4を下地金属層6,7,8をマスク
として、ウェット又はドライエッチングにより除去し、
電極パッド2上の突起電極10を形成した半導体基板1が
得られる。
Next, as shown in FIG. 4, a second photoresist film 9 is applied to the entire surface of the semiconductor substrate, and photolithography is performed to reach the protruding electrode forming metal layers 6, 7, 8 for the protruding electrodes. , A second slightly smaller than the first contact hole 5a of the first photoresist film 5
Contact hole 9a is formed. Next, as shown in FIG. 5, using the electroplating conductive layer 4 as a conductive path, the protruding electrode 10 made of Au, Ag, Cu, Pb-Sn or the like is formed on the base metal layer.
It is formed by electroplating. Then, after forming the bump electrode 10, as shown in FIG. 6, the first and second photoresist films 5 and 9 are removed. At this time, the unnecessary underlying metal layer 6, formed on the surface of the first photoresist film 5,
7, 8 are removed by the lift-off method when removing the first photoresist film 5. Finally, as shown in FIG.
The electroplating conductive layer 4 is removed by wet or dry etching using the underlying metal layers 6, 7, and 8 as masks,
The semiconductor substrate 1 having the protruding electrodes 10 formed on the electrode pads 2 is obtained.

【0010】この突起電極の形成方法においては、電気
メッキにより簡単な工程で突起電極10の形成が可能であ
り、また電気メッキ用導電層4と下地金属層6,7,8
を別個に形成しているため、エッチングの困難な下地金
属層6,7,8のエッチングが不要となり、最終工程で
エッチングの容易な電気メッキ用導電層4を除去するこ
とにより突起電極10を完成できるので、下地金属層のオ
ーバーエッチングなどに基づく突起電極の剥離などの発
生は阻止され、簡単な工程で信頼性の高い突起電極を形
成することができる。
In this method of forming the protruding electrode, the protruding electrode 10 can be formed by a simple process by electroplating, and the electroplating conductive layer 4 and the underlying metal layers 6, 7, 8 are formed.
Since it is formed separately, it is not necessary to etch the underlying metal layers 6, 7 and 8 which are difficult to etch, and the protruding electrode 10 is completed by removing the electroplating conductive layer 4 which is easy to etch in the final step. Therefore, the occurrence of peeling of the protruding electrode due to overetching of the underlying metal layer is prevented, and a highly reliable protruding electrode can be formed by a simple process.

【0011】[0011]

【発明の効果】以上、実施例に基づいて説明したよう
に、本発明によれば、最終工程でエッチングの容易な電
気メッキ用導電層を除去するだけでよく、エッチングの
困難な下地金属層のエッチングが不要となるので、簡単
な工程で剥離等の生じない信頼性の高い突起電極を形成
することができる。
As described above on the basis of the embodiments, according to the present invention, it is sufficient to remove the electroplating conductive layer which is easy to etch in the final step, and to remove the underlying metal layer which is difficult to etch. Since etching is unnecessary, it is possible to form a highly reliable bump electrode that does not cause peeling or the like in a simple process.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る突起電極の形成方法の一実施例を
説明するための製造工程を示す図である。
FIG. 1 is a diagram showing a manufacturing process for explaining an example of a method for forming a bump electrode according to the present invention.

【図2】図1に示した製造工程に続く製造工程を示す図
である。
FIG. 2 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG.

【図3】図2に示した製造工程に続く製造工程を示す図
である。
FIG. 3 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 2;

【図4】図3に示した製造工程に続く製造工程を示す図
である。
FIG. 4 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 3;

【図5】図4に示した製造工程に続く製造工程を示す図
である。
FIG. 5 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 4;

【図6】図5に示した製造工程に続く製造工程を示す図
である。
FIG. 6 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 5;

【図7】図6に示した製造工程に続く製造工程を示す図
である。
FIG. 7 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 6;

【図8】従来の突起電極の形成方法の一例を説明するた
めの一製造工程を示す図である。
FIG. 8 is a diagram showing one manufacturing process for explaining an example of the conventional method of forming the protruding electrode.

【図9】従来の方法で形成した突起電極の問題点を説明
するための図である。
FIG. 9 is a diagram for explaining a problem of a protruding electrode formed by a conventional method.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 電極パッド 3 表面保護膜 4 電気メッキ用導電層 5 第1のフォトレジスト膜 5a 第1のコンタクトホール 6 接着層 7 拡散防止層 8 メッキ層 9 第2のフォトレジスト膜 9a 第2のコンタクトホール 10 突起電極 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electrode pad 3 Surface protective film 4 Electroconductive layer 5 for electroplating 5 First photoresist film 5a First contact hole 6 Adhesive layer 7 Diffusion prevention layer 8 Plating layer 9 Second photoresist film 9a Second Contact hole 10 Projection electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の表面の所定部分に形成され
た電極パッド以外の半導体基板の表面部分に表面保護膜
を形成したのち、前記電極パッド及び表面保護膜上に電
気メッキ用導電層を形成する工程と、前記電気メッキ用
導電層上に第1のフォトレジスト膜を形成する工程と、
前記電極パッド上の突起電極が形成される部分の第1の
フォトレジスト膜を除去して第1のコンタクトホールを
形成する工程と、前記電極パッド上に形成された電気メ
ッキ用導電層の露出部及び第1のフォトレジスト膜上に
下地金属層を形成する工程と、下地金属層上に第2のフ
ォトレジスト膜を形成する工程と、第2のフォトレジス
ト膜を除去して前記電極パッド上に形成された前記第1
のコンタクトホール内に該第1のコンタクトホールより
僅かに小さい第2のコンタクトホールを形成する工程
と、前記第2のフォトレジスト膜をマスクとして第2の
コンタクトホール内において前記電気メッキ用導電層を
導電路とする電気メッキにより、前記電極パッド上の下
地金属層上に突起電極を形成する工程と、前記第1のフ
ォトレジスト膜上の下地金属層を第1及び第2のフォト
レジスト膜と共に除去する工程と、前記電極パッド上の
下地金属層をマスクとして半導体基板表面の電気メッキ
用導電層を除去する工程とからなることを特徴とする突
起電極の形成方法。
1. A surface protective film is formed on a surface portion of the semiconductor substrate other than the electrode pads formed on a predetermined portion of the surface of the semiconductor substrate, and then a conductive layer for electroplating is formed on the electrode pad and the surface protective film. And a step of forming a first photoresist film on the electroplating conductive layer,
A step of removing a first photoresist film on a portion of the electrode pad where a protruding electrode is formed to form a first contact hole; and an exposed portion of a conductive layer for electroplating formed on the electrode pad. And a step of forming a base metal layer on the first photoresist film, a step of forming a second photoresist film on the base metal layer, and a step of removing the second photoresist film on the electrode pad. The first formed
Forming a second contact hole slightly smaller than the first contact hole in the contact hole, and using the second photoresist film as a mask to form the electroplating conductive layer in the second contact hole. Forming a protruding electrode on the underlying metal layer on the electrode pad by electroplating to form a conductive path; and removing the underlying metal layer on the first photoresist film together with the first and second photoresist films. And a step of removing the electroplating conductive layer on the surface of the semiconductor substrate using the underlying metal layer on the electrode pad as a mask.
JP14986493A 1993-05-31 1993-05-31 Forming method of bump electrode Withdrawn JPH06342796A (en)

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US6617236B2 (en) * 1998-02-20 2003-09-09 Sony Corporation Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device
KR20120109309A (en) * 2011-03-23 2012-10-08 소니 주식회사 Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board
CN108735725A (en) * 2017-04-18 2018-11-02 中芯国际集成电路制造(北京)有限公司 A kind of semiconductor devices and its manufacturing method and electronic device
JP2019125695A (en) * 2018-01-16 2019-07-25 株式会社アルバック Semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6617236B2 (en) * 1998-02-20 2003-09-09 Sony Corporation Fabrication method of wiring substrate for mounting semiconductor element and semiconductor device
KR20120109309A (en) * 2011-03-23 2012-10-08 소니 주식회사 Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board
JP2012204391A (en) * 2011-03-23 2012-10-22 Sony Corp Semiconductor device, semiconductor device manufacturing method, and circuit board manufacturing method
CN108735725A (en) * 2017-04-18 2018-11-02 中芯国际集成电路制造(北京)有限公司 A kind of semiconductor devices and its manufacturing method and electronic device
CN108735725B (en) * 2017-04-18 2020-06-05 中芯国际集成电路制造(北京)有限公司 Semiconductor device, manufacturing method thereof and electronic device
JP2019125695A (en) * 2018-01-16 2019-07-25 株式会社アルバック Semiconductor device and manufacturing method thereof

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