JPH02125447A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve adhesive properties of Cu wirings with an insulating film and to prevent the wirings from oxidizing by covering the surface of the wirings with a conductive oxidation preventive film. CONSTITUTION:The surface of a semiconductor substrate 1 formed with a buffer film 4 is coated with a conductive oxidation preventive film (barrier metal film) which has a function of the conductive oxidation preventive film made of Mo, etc., to form a barrier metal film 5-1. Then, a Cu film 6 is formed on the film 5-1, and exposed with vapor of benzotriazole to form an oxidation preventive film 7-1 of a several-molecular layer thereon. Thereafter, a wiring pattern is formed with resist 8 therein. Subsequently, the films 7-1, 6 and 5-1 are sequentially etched from the surface by ion beam etching until arriving at the film 4, the film 4 and the resist 8 are thereafter removed to form Cu wirings 6-1. Then, the side face of the wirings 6-1 is further covered with the film 7-1 by a similar method to completely cover the wirings 6-1 with the film 7-1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to semiconductor devices such as LSIs and methods of manufacturing the same, and particularly relates to semiconductor devices such as LSIs, which have poor adhesion to insulating films and are easily oxidized, such as Cu. Moreover, the present invention relates to a semiconductor device using a metal whose compound has a high vapor pressure as a wiring material, and a method for manufacturing the same.

(Prior Art) In recent years, as LSIs have become more highly integrated, electrode wiring has become finer. However, as the electrode wiring becomes finer, current density increases and electromigration resistance deteriorates. Furthermore, finer interconnects are more likely to break due to stress caused by the passivation film, and stress migration resistance is also reduced.

Conventionally, Al-based alloys have generally been used as wiring materials for LSIs, but these Al-based alloys cannot solve the problems described above due to miniaturization. Therefore, recently, the electrical resistance is about 2/3 lower than that of Al-based alloys, and the migration resistance is about 2 times lower than that of Al-based alloys.
Cu-based alloys, which are of an order of magnitude higher, are attracting attention as new wiring materials.

(Problems to be Solved by the Invention) Although the above-mentioned Cu-based alloy brings about various effects, there are some problems that must be solved when applying it to LSI wiring.

The first problem is that the adhesion between Cu and the insulating film is poor.

That is, in a highly integrated semiconductor device such as an LSI, multilayer wiring is provided, and an interlayer insulating film made of S io 2 or the like is formed between the wirings. However, Cu is A! Since the adhesion with the interlayer insulating film is poor compared to that of the conventional method, a problem arises in that the wiring is easily peeled off.

The second problem is that Cu is easily oxidized and corroded.

That is, the Cu thin film is easily oxidized to the inside in the atmosphere at about 100°C. For this reason, pretreatment and annealing at 100° C. to 450° C., which are widely performed in the LSI wiring formation process, are performed in an inert gas atmosphere to prevent Cu from coming into contact with oxygen. However, it is difficult to control an atmosphere that prevents oxygen from being mixed in using such oxygen-free, high-purity gas.

Furthermore, as an interlayer insulating film, S is formed in an oxygen atmosphere.
Since the IO 2 film cannot be used and the oxygen plasma asher cannot be used to remove the resist, there is a problem that the reliability of the wiring is lowered and the cost of the product is increased.

The third problem is that Cu is difficult to etch.

In other words, since Cu has a low vapor pressure of a halogen compound,
Reactive dry etching, which is used for processing Al-based alloys, cannot be used. For this reason, wet etching using ammonium persulfate or ion beam etching for physically processing is used to process the Cu wiring.

However, the processing size of wet etching is limited to 3 μm and cannot be used for LSI. In addition, ion beam etching has the following problems: (1) The cross-sectional shape after processing becomes tapered, making microfabrication difficult. (2) There is large damage due to ion damage. (3) The selectivity ratio between Cu and the insulating film is small. Therefore, there are problems such as over-etching of the insulating film and making it thinner, and (4) difficulty in determining the end point of etching.

The purpose of the present invention was to solve such problems by improving the adhesion between the Cu wiring and the insulating film,
Another object of the present invention is to provide a highly reliable semiconductor device that can prevent Cu wiring from being oxidized and easily form fine wiring with little processing damage, and a method for manufacturing the same.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a semiconductor substrate having a semiconductor element formed on its surface, and at least copper for connecting the semiconductor element and external wiring to each other. A semiconductor device equipped with a metal wiring containing a metal wiring is characterized in that the surface of the metal wiring is covered with a conductive anti-oxidation film.

Furthermore, the manufacturing method includes a step of forming a first buffer film on the surface of the insulating film formed on the surface of the semiconductor substrate in an area other than the area where the metal wiring is formed, and a step of forming a metal thin film on the entire surface. forming a second oxidation prevention film on the entire surface of the metal thin film, and forming a second oxidation prevention film on the surface of the oxidation prevention film so as to cover the area of the metal thin film that will become the metal wiring.
The method is characterized in that etching is performed from the surface of the semiconductor substrate until the first buffer film is exposed.

(Function) As mentioned above, since the entire surface of the metal wiring is covered with a conductive oxidation prevention film, the adhesion between the metal wiring and the insulating film is improved.
In addition, it becomes possible to use a metal that is easily oxidized, such as Cu, which has high migration resistance, as a wiring material for a semiconductor device, and it becomes possible to improve the reliability of the semiconductor device.

Moreover, since the heat treatment can be performed even in an atmosphere containing oxygen, the production equipment and its maintenance and management will not be complicated.

Further, by forming the buffer film, physical etching such as ion beam etching can be performed without damaging the semiconductor substrate, so that precise processing of the metal thin film becomes possible.

Therefore, it becomes possible to form fine wiring patterns, and it becomes possible to provide a semiconductor device with a high degree of integration.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, a highly reliable wiring structure connecting the semiconductor element and external wiring in a semiconductor device in which a semiconductor element such as a transistor is formed will be described.

[First Example] In FIG. 1, a semiconductor substrate 1 on which a semiconductor element is formed
After depositing the SiO2 insulating film 3 on the surface of the semiconductor element, a predetermined pattern is formed in the contact region with the diffusion layer 2 of the semiconductor element by lithography.

Next, by reactive ion etching, the S io 2
Contact hole 1 is formed by etching a predetermined portion of insulating film 3.
form 5.

Next, the 5i02 insulating film 3 in which the contact hole 15 was formed
A resist serving as a buffer film is applied to the surface of the buffer film 4, and the resist in areas where metal wiring is to be formed is removed by lithography to form a buffer film 4.

The thickness of the buffer film 4 may be sufficient as long as it can withstand over-etching when etching the wiring material [FIG. 4(a)].

Next, on the surface of the semiconductor substrate 1 on which the buffer film 4 was formed, M
A barrier metal film 5-1 is formed by depositing a conductive oxidation film (hereinafter also referred to as a barrier metal film) to a thickness of 50 nm by sputtering, which functions as a conductive oxidation prevention film and is made of a material such as do. Note that the barrier metal film 5-1 may be deposited before the buffer film 4 is formed.

Next, Cu is deposited on the surface of the barrier metal film 5-1 to a thickness of 800 nm by sputtering to form a Cu film 6. The Cu film 6 thus formed is exposed to a vapor or liquid of benzotriazole or an aromatic amine-based organic substance having an azo group or an amino group to react with Cu, and the surface of the Cu film 6 is coated with a thickness of at least several molecules. An anti-oxidation film 7-1 is formed, which is a polymer consisting of
.

Thereafter, a wiring pattern is formed using a resist 8 on the surface of the oxidation prevention film 7-1 by phosphorography technique [FIG.
)].

Next, the anti-oxidation film 7-1, the Cu film 6, and the barrier metal film 5-1 are sequentially etched from the surface by ion beam etching until they reach the buffer film 4, and then the buffer film 4 made of resist and the resist 8 are etched. Remove Cu wiring 6
-1 [Figure (d)].

In this embodiment, a resist is used for the buffer film 4, but a polyimide-based organic material may also be used. Note that if polyimide is used, it may be left as is.

Thereafter, an anti-oxidation film 7-1 is further applied to the side surface of the processed Cu wiring 6-1 in the same manner as described above, and the Cu wiring 6-1 is completely covered with the anti-oxidation film 7-1.

Next, a flattening film 9 made of a single layer of a polyimide-based organic material, an SOG film, a microwave plasma CVD film, and an RF plasma CVD film or a laminate thereof is deposited on the recesses formed on the surface of the semiconductor substrate 1. After substantially flattening the surface, S r 02 was applied.

A semiconductor device having a highly reliable wiring structure can be obtained by depositing a protective film or interlayer insulating film 10-1 made of Si3N4 or a polyimide organic material.
Same figure (0)]. Note that the SiO□, S ia N4
If! Additionally, the film may have a composition other than the stoichiometric composition.

Furthermore, in this embodiment, since the anti-oxidation film 7-1 is formed of a polymer of Cu and an organic substance, there is no alloying reaction, and a Cu wiring having a low resistance value can be obtained. Note that in this example, only the method for forming the first layer wiring was explained.
By repeating the above-described process, it will be clear that the present invention can be applied to multilayer wiring.

[Second example] A second embodiment of the present invention will be described with reference to FIG.

In this figure, the same reference numerals as in FIG. 1 indicate the same or equivalent parts.

In this embodiment, barrier metal films 5-1 to 5-4 are formed above and below the two-layer Cu wiring 6-1, 6-2, and the surface of each upper barrier metal film 5-2, 5-4 is This is a wiring structure covered with an oxidation prevention film 7-1 and 7-2 made of S is N4.

Note that the steps up to the formation of the Cu film 6, which will later become the Cu wiring 6-1, are the same as those in the first embodiment, so a description thereof will be omitted.

In the figure, after forming a Cu film 6, a barrier metal film 5-2 made of MO is adhered to the surface of the Cu film 6. This barrier metal film 5-2 is a film that prevents the reaction between the anti-oxidation film 7-1 made of 5t3N4 and the Cu film 6, as will be described later. It also has the effect of increasing the adhesive strength between 6 and the antioxidant film 7-1.

Next, the barrier metal film 5-1, 5-2 and the Cu film 6 are etched using an ion beam etching device to etch the Cu wiring 6.
-1 is formed.

Thereafter, an anti-oxidation film 7-1 made of Si3N4 is bonded to the surface of the semiconductor substrate 1, including at least the side surfaces of the Cu wiring 6-1, by plasma CVD.

The Cu wiring 6-1 is bonded to the SiN film by reacting SiH4 and NH3 in a reducing atmosphere of H2.
is not oxidized.

Thereafter, the surface is flattened with a flattening film 9 in the same manner as in the first embodiment, and an interlayer insulating layer MIO-1 made of 51020) or polyimide is further deposited on the surface.

Next, a contact hole 12 is opened in the interlayer insulating film 10-1, and a buffer film is formed on the surface of the interlayer insulating film in an area other than the area where the metal wiring 6-2 is formed, as in the first embodiment. (
(not shown), and further, the interlayer insulating film 10-1,
A barrier metal film 5-4 is formed to cover the buffer film and the inside of the contact hole 12.

Note that the method for forming the subsequent metal wiring 6-20) oxidation prevention film 7-2, the etching method thereof, and the method for forming the insulating film 10-2 after etching are the same as in the first embodiment. Therefore, its explanation will be omitted.

In this example, Cu wiring 6-1 and 6-2 are both M O
Because the structure is covered with T S ta N J-, the Cu wiring 6-1, 6-2 does not come into direct contact with the external atmosphere (oxygen), making it a highly reliable semiconductor with two-layer Cu wiring. You can get the equipment.

Further, in this embodiment, a wiring structure in which the Cu wiring 6-1, 6-2 is covered with 2ffi by a barrier metal film and an anti-oxidation film has been described, but as described in the third embodiment below,
An anti-oxidation film 7-3 made of Si3N4 is applied directly to the Cu wiring 6.
A similar effect can be obtained by forming a .

[Third Embodiment] FIG. 3 is a partial sectional view of the third embodiment of the present invention, and the first
The same reference numerals as in the figures or FIG. 2 represent the same or equivalent parts.

In this embodiment, unlike the second embodiment, a barrier metal film 5-2, 5-4 is formed on the upper surface of the Cu wiring 6-1, 6-2.
It is characteristic that the anti-oxidation film 7-1, 7-2 made of Si3N4 is directly formed without bonding.

Further, an anti-oxidation film 7 formed on the surface of the Cu wiring 6-1
The characteristic feature is that the thickness of -1 is relatively thick, and the anti-oxidation film also functions as an interlayer insulating film or a protective film, respectively.

According to such a configuration, the manufacturing process is simplified compared to the case of the embodiment shown in FIG.

In the three embodiments described above, the barrier metal films 5-1 to 5-4 functioning as conductive oxidation-preventing films were described as being formed of MO, but TiN,
TiWSWSV%Ta.

Z rs P t % T I % Cr, Pb5Ai,
Similar effects can be achieved by using A11%Ni, Co%Fe, If alone, or their silicides.

Similarly, the anti-oxidation film 7-1.7-2 has been described as being formed from an organic polymer or Si3N4;
It may be nitrides such as Cr, Cu, etc., or a multilayer film made by laminating them.

By the way, coating Cu wiring with such a barrier metal can achieve remarkable effects in improving the oxidation resistance and peeling strength of Cu wiring as described above, but it does not improve electromigration resistance. From the viewpoint of improvement, depending on the type of barrier metal to be coated, it may be better not to coat at all.

Figure 4 shows 0. On the thermal oxide film formed with a thickness of 5 μm, barrier metals W1TiN and Mo with a film thickness of 0.1 μm are respectively deposited, and on top of that, Cu wiring with a film thickness of 0.8 μm is formed with a width of 2 μm and a length of 1 cm. -, and 1 to this wiring pattern.
This graph shows the rate of increase in resistance over time before and after a current of 8×10 A/Cm2 was passed in air at 50°C.

According to the results of this experiment, it can be seen that when WlTiN is used as the barrier metal, the rate of increase in resistance is higher than when the same <Mo is used or when Cu alone is used, and the wire breaks more quickly.

To be more specific, the resistance increase rate after 500 hours of test time is about 5% for the Cu/Mo two-layer structure and about 8% for the Cu single-layer structure, whereas the rate of resistance increase for Cu/W is about 5%. Approximately 35% for layered structure, approximately 30% for Cu/TiN two-layer structure
It becomes.

Also, when comparing the disconnection times, the Cu/Mo two-layer structure does not disconnect even after 1000 hours, similar to the Cu single-layer structure, whereas the Cu/W two-layer structure does not disconnect after about 700 hours.
When time elapses, the Cu/TiN two-layer structure breaks after about 500 hours.

Furthermore, as will be explained below, according to experiments conducted by the inventors, the amount of resistance change after annealing also decreases when Cu/M
o two-layer structure, Cu/W two-layer structure and Cu/T
It was confirmed that it was smaller than the iN two-layer structure and almost the same as the Cu single-layer structure.

Figure 5 shows the results before and after annealing at 450°C for 1 hour on a single layer of Cu, two layers of Cu/W, two layers of Cu/TiN, and two layers of Cu/Mo. FIG. 3 is a diagram showing changes in resistance value.

According to the results of this experiment, compared to the amount of change in resistance value in Cu single layer and Cu/Mo two layer structure, Cu/W and Cu
It can be seen that it is large in the two-layer structure of /T i N.

In addition, in the two-layer structure of Cu/W and Cu/TiN, W and TiN react with Cu and form many reaction products, whereas in the two-layer structure of Cu/Mo This is because MO does not react much with Cu and does not form much reaction products.

Therefore, if the barrier metal film is required not only to prevent oxidation but also to maintain high electromigration and low resistance, it is desirable to use Mo as the barrier metal.

[Fourth Embodiment] FIG. 6(a) is a sectional view of a fourth embodiment of the present invention, and FIG. 6(b) is a side sectional view thereof.

In this example, the side and top surfaces of the Cu wiring 6 formed on the semiconductor substrate 1 via the barrier metal 5-1 are fluoridated or nitrided, and Cu fluoride or Cu nitride 11 is formed thereon. This structure is achieved by the following manufacturing method.

First, a barrier metal 5-1 is deposited on the surface of the insulating film 3 and the contact hole 15 in order to suppress the reaction between the St of the diffusion layer 2 and the Cu wiring and to improve the adhesion between the insulating film 3 and the Cu wiring 6. After depositing a layer of 0.1 .mu.m, for example, 0.8 .mu.m of Cu, which will become the Cu wiring 6, the Cu wiring 6 is formed by patterning in the same manner as described above.

Next, the exposed side surfaces and top surface of the Cu wiring 6 are fluoridated or nitrided to form Cu fluoride or Cu nitride 11 thereon. In case of fluorination, NF3, CF
Fluorine-containing gas such as No. 4, or NH3 in the case of nitriding
, N2, and the like are used as reaction gases, and the reaction is carried out by, for example, a photoexcitation method, a plasma processing method using a plasma generator, or the like.

Note that it is desirable that the thickness of the fluorine steel or copper nitride 11 formed by the fluorine treatment or nitriding treatment be 0.1 μm, which is enough to withstand the subsequent heat treatment.

According to this example, the side and top surfaces of the Cu wiring are covered with fluorine steel or copper nitride, which has excellent oxidation resistance, so that the Cu wiring is prevented from being oxidized even when an interlayer insulating film is formed later. do not have.

[Fifth Embodiment] FIG. 7 is a sectional view of a fifth embodiment of the present invention.
The same reference numerals as in the figures to FIG. 3 represent the same or equivalent parts.

This embodiment is characterized in that the barrier metal 13 is embedded in the contact holes 15.12, and such a structure is achieved by the following manufacturing method.

S10 is applied to the surface of the semiconductor substrate 1 on which the semiconductor element is formed.
2 insulation II! 3, a predetermined pattern is formed in the contact region with the diffusion layer 2 of the semiconductor element by phosphorography technique. Next, a contact hole 15 is formed by etching a predetermined portion of the SiO2 insulating film 3 using reactive ion etching.

Next, after filling the barrier metal 13 into the contact hole 15 to a portion corresponding to the height of the insulating film 3, the insulating film 3 is
A barrier metal film 5-1 is further deposited on the surface of the barrier metal 13 to a thickness of 0.1 μm.

At this time, high electromigration occurs in the Cu wiring.
If low resistance is required, it is desirable to use MO as the barrier metal film 5-1, as described above.

Next, after the thickness of the Cu film that will become the Cu wiring is, for example, 0.8 μm*i, the barrier metal film 5-1 and the Cu film are etched in the same manner as described above to form the Cu wiring 6-1.

Here, an anti-oxidation film, barrier metal, copper fluoride, etc. may be formed on the top and side surfaces of the Cu wiring exposed to the outside in the same manner as described above. If an insulating film or a method of depositing an insulating film that does not oxidize or corrode the Cu wiring is used as the insulating film, there is no need to form the oxidation prevention film or the like.

As such an interlayer insulating film, polyimide and SOG (Spin 0nGla), which can be deposited with room temperature liquid, are used.
ss) film, photo-CVD film and microwave plasma CVD film that can be deposited at low temperatures, and RF plasma CVD film that reacts SiH4 and H and deposits in a reducing atmosphere of H2.
A single layer film such as a membrane or a multilayer film thereof can be considered.

Once the interlayer insulating film 14 made of any of the above-mentioned materials is formed, a contact hole 12 is formed for connecting the Cu wiring 6-1, which will become the first layer wiring, and the Cu wiring 6-2, which will become the second layer wiring. An opening is formed in the interlayer insulating film 14, and a barrier metal 13 is selectively buried in the contact hole.

After that, a barrier metal film 5-3 and a Cu wiring 6-2, which will become a second layer wiring, are formed in the same manner as described above.

According to this embodiment, since the Cu wiring does not become concave at the contact hole opening, the strength against disconnection is improved.

[Sixth Embodiment] FIG. 8 is a sectional view of the sixth embodiment of the present invention.
The same reference numerals as in the figures represent the same or equivalent parts.

In the above embodiments, only the barrier metal 5-1 was interposed between the diffusion layer 2 and the Cu wiring 6, but in order to reduce the contact resistance, the diffusion layer 2 and the barrier metal 5 were In between, M o S l 20) WSi20) T
It is desirable to form a silicide layer 16 made of PtSi or the like.

Therefore, in this embodiment, a silicide layer 16 is formed in the contact portion.
was formed, and only the contact portion had a structure of Cu6/barrier metal 5-1/silicide 16/diffusion layer 2.

The contact hole 15 can be formed by opening a contact hole 15 in the silicide 16, filling the contact hole 15 with a metal such as M o , Ws T is P t, and further performing heat treatment at about 600° C. Note that the silicide film may be formed by directly breaking a silicide film on this silicide 16.

According to this embodiment, contact resistance can be reduced and a semiconductor device with even higher performance can be provided.

In addition, in the above-mentioned six embodiments, the material of the metal wiring was explained as Cu, but it may be a Cu-based alloy, and in this case, the metal added may be Ag, AI, N.
i, Fe%Znx Zr, etc. are preferable.

Furthermore, the present invention is not limited to the six embodiments described above, but may be any combination of these embodiments as appropriate.

(Effects of the Invention) As is clear from the above description, the following effects are achieved according to the present invention.

(1) Since the surface of the metal thin film serving as the wiring material is covered with the barrier metal film, the adhesion with the insulating film is improved and peeling of the wiring material can be prevented.

(2) Since the surface of the metal thin film used as the wiring material is coated with an anti-oxidation film, metals such as Cu, which are easily oxidized but have high migration resistance, can now be used as the wiring material for semiconductor devices. , it becomes possible to improve the reliability of the semiconductor device.

(3) Even when a metal that is easily oxidized is used as the wiring material, SiO2 can be used as the insulating film, so it is possible to provide a highly reliable semiconductor device at low cost.

(4) Since heat treatment can be performed even in an atmosphere where oxygen exists, Cu wiring can be formed without complicating the manufacturing equipment and the maintenance of the manufacturing equipment.

(5) Forming a buffer film allows physical etching such as ion beam etching to be performed without damaging the semiconductor substrate, and also makes it easier to determine the end point of etching. Precise processing is possible.

Therefore, it becomes possible to form fine wiring patterns, and it becomes possible to provide a semiconductor device with a high degree of integration.

(6) Since the oxidation prevention film of the metal wiring is formed of an organic polymer, there is no alloying reaction and Cu has a low resistance value.
Wiring can now be formed.

(7) By connecting the barrier metal and the semiconductor layer via silicide, contact resistance can be reduced and a high-performance semiconductor device can be provided.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 3 is a sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 4 is a diagram showing the resistance change rate of the Cu/barrier metal structure. FIG. 5 is a diagram showing the annealing test results of the Cu/barrier metal structure. FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention. FIG. 8 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention.

Claims (25)

[Claims] (1) a semiconductor substrate with a semiconductor element formed on one main surface; an insulating film formed on the surface of the semiconductor substrate with a contact hole exposing a predetermined portion of the semiconductor substrate; and a surface of the insulating film. and a metal wiring containing at least copper formed through a conductive anti-oxidation film uniformly deposited within the contact hole, and an anti-oxidation film deposited to cover the metal wiring. A semiconductor device characterized by: (2) a semiconductor substrate with a semiconductor element formed on one main surface; an insulating film formed on the surface of the semiconductor substrate with a contact hole that exposes a predetermined portion of the semiconductor substrate; and inside the contact hole. a buried metal material buried to approximately the height of the insulating film; and a conductive oxidation preventive film uniformly deposited on the surface of the insulating film and the surface of the buried metal material. What is claimed is: 1. A semiconductor device comprising: a metal wiring containing: and an anti-oxidation film deposited to cover the metal wiring. (3) The semiconductor device according to claim 1 or 2, wherein a flattening film is formed in the recessed portion caused by the formation of the metal wiring. (4) The semiconductor device according to any one of claims 1 to 3, wherein a buffer film is formed on the surface of the insulating film on which the metal wiring is not formed. (5) a semiconductor substrate with a semiconductor element formed on one main surface; and a first insulating film formed on the surface of the semiconductor substrate with a first contact hole that exposes a predetermined portion of the semiconductor substrate. and a first metal wiring formed through a first conductive oxidation prevention film deposited on the surface of the first insulating film and in the first contact hole, and covering the first metal wiring. A first oxidation-preventing film is deposited as shown in FIG. the formed planarizing film; a second conductive anti-oxidant film deposited on the surfaces of the first anti-oxidant film and the planarizing film and in the second contact hole; and a second conductive anti-oxidant film. A semiconductor device comprising: a second metal wiring formed on a surface of a film; and a second anti-oxidation film deposited to cover the second metal wiring. (6) A buffer film is formed on at least one of the first insulating film surface on which the first metal wiring is not formed and the second insulating film surface on which the second metal wiring is not formed. A semiconductor device according to claim 5, characterized in that: (7) The semiconductor device according to claim 3 or 6, wherein the buffer film is made of a polyimide organic material. (8) The surface of the first oxidation prevention film and the planarization film and the second
8. The semiconductor device according to claim 5, wherein an interlayer insulating film is formed between the conductive oxidation prevention film and the conductive oxidation prevention film. (9) A third conductive oxidation prevention film is formed between the upper surface of the first metal wiring and the first oxidation prevention film. The semiconductor device according to any one of Item 8. (10) Claims 5 to 9, characterized in that a fourth conductive oxidation prevention film is formed between the second metal wiring and the second oxidation prevention film. The semiconductor device according to any one of paragraphs. (11) In the first contact hole, the semiconductor substrate and the first conductive anti-oxidation film are connected via silicide. The semiconductor device according to any one of paragraphs. (12) The conductive anti-oxidation film may include Mo, W, TiN,
TiW, V, Ta, Zr, Pt, Ti, Cr, Pb, A
The semiconductor device according to any one of claims 1 to 11, characterized in that the semiconductor device is a simple substance of 1, Au, Ni, Co, Fe, or Hf, or a silicide thereof. (13) The semiconductor device according to any one of claims 1 to 12, wherein the anti-oxidation film is copper fluoride obtained by fluorinating the surface of the metal wiring. (14) The antioxidant film may include Si, Al, Cu, Mo,
It is characterized by being any one of each nitride of W, Ti, Ta, or Cr, a polymer of benzotriazole, and a polymer of aromatic amine having an azo group or an amino group, or a laminate thereof. A semiconductor device according to any one of claims 1 to 12. (15) The planarization film is made of polyimide organic material, SOG
The semiconductor device according to any one of claims 3 to 14, characterized in that the semiconductor device is any one of a film, a microwave plasma CVD film, and an RF plasma CVD film, or a laminate thereof. . (16) The interlayer insulating film is Si_3N_4, SiO_
2 film, polyimide organic material, SOG film, photo CVD film, microwave plasma CVD film, and RF plasma CVD
16. The semiconductor device according to claim 5, wherein the semiconductor device is a single layer film of any one of these films or a multilayer film of these films. (17) The organic polymer as the antioxidant film is deposited to a thickness of at least several molecular layers. Semiconductor equipment. (18) forming a first insulating film on one main surface of the semiconductor substrate; forming a first contact hole exposing a predetermined portion of the semiconductor substrate in the first insulating film; forming a first buffer film on the surface of the first insulating film in a region other than the region where the first metal wiring is formed; and surfaces of the first insulating film and the first buffer film. , and forming a first conductive anti-oxidation film to cover the inside of the first contact hole; and forming a first metal thin film on the surface of the first conductive anti-oxidation film. forming a first oxidation preventive film to cover the first metal thin film; and forming the first oxidation preventive film to cover a region of the first metal thin film that will become the first metal wiring forming a second buffer film on the surface of the film; 1
a step of etching the metal thin film and the first conductive oxidation prevention film; a step of removing at least the second buffer film of the first and second buffer films; and a step of removing at least the first metal wiring. A method for manufacturing a semiconductor device, comprising the step of further forming a first oxidation prevention film on a side surface. (19) The method for manufacturing a semiconductor device according to claim 15, further comprising the step of forming a flattening film in the recesses created by the etching. (20) Following the steps set forth in claim 18, a step of forming a flattening film in the recesses caused by the etching, and forming a first metal thin film on the first oxidation prevention film. forming a second contact hole that exposes a portion; and forming a third buffer film on the surfaces of the first oxidation prevention film and the planarization film other than the region where the second metal wiring is formed. a step of depositing a second conductive anti-oxidation film so as to cover the first oxidation-preventing film, the planarizing film, the third buffer film, and the inside of the second contact hole; forming a second metal thin film on the surface of the second conductive oxidation-preventing film; depositing a second oxidation-preventing film to cover the second metal thin film; forming a fourth buffer film on the surface of the second antioxidant film so as to cover a region of the metal thin film that will become the second metal wiring; From the surface of the buffer film to the third buffer film exposed, the second anti-oxidation film and the second
a step of etching the metal thin film and a second conductive oxidation prevention film; a step of removing at least the third buffer film of the third and fourth buffer films; and a step of etching at least the second metal wiring. 1. A method of manufacturing a semiconductor device, further comprising the step of forming an anti-oxidation film on a side surface. (21) Claims further comprising the step of forming an interlayer insulating film between the surfaces of the first anti-oxidation film and the planarization film and the second conductive anti-oxidation film. 21. The method for manufacturing a semiconductor device according to item 20. (22) Claim 20, further comprising the step of forming a third conductive anti-oxidation film between the first metal thin film and the first anti-oxidation film. Alternatively, the method for manufacturing a semiconductor device according to item 21. (23) Claim 20, further comprising the step of forming a fourth conductive anti-oxidation film between the second metal thin film and the second anti-oxidation film. 23. The method for manufacturing a semiconductor device according to any one of items 22 to 22. (24) The method for manufacturing a semiconductor device according to any one of claims 18 to 23, wherein the buffer film is made of a resist or a polyimide-based organic material. (25) The method for manufacturing a semiconductor device according to any one of claims 18 to 24, wherein the etching is ion beam etching or sputtering.