JP4152164B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a wiring made of a metal including copper in a buried method.
[0002]
[Prior art]
In recent years, it has been known that copper (Cu) wiring is used as a wiring layer of a semiconductor device in order to improve the reliability of the wiring layer of the semiconductor device. Since Cu wiring in the wiring layer of the semiconductor device is difficult to be patterned by dry etching, a method of forming a groove in the interlayer insulating film and embedding copper in this groove (damascene method) is employed.
[0003]
As the interlayer insulating film, a silicon oxide film (SiO ₂ film) is mainly used. However, since Cu diffuses into the silicon oxide film (SiO ₂ film) and causes an increase in wiring resistance and wiring leakage, A method of forming a thin film having a barrier property to prevent diffusion of Cu is used.
[0004]
Various films have been studied as Cu diffusion preventing films, and tantalum (Ta) -based films are promising from the viewpoint of barrier properties and adhesion.
[0005]
Such a conventional technique for forming a copper wiring is disclosed, for example, in Patent Document 1, in which a hexagonal phase is formed between a silicon oxide film (SiO ₂ film) that is an interlayer insulating film and Cu when forming a Cu buried wiring. It has been disclosed that the problem of Cu diffusion during annealing at 500 ° C. can be prevented by using a TaN layer or a multilayer film of a hexagonal phase TaN layer and an α phase Ta as a barrier film.
[0006]
Hereinafter, a conventional process for forming a copper wiring will be described with reference to FIGS.
[0007]
Referring to FIG. 3, first, a silicon oxide film (SiO ₂ film) 202 is formed on a semiconductor substrate 201 on which a transistor (not shown) and a contact (not shown) are formed, and an etching stopper film such as a SiN film or a SiON film. After forming 203 about 50 nm, an interlayer insulating film 204 made of a silicon oxide film (SiO ₂ film) for forming a trench for embedding Cu is formed about 400 nm (FIG. 3A).
[0008]
Then, a photoresist 205 is applied and formed, exposed and developed and patterned (FIG. 3B), and the interlayer insulating film 204 is etched using this as a mask to form a wiring groove 206 shown in FIG. 3C. Form.
[0009]
Next, a Ta-based barrier film 207 such as Ta or TaN is sputtered to a thickness of about 30 nm and then a Cu sputtered film 208 is sputtered to a thickness of about 100 nm on the silicon substrate on which the wiring trench 206 is formed (FIG. 3D). ), A Cu plating film 209 having a thickness of about 800 nm is formed by electrolytic plating (FIG. 4A).
[0010]
The Cu plating film 209 formed by the electrolytic plating method has a specific resistance of 2.4 μΩ · cm (20 ° C.) which is slightly higher than that of bulk Cu (1.72 μΩ · cm (20 ° C.)) and has a small particle size. Therefore, electromigration (EM) resistance is low.
[0011]
Conventionally, the specific resistance can be reduced to about 1.9 μΩ · cm (20 ° C.) by annealing at a temperature of about 250 ° C. to 400 ° C., and at the same time, grain growth occurs and EM resistance is improved. It is known to do.
[0012]
Thereafter, planarization is performed until the surface of the interlayer insulating film 204 is exposed by a chemical mechanical polishing (CMP) method, whereby Cu can be embedded in the groove as shown in FIG. Next, the silicon substrate 201 is washed and dried, and then a Cu oxide protective film such as the SiN film 210 is formed on the entire surface by the plasma CVD method, so that the structure having the Cu embedded wiring shown in FIG. Realized.
[0013]
[Patent Document 1]
JP-A-9-17790 (paragraph numbers 0023 to 0026, FIG. 1)
[Non-Patent Document 1]
Thin Solid Films, Oxidation of Ta diffusion barrier layer for Cu metallizationin thermal annealing, Fusen Chen et, 388 (2001), PP27-33
[0014]
[Problems to be solved by the invention]
However, according to a report by Fusen Chen et al. According to Non-Patent Document 1, when Cu is deposited on Ta and annealed, a Ta oxide layer is formed at the Cu / Ta interface. It is reported that a Ta oxide layer is observed along the grain of Cu when annealed in an Ar atmosphere of 10 ⁻³ torr. It is considered that oxygen that causes oxidation of Ta is supplied from outside air through Cu grains.
[0015]
Therefore, when Ta is used as a barrier film for preventing Cu diffusion, Ta at the Cu / Ta interface is oxidized by annealing. It has been empirically found that when Cu is polished in a state where Ta of the barrier film is oxidized, the Cu film is peeled off along the Cu grains and easily becomes a wiring defect.
[0016]
The reason why the Cu film peels along the Cu grains is that Ta at the Cu / Ta interface is oxidized, which is considered to deteriorate the adhesiveness with Cu. There is a problem that invites.
[0017]
Therefore, the present invention provides a manufacturing method for improving the reliability of Cu wiring by preventing oxidation of Ta during annealing when Ta is used as a barrier film in a semiconductor device using Cu wiring. That is, the object of the present invention is to prevent or suppress the oxidation of the Ta film, which is a Cu diffusion preventing film, during Cu annealing, thereby preventing Cu peeling during Cu polishing after annealing and providing a highly reliable Cu wiring. Is to form.
[0018]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention includes a barrier film made of a tantalum layer film or a laminated film of a tantalum layer film and another alloy film in any one of a wiring groove and a contact hole formed on an insulating film of a semiconductor substrate. forming a first film forming step of forming a film, a second film forming step of forming a copper film on the barrier film by a method comprising an electrolytic plating method, an oxygen diffusion barrier layer on the copper layer a third film forming step of, after the third film forming step, a structure having a copper film heat treatment step of performing heat treatment of the copper film at a temperature of 250 ° C. to 400 ° C..
[0021]
Furthermore, the oxygen diffusion preventing film used in the method for manufacturing a semiconductor device of the present invention is a SiON film. The oxygen diffusion prevention film used in the method for manufacturing a semiconductor device of the present invention is made of cupric hydroxide, cuprous oxide, and copper carbonate formed by treating a Cu plating film with dilute hydrofluoric acid. Cu oxide film.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of a method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 is a cross-sectional structure diagram of a semiconductor device showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps. Here, a case where Cu wiring is applied to the first layer wiring is shown.
[0025]
Referring to FIG. 1A, in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, a silicon oxide film is formed on a silicon substrate 101 on which a transistor part (not shown) and a contact (not shown) are formed. (SiO ₂ film) An insulating film 102 is formed, and subsequently an etching stopper film 103 such as a SiN film or a SiON film is formed to a thickness of about 50 nm, and then a silicon oxide film (SiO ₂ film for forming a trench for embedding Cu is formed. Is formed to a thickness of about 400 nm.
[0026]
Next, a photoresist 105 is applied and formed thereon, exposed and developed, patterned (FIG. 1B), and then the interlayer insulating film 104 is etched using this as a mask to form the wiring trench shown in FIG. 1C. 106 is formed.
[0027]
Next, a Ta barrier film 107 is formed by sputtering on the silicon substrate on which the wiring trench 106 is formed. The barrier film is not limited to Ta, and may be a laminated structure of Ta and another alloy. The thickness of the barrier film is preferably 50 to 60 nm, and if it is thinner than this, the barrier property is insufficient.
[0028]
Subsequently, the Cu sputtered film 108 is sputtered to about 100 nm (FIG. 1D), and a Cu plated film 109 is formed to a thickness of about 800 nm by an electrolytic plating method (FIG. 2A). Next, an SiN film, which is an oxygen diffusion prevention film 110 for preventing Ta, which is a barrier film, from being oxidized by oxygen supplied from the outside during annealing, is formed by a plasma CVD method with a film thickness of about 20 nm. It is formed on the Cu plating film 109 (FIG. 2B).
[0029]
The oxygen diffusion prevention film 110 is not limited to the SiN film, but cupric hydroxide, cuprous oxide formed by treating the SiON film or Cu plating film with dilute hydrofluoric acid, Alternatively, a Cu oxide film made of copper carbonate may be used.
[0030]
Subsequently, annealing is performed at a temperature of about 250 ° C. to 400 ° C. By forming an oxygen diffusion prevention film before annealing, it is possible to prevent or suppress oxygen existing in the annealing atmosphere from diffusing in Cu along the Cu grains and oxidizing Ta at the Cu / Ta interface. it can.
[0031]
Thereafter, planarization is performed by chemical mechanical polishing (CMP) until the surface of the interlayer insulating film 104 is exposed, so that Cu is embedded in the groove as shown in FIG.
[0032]
Next, the silicon substrate 101 is washed and dried, and then a Cu oxidation protection film such as the SiN film 111 is formed on the entire surface by the plasma CVD method, so that the structure having the Cu embedded wiring shown in FIG. Realized.
[0033]
【The invention's effect】
As described above, according to the present invention, by forming an oxygen diffusion preventing film, oxygen existing in the atmosphere during annealing diffuses in Cu along the Cu grains, and oxidizes Ta at the Cu / Ta interface. This has the effect of preventing or suppressing the operation.
[0034]
Since the adhesion between Cu and Ta is maintained by suppressing the oxidation of Ta, defects in the Cu wiring due to peeling of the Cu film that occur when the adhesion is low when polishing the Cu film by the CMP method. Generation | occurrence | production can be prevented and the improvement of the reliability of Cu wiring can be measured.
[Brief description of the drawings]
FIG. 1 is a manufacturing process cross-sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a manufacturing process sectional view of the semiconductor device in the embodiment of the invention, following FIG. 1;
FIG. 3 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.
4 is a manufacturing process sectional view of the conventional semiconductor device, following FIG. 3;
[Explanation of symbols]
101, 201 Semiconductor substrate 102, 202 Silicon oxide film (SiO ₂ film)
103, 203 Etching stopper film 104, 204 Silicon oxide film (SiO ₂ film) Interlayer insulating film 105, 205 Photo resist 106, 206 Wiring groove 107, 207 Barrier film 108, 208 Cu sputtered film 109, 209 Cu plating film 110 Oxygen diffusion Prevention film 111,210 SiN film

Claims (3)

A first film forming a barrier film made of a tantalum layer film or a laminated film of a tantalum layer film and another alloy film in any one of a wiring groove and a contact hole formed on an insulating film of a semiconductor substrate. Process,
A second film forming step of forming a copper film on the barrier film by a method including an electrolytic plating method;
A third film forming step of forming an oxygen diffusion preventing film on the copper film;
After the third film forming step, it has a copper film heat treatment step of performing heat treatment of the copper film at a temperature of 250 ° C. to 400 ° C.,
The oxygen diffusion prevention film is a Cu oxide film made of cupric hydroxide, cuprous oxide, and copper carbonate formed by treating a Cu plating film with dilute hydrofluoric acid. Manufacturing method. The method of manufacturing a semiconductor device according to claim 1, wherein the second film forming step is a step of forming the copper film by a sputtering method and then forming the copper film by an electrolytic plating method. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of planarizing the copper film by a CMP method until the surface of the insulating film is exposed after the copper film heat treatment step.

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