JPH0474457A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent increases in disconnection and resistance of wiring in contact holes by providing the second conductive layer connected to the first conductive layer though the contact holes and areas of an oxidation-resistant material formed on at least parts of the surface of the second conductive layer. CONSTITUTION:Contact holes 107A are formed to N-type diffusion layers (sources) 105 through an interlayer insulating film 106A after the film 106A is formed on the entire surface of a substrate 101. Then the lower electrodes 108, capacitor insulating films 109, and upper electrodes 110 of capacitors and the cell capacitors of DRAMs are formed on the contact holes 107A. After covering the entire surface with an interlayer insulating film 106B, another contact holes 107B reaching the N-type diffusion layers 105 are formed. Thereafter, bit lines (second conductive layers) 111 are formed on the insulating film 106B and contact holes 107B. Then a film 112 of an oxidation-resistant material, such as SiN, is formed. After forming the film 112, an interlayer insulating film (second insulating layer) 113 is formed on the film 112 with large level differences in the vicinity of the bit lines 111.

Description

[Detailed Description of the Invention] [Object of the Invention (Industrial Application Field) The present invention relates to a semiconductor device and a method for manufacturing the same;
It is particularly used for high-density LSIs having fine wiring.

(Prior Art) Conventionally, a semiconductor device, for example, a DRA formed with a bit line
The M memory cell has a structure as shown in FIGS. 8(a) to 8(C). Here, the figure (b) is a cross-sectional view along the line AA' in the figure (a), and the figure (c) is a cross-sectional view taken along the line A-A' in the figure (a).
- It is a sectional view along the B' line. Further, 701 is a P-type semiconductor substrate, 702 is an element isolation oxide film, 703 is a silicon oxide film, 704 is a gate electrode of MOSFET, and 705 is an N
Type diffusion layer, 706A, 706B are interlayer insulating films, 707A
, 707B is a contact hole, 708 is a lower electrode of the capacitor, 709 is a capacitor insulating film, 710 is an upper electrode of the capacitor, and 711 is a bit line.

Note that a flattened interlayer insulating film, such as a BPSG film, is usually formed on the memory cell.

Further, metal (eg, A, Q) wirings are formed on the insulating film. Furthermore, a passivation film is formed on the metal wiring to complete the DRAM. Below, DRA
The manufacturing method until M is completed will be explained with reference to FIGS. 8 to 10.

First, as shown in FIG. 8, an element isolation oxide film 702 is formed on a P-type semiconductor substrate 701. Furthermore, a silicon oxide film 703, a gate electrode 704, and an N-type diffusion layer 705 are each formed on the element region of the P-type semiconductor substrate 701 by well-known methods to form a MOSFET. After forming an interlayer insulating film 706A on the entire surface, an N-type diffusion layer (source) 705 is formed.
A contact hole 707A is opened to reach the contact hole 707A. Also,
The lower electrode 7 of the capacitor is placed on the contact hole 707A.
08, capacitor insulation H709 and capacitor upper electrode 710 are formed to form a DRAM cell capacitor.

After forming an interlayer insulating film 706B on the entire surface, an N-type diffusion layer (
A contact hole 707B reaching the drain) 705 is opened. After this, a bit line 711 is formed on the interlayer insulating film 706B and the contact hole 707B. Here, the bit line 711 is formed by depositing a silicide film such as MoSi2 or WSi2 by sputtering.

Next, as shown in FIG. 9, an interlayer insulating film 712 is formed on the entire surface.
For example, silicate glass (BPSG film) containing boron (B), phosphorus (P), etc. is formed. Here, the same figure (b
), the level difference in the interlayer insulating film 712 is large near the bit line 711.

Next, as shown in FIG. 10, high-temperature heat treatment (annealing) is performed in an oxidizing atmosphere, and the interlayer insulating film 712 is
Flatten the surface. At this time, the oxidizing agent is applied to the interlayer insulating film 71.
2 and oxidizes the bit line 711 made of a silicide film.

Therefore, an oxide film 713 is formed on the surface of the bit line 711. Thereafter, a metal (eg, AF) wiring 714 is formed on the planarized interlayer insulating film 712. Further, a passivation film 715 is formed on the entire surface to complete the DRAM.

However, in the manufacturing method described above, the bit line 711 formed by sputtering has a poor step cover lane, and the contact hole 707 is smaller than that on a flat surface.
It is known that within B, the film thickness becomes thinner. Therefore, if heat treatment is performed in an oxidizing atmosphere in this state, the thinned portion of the bit line 711 in the contact hole 707B will be entirely oxidized, causing disconnection and an increase in resistance. In other words, there is a drawback that sufficient yield and reliability cannot be obtained.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor device has poor wiring step coverage in the contact hole portion. For this reason,
When heat treatment is performed later, the oxidizing agent reacts with the wiring and forms an oxide film, which has the disadvantage of causing wire breakage and increased resistance in areas where the wiring is thin in the contact hole.

The present invention has been made to solve the above-mentioned drawbacks, and is a semiconductor device and method for manufacturing the same that can achieve high yield and high reliability by preventing disconnection of wiring and increase in resistance in contact holes. The purpose is to provide

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a semiconductor device of the present invention includes a first conductive layer and an insulating layer having a contact hole reaching the first conductive layer. a second conductive layer connected to the first conductive layer through the contact hole; and an oxidation-resistant material formed on at least a portion of the surface of the second conductive layer. There is.

In the method for manufacturing a semiconductor device of the present invention, first, a first conductive layer is formed on a surface region of a semiconductor substrate, and a first insulating layer is formed on the semiconductor substrate. Further, a contact hole reaching the first conductive layer is formed in the first insulating layer. Furthermore, after forming a second conductive layer on the entire surface, the second conductive layer is patterned. Further, an oxidation-resistant material is formed on the entire surface, and a second insulating layer is formed on the entire surface. After this, heat treatment is performed in an oxidizing atmosphere.

Further, in the method for manufacturing a semiconductor device of the present invention, first, a first conductive layer is formed in a surface region of a semiconductor substrate, and a first insulating layer is formed on the semiconductor substrate. Further, a contact hole reaching the first conductive layer is formed in the first insulating layer. Furthermore, a second conductive layer is formed on the entire surface, and an oxidation-resistant material is formed on the entire surface. Further, the oxidation-resistant material and the second conductive layer are patterned to form a second insulating layer over the entire surface. After step 2, heat treatment is performed in an oxidizing atmosphere.

(Function) According to the above configuration, the oxidation-resistant material is formed on at least a portion of the surface of the second conductive layer.

Therefore, it is possible to prevent wire breakage and increase in resistance within the contact hole, and it is possible to provide a semiconductor device with high yield and high reliability.

Further, according to the above method, the thinned portion of the conductive layer inside the contact hole can be covered with the oxidation-resistant material. Further, if necessary, a part of the surface of the conductive layer outside the contact hole can be covered with an oxidation-resistant material. Therefore, it is possible to reduce the resistance of the wiring without causing disconnection or the like.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a semiconductor device according to an embodiment of the present invention. Here, the figure (b) is AA' in the figure (a).
A cross-sectional view taken along line B-B' in FIG. 3(a). Here, 101 is a P-type semiconductor substrate, 102 is an element isolation oxide film, 103 is a silicon oxide film,
104 is the gate electrode of the MOSFET, 105 is the N-type diffusion layer (first conductive layer), 106A and 106B are interlayer insulating films (insulating layers), 107A and 107B are contact holes, 108 is the lower electrode of the capacitor, and 109 is the capacitor insulation The film 110 is the upper electrode of the capacitor, and 111 is the bit line (second conductive layer).

That is, on the P-type semiconductor substrate 101, an element isolation oxide film 1 is formed.
02 is formed. Further, a silicon oxide film 103 and a gate electrode 104 are provided on the element region of the P-type semiconductor substrate 101.
, and an N-type diffusion layer 105 are formed, respectively, and constitute a MOSFET. An interlayer insulating film]06A is formed on the entire surface, and an N layer is formed on the interlayer insulating film 106A.
Contact hole 1 reaching type diffusion layer (source) 105
07A is drilled. In addition, contact hole 10
A capacitor lower electrode 108, a capacitor insulating film 109, and a capacitor upper electrode 110 are formed on the capacitor 7A to constitute a DRAM cell capacitor. An interlayer insulating film 106B is formed on the entire surface, and an interlayer insulating film 1
A contact hole 107B reaching the N-type diffusion layer (drain) 105 is opened in 06B. A bit line 111 made of a silicide film such as MoSi2 or WSi2 is formed on the interlayer insulating film 106B and the contact hole 107B. Also, bit line 1
On the surface of 11, an oxidation-resistant material 112 made of, for example, 513N4 is formed.

According to such a configuration, the surface of the bit line 111 is covered with an oxidation-resistant material 112. In other words, as can be seen from the same figures (a) and (b), since the thinned part of the bit line 111 in the contact hole 107B is covered with the oxidation-resistant material 1]2, it is not exposed to the oxidizing agent during heat treatment. Never oxidized. Therefore, it is possible to prevent the bit line 111 in the contact hole 107B from being disconnected or increasing its resistance value due to oxidation.

2 to 4 show a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 2, an element isolation oxide film 102 is formed on a P-type semiconductor substrate 101. Furthermore, a silicon oxide film 103, a gate electrode 104, and an N-type diffusion layer (first conductive layer) 105 are each formed on the element region of the P-type semiconductor substrate 101 by well-known methods to form a MOSFET. After forming an interlayer insulating film 106A on the entire surface, a contact hole]07A reaching the N-type diffusion layer (SOS) 105 is opened. Further, a capacitor lower electrode 108, a capacitor insulating film 109, and a capacitor upper electrode 110 are formed on the contact hole 1.07A, thereby forming a DRAM cell capacitor. After forming an interlayer insulating film 106B over the entire surface, a contact hole 107B reaching the N-type diffusion layer (drain) 105 is opened. Thereafter, a bit line (second conductive layer) 11] is formed on the interlayer insulating film 106B and the contact hole 107B. Here, the bit line 111 is, for example, M o S i 2 , W S i
It is formed by depositing a silicide film such as No. 2 by sputtering.

Next, as shown in FIG.
, for example, forming a SiN film. In addition, oxidation-resistant material 11
2, an interlayer insulating film (second insulating layer) 113, for example, silicate glass (B) containing boron (B), phosphorus (P), etc.
PSG film) is formed. Here, as shown in FIG. 2(b), in the vicinity of bit II 111, the interlayer insulation [1
The step difference in Yu 3 is getting bigger.

Next, as shown in Figure 4, in an oxidizing atmosphere,
A high-temperature heat treatment (annealing) is performed to form the interlayer insulating film 113.
Flatten the surface. At this time, the oxidizing agent is
3, or the surface of the bit line 111 is covered with the oxidation-resistant material 112.
Bit line 111 within 07B is never oxidized. Thereafter, although not shown, a metal (for example, A[) wiring is formed on the interlayer insulating film 113. Further, a passivation film is formed on the entire surface to complete the DRAM.

According to such a method, the oxidation-resistant material can also be applied to the thinned portion of the bit line 111 in the contact hole 107B]
Since the contact hole 107B is covered, the bit line 111 inside the contact hole 107B will not be oxidized even if heat treatment is performed thereafter. Therefore, disconnection of the bit line 111 and increase in resistance value can be prevented.

By the way, in the above embodiment, when an N os j2 film is used for the bit line 111, the mo s i 2 film is
It is known that oxidation reduces the sheet resistance value. In other words, as long as it does not cause disconnection, etc.
This may occur if you intentionally want to oxidize the bit line 111.

Such requirements can be satisfied by the method shown below.

5 to 7 show a method of manufacturing a semiconductor device according to another embodiment of the present invention. Note that the same parts as in the embodiment described above are given the same reference numerals.

First, as shown in FIG. 5, an element isolation oxide film 102 is formed on a P-type semiconductor substrate 01. Further, a silicon oxide film 103 and a gate electrode 104 are provided on the P-type semiconductor substrate 101.
, and an N-type diffusion layer (first conductive layer) 105.
Form an SFET. Contact hole all over] 07A
06A is formed. After this, the lower electrode 108, the capacitor insulating film 109, and the upper electrode 1
．． A DRAM cell capacitor consisting of 10 cells is formed.

Interlayer insulating film 1 having contact holes 107B on the entire surface
Form 06B. Next, for example, MoS i2 is applied to the entire surface.
, WS i2 or the like is formed. Further, an oxidation-resistant material 112 such as a SiN film is provided on the silicide film.
form. Thereafter, the oxidation-resistant material 112 and the silicide film are laminated and patterned to form the bit line (second conductive layer) 111. Here, the oxidation-resistant material 112 is
It exists only on the top surface of the bit line 111 and does not exist on its side surfaces.

Next, as shown in FIG. 6, an interlayer insulating film (second insulating layer) 113, such as boron (B) or phosphorus
), etc., is formed. Here, as shown in FIG. 2(b), the bit line 111
In the vicinity, the step difference in the interlayer insulating film 113 is large.

Next, as shown in FIG. 7, in an oxidizing atmosphere,
A high temperature heat treatment (annealing) is performed to planarize the surface of the interlayer insulating film 113. At this time, the oxidizing agent is applied to the interlayer insulating film 113.
Since the bit line 111 passes through the inside thereof, except for the upper surface covered with the oxidation-resistant material 112, the side and lower surfaces of the bit line 111 are oxidized to form an oxide film 114. On the other hand, the bit line 111 in the contact hole 107B is made of oxidation-resistant material 11
2, so it will not be oxidized. Thereafter, a metal (for example, A
Ω) Form wiring. In addition, a panhaenyong film is formed on the entire surface to complete the DRAM.

According to this method, only the upper surface of the bit line 111 is covered with the oxidation-resistant material 112. Therefore, the resistance value of the bit line 111 can be lowered by consciously oxidizing the side and bottom surfaces of the bit line [1] to the extent that disconnection or the like does not occur. Further, since the oxidizing agent does not reach the bottom of the contact hole 107B, the thinned portion of the bit line 111 inside the contact hole 107B is not oxidized, and disconnection and increase in resistance can be prevented.

It goes without saying that in the above embodiment, the bit line 111 may have a stacked structure of a polycrystalline silicon film and a silicide film. In addition, contact hole 10
7B is not limited to one that reaches the substrate 101.

Furthermore, in the above embodiment, the semiconductor memory device D
I have explained RAM, but it is not limited to high-density LS with miniaturized semiconductor elements.
It is possible to apply to all of I.

[Effects of the Invention] As described above, according to the semiconductor device and the manufacturing method thereof of the present invention, the following effects are achieved.

At least a portion of the surface of the patterned conductive layer is covered with an oxidation-resistant material. Therefore, it is possible to prevent wire breakage and increase in resistance within the contact hole, and it is possible to provide a semiconductor device with high yield and high reliability.

[Brief explanation of drawings]

1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIGS. 2 to 4 are diagrams each showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 5 to 7 The figures each show a method of manufacturing a semiconductor device according to another embodiment of the present invention, and FIGS. 8 to 10 each show a method of manufacturing a conventional semiconductor device. 101- P-type semiconductor substrate, 102... element isolation oxide film, 103... silicon oxide film, 104... MOSF
ET gate electrode, 105...N type diffusion layer, 106A
, 106B... interlayer insulating film, 107A107B...
Contact hole, 108... Lower electrode of capacitor, ]09... Capacitor insulating film, 110... Upper electrode of capacitor, 111... Bit line, 112...
Oxidation-resistant material, 113... Interlayer insulating film, 4... Oxide film.

Claims (5)

[Claims] (1) a first conductive layer; an insulating layer having a contact hole reaching the first conductive layer; formed on the insulating layer and connected to the first conductive layer via the contact hole; A semiconductor device comprising: a second conductive layer; and an oxidation-resistant material formed on at least a portion of a surface of the second conductive layer. (2) The semiconductor device according to claim 1, wherein the oxidation-resistant material is formed only on the upper surface of the second conductive layer. (3) The semiconductor device according to claim 1, wherein the oxidation-resistant material is formed on an upper surface and side surfaces of the second conductive layer. (4) forming a first conductive layer on a surface region of a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; and forming a first conductive layer on the first insulating layer. forming a second conductive layer on the entire surface; patterning the second conductive layer; forming an oxidation-resistant material on the entire surface; 1. A method for manufacturing a semiconductor device, comprising the steps of: forming an insulating layer; and performing heat treatment in an oxidizing atmosphere. (5) forming a first conductive layer on a surface region of a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; and forming a first conductive layer on the first insulating layer. forming a second conductive layer on the entire surface; forming an oxidation-resistant material on the entire surface; and patterning the oxidation-resistant material and the second conductive layer. A method for manufacturing a semiconductor device, comprising: forming a second insulating layer over the entire surface; and performing heat treatment in an oxidizing atmosphere.