JPS63169047A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63169047A
JPS63169047A JP130487A JP130487A JPS63169047A JP S63169047 A JPS63169047 A JP S63169047A JP 130487 A JP130487 A JP 130487A JP 130487 A JP130487 A JP 130487A JP S63169047 A JPS63169047 A JP S63169047A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
bpsg
grown
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP130487A
Other languages
Japanese (ja)
Inventor
Hiroshi Ito
浩 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
YAMAGUCHI NIPPON DENKI KK
Original Assignee
YAMAGUCHI NIPPON DENKI KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by YAMAGUCHI NIPPON DENKI KK filed Critical YAMAGUCHI NIPPON DENKI KK
Priority to JP130487A priority Critical patent/JPS63169047A/en
Publication of JPS63169047A publication Critical patent/JPS63169047A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a reflow having large step moderation at lower temperature by forming a nitride film under the BPSG film of a semiconductor device in which the BPSG film is used as an interlayer film to allow the BPSG film to reflow in a steam atmosphere. CONSTITUTION:An oxide film 16 and a nitride film 17 are grown on a P-type MOS with a polycrystalline silicon film 15 as a gate material on an N-type silicon substrate 11, and a BPSG film 18 is grown thereon. A hole is opened in the same shape as that of a contact at part of the film 17 at a contact part 19, and the film 17 is always formed at a lower layer of the film 18 at the part except the hole. That is, the film 17 is formed under the film 18 to eliminate the oxidation of a P-type diffused layer region 12 to cause a P-type diffused layer resistance to rise. After the film 18 reflows, the contact part 19 is opened by PR technique and dry etching technique, heat treated in a nitrogen atmosphere, thereby alleviating the step of the contact part 19.

Description

【発明の詳細な説明】 1]産業上の利用分野〕 本発明は半導体装置に関し、特に眉間膜にBP8G膜を
用いた半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION 1] Industrial Application Field The present invention relates to a semiconductor device, and particularly to a semiconductor device using a BP8G film for the glabellar membrane.

(従来の技術〕 従来、半導体装置の層間膜としてはBp s c;膜が
一般に使用されている。
(Prior Art) Conventionally, a Bpsc; film has generally been used as an interlayer film of a semiconductor device.

1発明が解決しようとする問題点〕 かかる従来の層間膜の構造においては、層間B1)S 
GIliのりフローとして、より低温の処理によって短
時間に層間膜の段差緩和のためのりフロー効果が得られ
るような水蒸気雰囲気中での熱処理が実施できない。す
なわち、水蒸気雰囲気中で熱処理を行うと、酸化種が容
易に[3PSG膜を通り抜けBeSO4摸より下層のシ
リコン基板および多結晶シリコン膜等を激しく酸化して
しまうため、実施できない。このため、従来の層間膜の
場りにはりフロー効果が少ないとわかっていても、窒素
雰囲気での熱処理が実施されてきた。このため、近年の
゛L導体装置のVJ3:iにおいては、低温化傾向に反
するという問題があった。
1) Problems to be Solved by the Invention] In the structure of such a conventional interlayer film, the interlayer B1)S
As a GIli glue flow, heat treatment cannot be performed in a steam atmosphere where a glue flow effect for alleviating the step difference in the interlayer film can be obtained in a short time by processing at a lower temperature. That is, heat treatment cannot be carried out in a water vapor atmosphere because oxidizing species easily pass through the [3PSG film and violently oxidize the silicon substrate, polycrystalline silicon film, etc. below the BeSO4 film. For this reason, heat treatment in a nitrogen atmosphere has been carried out for conventional interlayer films even though it is known that the flow effect is small. For this reason, VJ3:i of recent L conductor devices has had the problem of going against the trend toward lower temperatures.

本発明の目的は、リフロー効果の高い■つより低温で短
時間に処理することができる半導体装置を提供すること
にある。
An object of the present invention is to provide a semiconductor device that has a high reflow effect and can be processed at a lower temperature in a shorter time.

1問題点を解決するための手段“1 本発明は層間膜としてHP S C,膜を用いる半導体
装置において、[’i r’ S G膜と、このB F
’ S G l漠により絶縁されている配線層と、前記
Bp s c;膜および前記配線層間で1つコンタクト
部を除く領域に一様に形成させた窒化膜とを含んで構成
される。
1 Means for Solving Problems 1 The present invention provides a semiconductor device using a HP SC film as an interlayer film.
The wiring layer is insulated by a S G layer, and a nitride film is uniformly formed in a region between the Bp sc film and the interconnect layer except for one contact portion.

すなわち、上述した従来のB ITI S c;膜のみ
による層間膜構造では゛i導木装置の製逍染件、つまり
層間1摸のリフローのための熱処理染件を検討しなけれ
はならないのに対し、本発明ではその構造を絶縁用層間
膜と配線層との間にさらに一様になるような窒化膜を少
なくとも形成することにより解消させるらのである。
In other words, in the conventional interlayer film structure using only the BITIS film as described above, it is necessary to consider the manufacturing and dyeing of the i-guiding device, that is, the heat treatment dyeing for reflow of one layer. In the present invention, this structure is solved by forming at least a nitride film between the insulating interlayer film and the wiring layer to make it more uniform.

(実施例j 次に、本発明の実施例について図面を参照して説明する
(Example j) Next, an example of the present invention will be described with reference to the drawings.

第1図は本発明の第一の実施例を説明するための断面図
であり、特にp rr:i M OS半導体装置の断面
の一部を模式的にあられしたものである。
FIG. 1 is a cross-sectional view for explaining the first embodiment of the present invention, and in particular, a part of the cross-section of a p rr:i MOS semiconductor device is schematically shown.

第1図に示すように、N型シリコン基板11上に多結晶
シリコン1模15をゲーI・材料としたP型MO8上に
酸1ヒ膜16.窒化膜17を成長させ、−εの1.に口
P S G膜18を成長させた構造である。尚、=1ン
タク1一部19では窒化膜17の一部に=1ンタクI・
と同形で穴がおいているが、それ以外α)部分では必ら
ずB r)SG膜18より下層に窒(ヒIts!17を
形成する。
As shown in FIG. 1, an acid-1 arsenic film 16 is placed on a P-type MO8 made of polycrystalline silicon 15 as a GaI material on an N-type silicon substrate 11. The nitride film 17 is grown and -ε is 1. This is a structure in which a thin PSG film 18 is grown. In addition, in =1 tank 1 part 19, =1 tank I is applied to a part of the nitride film 17.
It has the same shape as , and has a hole, but in other parts α), a nitrogen film 17 is always formed below the SG film 18.

次に、かかる第一の実施例の製造工程について説明する
。まづ、N型シリコン基板11−ヒにLOL: OS法
により厚いフィールド酸化膜13として8 [) 0 
[’1人程度の膜を熱酸化により形成した後、ゲート酸
化膜14として400人程変力膜を熱酸1ヒにより成長
させる。次に、全面に不純物を導入した一2結晶シリコ
ン膜を成長させ、PR技術によりデー1〜金属及び配線
部用に前記多結晶シリコン膜をバターニング後、多結晶
シリコン膜15を形1」(する。次に、900℃の水蒸
気雰囲気中で10汁間酸化し酸化膜16を形成する。次
に、かかる酸化膜16を形成したN型シリコン基板11
上に11’ CV D法により窒化1模17を厚さ10
00人程度一様に成長させる。しかる後、B P S 
G膜18を常圧CV D法により厚さ1000 (’)
程度度成長させ、900℃の水蒸気雰囲気中で20分間
の熱処理を実施する。この熱処理により、r(PSG膜
1膜力8差を緩和する。一方、従来は前記水、蒸気雰囲
気中での熱処理においては、P型拡散層領域12の表面
が酸化されI〕型型数散層抵抗上昇してしまうことがあ
−)なか、この第一の実施例のように、B f’ S 
(−;膜18の下方に9.(ヒ膜17を形成することに
より、Pを拡散層領域12が酸化され[〕型拡散層抵抗
が−1−dすることは無くなる。次に、B P S G
膜18のリフロー後、コンタクト部1つをI” R技術
とドライエツチング技術を用いて開口し900℃の窒素
雰囲気中で熱処理することにより、コンタクI・部19
の段差を緩和する。最後に、このコンタクI・部19の
表面にアルミニウムをスパッタ法により1・1着させ、
P R技術とドライエツチング技術とにより、配線用と
なるアルミニウム配線20を形成する。
Next, the manufacturing process of the first embodiment will be explained. First, on the N-type silicon substrate 11-H, a thick field oxide film 13 is formed using the OS method.
['After forming a film of about 1 layer by thermal oxidation, a variable strength film of about 400 layers is grown as the gate oxide film 14 by thermal oxidation. Next, a dodecrystalline silicon film doped with impurities is grown on the entire surface, and after patterning the polycrystalline silicon film for metal and wiring parts using PR technology, a polycrystalline silicon film 15 is formed into a shape 1'' ( Next, the oxide film 16 is formed by oxidation for 10 minutes in a steam atmosphere at 900° C. Next, the N-type silicon substrate 11 on which the oxide film 16 is formed is
11' CVD method is used to deposit nitrided 1 pattern 17 on top to a thickness of 10
00 people will grow uniformly. After that, BPS
G film 18 was formed to a thickness of 1000 (') by normal pressure CVD method.
After a certain degree of growth, heat treatment is performed for 20 minutes in a steam atmosphere at 900°C. This heat treatment alleviates the difference in film strength of r(PSG film 1).On the other hand, in the conventional heat treatment in the water or steam atmosphere, the surface of the P-type diffusion layer region 12 is oxidized and the I]-type diffusion layer is oxidized. However, as in this first embodiment, B f' S
(-; By forming the 9. S.G.
After reflowing the film 18, one contact part 19 is opened using the I''R technology and dry etching technology and heat treated in a nitrogen atmosphere at 900°C.
Alleviate the difference in level. Finally, aluminum is deposited one by one on the surface of this contact I portion 19 by sputtering.
Aluminum wiring 20 for wiring is formed using PR technology and dry etching technology.

第2図は本発明の第二の実施例を説明するための半導体
装置の断面図である。この第二の実施例は2 Jf?J
のB P S G l摸および2層の窒化膜ならびに2
層の多結晶シリコン膜を使用したI・ランジスタを;l
’: している。
FIG. 2 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention. This second embodiment is 2 Jf? J
B P S G l model and two layers of nitride film and two
An I transistor using a layer of polycrystalline silicon film;
': are doing.

第2図に示すように、第一のB P S (”;膜27
の直1・°には第一の窒化膜26が形成されている。ま
た、第一の多結晶シリコン膜25をいわゆるゲートポリ
シリとして使用し、第二の多結晶シリコン11Q 2 
Qを配線として使用する。この第二の多結晶シリコン膜
29とアルミ配線34を絶縁するために第二のI3 P
 S G膜32を形成しているが、その1・層には第一
のl(I” S G I摸27の下の第一の窒化膜20
と同様に第二の窒化膜31が形成されている。これら窒
化1漠により、それぞれのII P S C;膜:g7
.′−i2のためのりフローの際に下地の「゛型シリ=
1ンJ、!:板21と第一および第二の多結晶シリコン
膜25.29を酸化することなしにリフローすることが
できる。また、このよっに、各RF’ S G膜の[に
窒化膜26.31を形成していることに、Lす、それぞ
れのB P S G l模27,32を水蒸気雰囲気中
でより低温でリフローすることができる。
As shown in FIG.
A first nitride film 26 is formed on the right 1°. Further, the first polycrystalline silicon film 25 is used as a so-called gate polysilicon film, and the second polycrystalline silicon film 11Q 2
Use Q as wiring. In order to insulate this second polycrystalline silicon film 29 and aluminum wiring 34, a second I3P
The S G film 32 is formed, and its first layer includes the first nitride film 20 under the S G I film 27.
A second nitride film 31 is formed similarly. By these nitriding methods, each II P SC; membrane: g7
.. During the glue flow for ′-i2, the base “゛-type series =
1 J,! : Reflow can be performed without oxidizing the plate 21 and the first and second polycrystalline silicon films 25 and 29. In addition, since the nitride film 26, 31 is formed on each RF' S G film, each B P S G film 27, 32 is formed at a lower temperature in a steam atmosphere. Can be reflowed.

次に、この第二の実施例の製造工程について説明する。Next, the manufacturing process of this second embodiment will be explained.

まづ第一のr3 r S G膜27のリフローまでは前
記第一の実施例と同じである。この第二の実施例では、
第一のコンタク1〜部28の開口後、第一の多結晶シリ
コン膜2つを1.、、 P CV I)法により厚さ4
000程度度成長させ、しかる後900℃の水蒸気雰囲
気中で10分間熱処理し、酸化膜30を成長させる。次
に、第二の窒F膜31をこの酸化膜30の上にL P 
CV D法により成長させた後、第二のB[)SG膜3
2を成長させ、しかる後水蒸気雰囲気中で熱処理してリ
フローする。最後に、第二のコンタク1〜部33を開口
しアルミ配線34を形成する。このように、多層のB 
P S cr膜27.32を層間膜として使用する場合
にも各々のB P S G膜の下に窒化膜26.31を
形成することにより水蒸気雰囲気中でのB P S G
膜のりフローをより低温で実施することができる。特に
、熱処理を減らす効果は非常に大きい。
First, the steps up to the reflow of the first r3rSG film 27 are the same as in the first embodiment. In this second example,
After opening the first contacts 1 to 28, the two first polycrystalline silicon films are 1. ,, Thickness 4 by PCV I) method
After that, the oxide film 30 is grown by heating at 900° C. for 10 minutes in a steam atmosphere. Next, a second nitride F film 31 is placed on top of this oxide film 30.
After growing by CVD method, the second B[)SG film 3
2 is grown, then heat treated in a steam atmosphere and reflowed. Finally, the second contacts 1 to 33 are opened and the aluminum wiring 34 is formed. In this way, the multilayer B
Even when the P S CR film 27.32 is used as an interlayer film, a nitride film 26.31 is formed under each B P S G film to prevent B P S G in a water vapor atmosphere.
Membrane flow can be carried out at lower temperatures. In particular, the effect of reducing heat treatment is very large.

以」−5二つの実施例について説明したが、BPS(:
;膜の直下に形成する窒化膜はこれらに限らず、これら
11 P S (i膜および窒化膜の間に常圧CVD成
長法による酸化膜やPSG膜があっても同様の代能が達
成される。
Although two embodiments have been described, BPS (:
The nitride film formed directly below the film is not limited to these 11PS (the same performance can be achieved even if there is an oxide film or PSG film grown by atmospheric pressure CVD between the i film and the nitride film). Ru.

1発明の効果1 以ト説明したように、本発明はBPSG膜を層間膜とし
て使用する半導体装置において層間のB1+ 8(’、
y 膜下に窒化膜が存在することにより、水蒸気雰囲気
中でのB P S G膜のりフローを可能にするととも
に、窒化雰囲気中の処理によるリフローに比べても、よ
り低温で段差緩和の大きいリフI7−を実現することが
できる効果がある。
1 Advantages of the Invention 1 As explained above, the present invention provides a semiconductor device using a BPSG film as an interlayer film, in which B1+8(',
y The existence of the nitride film under the film enables the BPSG film to flow in a water vapor atmosphere, and also enables reflow at a lower temperature and with greater relief of steps than reflow in a nitriding atmosphere. This has the effect of realizing I7-.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第一の実施例を説明するための半導体
装置の断面図、第2図は本発明の第゛、の実施例を説明
する半導体装置の断面図である。 11・・・Nシリコン基板、12・・・1)型拡散層領
域、I3・・・フィールド酸化膜、14・・・ゲート酸
化膜、15・・・多結晶シリコン膜、16・・・酸化膜
、17・・・窒化膜、18・・・BPSGW;4.19
・・・コンタクト部、20・・・アルミ配線、21・・
・P型シリコン居板、22・・・N型拡散層領域、23
・・・フィールド酸1ヒ膜、24・・・ゲート酸化膜、
25・・・第1の多結晶シリコン膜、26・・・第1の
窒化膜、27・・・第1のr31) S (i膜、28
・・・第1のコンタクト部、2つ・・・第2の多結晶シ
リコン膜、30・・・酸化膜、31・・・第2の窒化膜
、32・・・第2のB P S G膜、33・・・第2
のコンタクト部、34・・・アルミ配線。 ;+it 、”11 代理人 弁理士 内 原  4. 〜、第7図
FIG. 1 is a cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention. 11... N silicon substrate, 12... 1) type diffusion layer region, I3... Field oxide film, 14... Gate oxide film, 15... Polycrystalline silicon film, 16... Oxide film , 17... Nitride film, 18... BPSGW; 4.19
...Contact part, 20...Aluminum wiring, 21...
・P-type silicon plate, 22...N-type diffusion layer region, 23
...Field acid 1 arsenic film, 24...Gate oxide film,
25... First polycrystalline silicon film, 26... First nitride film, 27... First r31) S (i film, 28
...First contact portion, two...Second polycrystalline silicon film, 30...Oxide film, 31...Second nitride film, 32...Second B P S G Membrane, 33...2nd
Contact part, 34...aluminum wiring. ;+it,”11 Agent Patent Attorney Uchihara 4. ~, Figure 7

Claims (1)

【特許請求の範囲】[Claims] 層間膜としてBPSG膜を用いる半導体装置において、
BPSG膜と、このBPSG膜により絶縁されている配
線層と、前記BPSG膜および前記配線層間で且つコン
タクト部を除く領域に一様に形成させた窒化膜とを含む
ことを特徴とする半導体装置。
In a semiconductor device using a BPSG film as an interlayer film,
A semiconductor device comprising a BPSG film, a wiring layer insulated by the BPSG film, and a nitride film uniformly formed in a region between the BPSG film and the wiring layer and excluding a contact portion.
JP130487A 1987-01-06 1987-01-06 Semiconductor device Pending JPS63169047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP130487A JPS63169047A (en) 1987-01-06 1987-01-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP130487A JPS63169047A (en) 1987-01-06 1987-01-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63169047A true JPS63169047A (en) 1988-07-13

Family

ID=11497743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP130487A Pending JPS63169047A (en) 1987-01-06 1987-01-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63169047A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474457A (en) * 1990-07-17 1992-03-09 Toshiba Corp Semiconductor device and its manufacture
JPH04196222A (en) * 1990-11-27 1992-07-16 Mitsubishi Electric Corp Semiconductor device
WO1997002594A1 (en) * 1995-07-03 1997-01-23 Intel Corporation Low damage source and drain doping technique
WO1997025738A3 (en) * 1996-01-05 1997-09-18 Univ Yale A water vapor annealing process
US5670390A (en) * 1991-12-04 1997-09-23 Mitsubishi Denki Kabushiki Kaisha Method of making semiconductor device having thin film transistor
JP2008112824A (en) * 2006-10-30 2008-05-15 Denso Corp Method for fabricating silicon carbide semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0474457A (en) * 1990-07-17 1992-03-09 Toshiba Corp Semiconductor device and its manufacture
JPH04196222A (en) * 1990-11-27 1992-07-16 Mitsubishi Electric Corp Semiconductor device
US5670390A (en) * 1991-12-04 1997-09-23 Mitsubishi Denki Kabushiki Kaisha Method of making semiconductor device having thin film transistor
WO1997002594A1 (en) * 1995-07-03 1997-01-23 Intel Corporation Low damage source and drain doping technique
US5976939A (en) * 1995-07-03 1999-11-02 Intel Corporation Low damage doping technique for self-aligned source and drain regions
WO1997025738A3 (en) * 1996-01-05 1997-09-18 Univ Yale A water vapor annealing process
US6136728A (en) * 1996-01-05 2000-10-24 Yale University Water vapor annealing process
JP2008112824A (en) * 2006-10-30 2008-05-15 Denso Corp Method for fabricating silicon carbide semiconductor device

Similar Documents

Publication Publication Date Title
US5324974A (en) Nitride capped MOSFET for integrated circuits
JPH0228902B2 (en)
JPS63169047A (en) Semiconductor device
JPH03227516A (en) Manufacture of semiconductor device
JP2679143B2 (en) Method for manufacturing semiconductor device
JPS5812340A (en) Manufacture of semiconductor device
JPS644069A (en) Manufacture of semiconductor device
JPH043419A (en) Manufacture of semiconductor device
JPH0456222A (en) Manufacture of semiconductor device
JPS62293772A (en) Semiconductor device
JP2789938B2 (en) Semiconductor device
JPH01295427A (en) Manufacture of semiconductor device
JPS6154661A (en) Manufacture of semiconductor device
JPS6134255B2 (en)
JPS62133765A (en) Manufacture of semiconductor device
JPS6222437A (en) Forming method of contact hole
JPS60195972A (en) Manufacture of semiconductor device
JPH0748495B2 (en) Method for manufacturing semiconductor device
JPH028463B2 (en)
JPS6188543A (en) Manufacture of semiconductor device
JPH05109651A (en) Semiconductor element and manufacture thereof
JPS62296473A (en) Manufacture of semiconductor device
JPS63160245A (en) Semiconductor device and manufacture thereof
JPS61170024A (en) Manufacture of semiconductor device
JPH04111318A (en) Manufacture of semiconductor device