JPH0748495B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0748495B2 JPH0748495B2 JP62184796A JP18479687A JPH0748495B2 JP H0748495 B2 JPH0748495 B2 JP H0748495B2 JP 62184796 A JP62184796 A JP 62184796A JP 18479687 A JP18479687 A JP 18479687A JP H0748495 B2 JPH0748495 B2 JP H0748495B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- titanium
- titanium silicide
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 238000000034 method Methods 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 35
- 238000009792 diffusion process Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 21
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 18
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 2
- 238000005121 nitriding Methods 0.000 claims description 2
- 239000000470 constituent Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- 239000011229 interlayer Substances 0.000 description 20
- 239000010936 titanium Substances 0.000 description 11
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 10
- 239000011521 glass Substances 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 229920005591 polysilicon Polymers 0.000 description 9
- 229910052719 titanium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 7
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に高い信頼性を有し、か
つ高い性能をもつ半導体装置の製造方法に関する。The present invention relates to a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having high reliability and high performance.
従来、チタンシリサイド膜が多結晶シリコン電極上部表
面又は多結晶シリコン配線上部表面又は拡散層表面又
は、シリコン酸化膜表面の一部に形成されている半導体
装置においては、形成されるチタンシリサイド膜はその
表面上部に形成される層間絶縁膜であるシリコン酸化膜
系の膜に直接、被覆されていた。Conventionally, in a semiconductor device in which a titanium silicide film is formed on the upper surface of the polycrystalline silicon electrode, the upper surface of the polycrystalline silicon wiring, the surface of the diffusion layer, or a part of the surface of the silicon oxide film, the formed titanium silicide film is It was directly covered with a silicon oxide film, which is an interlayer insulating film formed on the upper surface.
上述した従来技術においては、チタンシリサイド膜が化
学的気相成長法（CVD法）により形成されるシリコン酸
化膜系の絶縁膜、例えば、ボロンリンガラスに直接、被
覆されているために層間絶縁膜形成中に、または形成後
の熱処理により、チタンシリサイド膜とシリコン酸化膜
系の膜が反応して、チタンシリサイド膜の大部分は高抵
抗を有するチタンとシリコンと酸素との化合物に変化す
るという問題を有する。In the above-mentioned conventional technique, the titanium silicide film is an interlayer insulating film because it is directly coated on a silicon oxide film-based insulating film formed by a chemical vapor deposition method (CVD method), for example, boron phosphorus glass. A problem that a titanium silicide film and a silicon oxide film-based film react with each other by heat treatment during formation or after formation, and most of the titanium silicide film is changed to a compound of titanium, silicon, and oxygen having high resistance. Have.
また、チタンシリサイド膜を直接、被覆する層間絶縁膜
中のリン又はボロンが層間絶縁膜形成後の熱処理によっ
てチタンとシリコンと酸素との化合物、及びチタンシリ
サイド膜を通してポリシリ電極中又はポリシリ配線中又
は拡散層に拡散するため、拡散層特性及びコンタクト抵
抗等が変動し、半導体装置の特性が低下するという問題
も有している。Further, phosphorus or boron in the interlayer insulating film that directly covers the titanium silicide film is diffused in the polysilicon electrode or the polysilicon wiring through the compound of titanium, silicon and oxygen and the titanium silicide film by the heat treatment after the interlayer insulating film is formed. Since it diffuses into the layer, there is also a problem that the characteristics of the semiconductor device are deteriorated due to changes in the characteristics of the diffusion layer, contact resistance and the like.
上述した従来のチタンシリサイド膜を有する半導体装置
に対し、本発明はチタンシリサイド膜を窒素中又は窒素
と水素の混合ガス又はアンモニアガス中で熱処理するこ
とによって形成された窒化チタンがチタンシリサイド膜
全体を被うという独創的内容を有する。In contrast to the above-described conventional semiconductor device having a titanium silicide film, according to the present invention, titanium nitride formed by heat-treating the titanium silicide film in nitrogen, a mixed gas of nitrogen and hydrogen, or an ammonia gas covers the entire titanium silicide film. It has an original content of covering.
本発明による半導体装置はポリシリ電極上部表面又はポ
リシリ配線上部表面又は拡散層表面又はシリコン酸化膜
表面の一部にチタンシリサイド膜が形成され、さらにこ
のシリサイド膜の表面全体に窒化チタン膜が形成されて
いる構造を有している。この半導体装置を実現する本発
明の製造方法は窒化チタン膜の形成においてチタンシリ
サイド膜を窒素又は窒素と水素の混合ガス又はアンモニ
アガス中で熱処理する工程を有している。In the semiconductor device according to the present invention, the titanium silicide film is formed on a part of the upper surface of the polysilicon electrode, the upper surface of the polysilicon wiring, the surface of the diffusion layer, or the surface of the silicon oxide film, and the titanium nitride film is formed on the entire surface of the silicide film. It has a structure that The manufacturing method of the present invention for realizing this semiconductor device includes a step of heat-treating the titanium silicide film in nitrogen or a mixed gas of nitrogen and hydrogen or ammonia gas in forming the titanium nitride film.
本発明で用いる窒化チタン膜はチタンシリサイド膜を窒
素又は窒素と水素の混合ガス又は、アンモニアガス中
で、熱処理して、表面を窒化することによって、得てい
るために、緻密な膜である。また、この窒化チタン膜と
シリコン酸化膜系の膜との反応はチタンシリサイド膜と
シリコン酸化膜系の膜との反応に比べて、起こりにくい
ために、チタンシリサイドの表面にこの窒化チタン膜を
形成することにより、チタンシリサイド膜のチタンとシ
リコンと酸素との化合物への変化は起きず、さらにシリ
コン酸化膜系の膜中に含まれているリン又はボロンがチ
タンシリサイド膜の下地へ拡散することが抑制されるた
めに、拡散層特性の変動及びコンタクト抵抗の変動が起
こらない。その結果高い信頼性を有する半導体装置が得
られる。The titanium nitride film used in the present invention is a dense film because it is obtained by subjecting the titanium silicide film to heat treatment in nitrogen or a mixed gas of nitrogen and hydrogen or ammonia gas to nitride the surface. Since the reaction between the titanium nitride film and the silicon oxide film is less likely to occur than the reaction between the titanium silicide film and the silicon oxide film, the titanium nitride film is formed on the surface of the titanium silicide. As a result, the titanium silicide film does not change into a compound of titanium, silicon and oxygen, and phosphorus or boron contained in the silicon oxide film can diffuse into the underlying layer of the titanium silicide film. As a result, the diffusion layer characteristics and the contact resistance do not fluctuate. As a result, a semiconductor device having high reliability can be obtained.
また、この窒化チタン膜は100μΩ・cm〜200μΩ・cmと
いう低い比抵抗を有するために、チタンシリサイド膜の
表面に窒化チタン膜を形成しても、層抵抗の大幅な増加
はなく、この半導体装置を用いることにより、高い性能
のものが得られる。Further, since this titanium nitride film has a low specific resistance of 100 μΩ · cm to 200 μΩ · cm, even if the titanium nitride film is formed on the surface of the titanium silicide film, the layer resistance is not significantly increased. High performance can be obtained by using.
第１図は本発明の第１の実施例により製造したMOSトラ
ンジスタの縦断面図である。11はＰ型Si基板、12は素子
分離用シリコン酸化膜、13はゲート酸化膜、14は多結晶
シリコン（ゲートポリシリ電極）、15はN-拡散層、16は
サイドウォールシリコン酸化膜、17はチタンシリサイド
膜、18は窒化チタン、19はN+拡散層、20はボロンリンガ
ラスからなる層間絶縁膜、21はアルミ配線である。FIG. 1 is a vertical sectional view of a MOS transistor manufactured according to the first embodiment of the present invention. 11 is a P-type Si substrate, 12 is a device isolation silicon oxide film, 13 is a gate oxide film, 14 is polycrystalline silicon (gate polysilicon electrode), 15 is an N - diffusion layer, 16 is a sidewall silicon oxide film, and 17 is titanium. A silicide film, 18 is titanium nitride, 19 is an N + diffusion layer, 20 is an interlayer insulating film made of boron phosphorus glass, and 21 is an aluminum wiring.
このように構成された半導体装置においては、N+拡散層
15及び多結晶シリコン（ゲートポリシリ電極）、14表面
にチタンシリサイド膜17その上に窒化チタン膜18が形成
されているために、層間絶縁膜20のボロンリンガラスと
チタンシリサイド膜17とは反応せず、また、ボロンリン
ガラス層間絶縁膜20から多結晶シリコン膜14及びN+拡散
層15へボロン又はリンは拡散せず、信頼性の高いものと
なる。In the semiconductor device configured in this way, the N + diffusion layer
Since the titanium silicide film 17 is formed on the surface of 15 and polycrystalline silicon (gate polysilicon electrode), 14 and the titanium nitride film 18 is formed thereon, the boron phosphorus glass of the interlayer insulating film 20 does not react with the titanium silicide film 17. Further, boron or phosphorus is not diffused from the boron-phosphorus glass interlayer insulating film 20 to the polycrystalline silicon film 14 and the N + diffusion layer 15, which is highly reliable.
次に本発明の半導体装置第１の実施例の製造方法につい
て説明する。Next, a manufacturing method of the first embodiment of the semiconductor device of the present invention will be described.
第２図（ａ）〜（ｃ）は本発明の第１の実施例による半
導体装置の製造方法を説明するための工程図である。2A to 2C are process drawings for explaining the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
まず第２図（ａ）に示すように、選択酸化法等により素
子分離用酸化膜12がＰ型Si基板11上に形成され、素子分
離用酸化膜12以外の活性領域にゲート酸化膜13を200Å
の膜厚に形成し、その上にゲート電極として、多結晶シ
リコン膜14が4000Åの膜厚にCVD法により形成される。
この多結晶シリコン14中にリン（Ｐ）が熱拡散によりド
ープされ20Ω／口の抵抗値に設定された後、リアクティ
ブイオンエッチング法等の方法によりパターニングされ
てゲート電極が形成される。次に、多結晶シリコン14を
マスクとする自己整合法により、ＰイオンをＰ型Si基板
11に注入し、900℃の熱処理を加えてN-拡散層が形成さ
れる。この後、CVD法によりシリコン酸化膜が2000Åの
膜厚に形成され、リアクティブイオンエッチング法等の
方法によりエッチバックが行なわれ、サイドウォールシ
リコン酸化膜16が形成される。次に第２図（ｂ）に示す
ように、チタン（Ti）膜がスパッタ法等により素子分離
用シリコン酸化膜14表面、N-拡散層15表面サイドウォー
ルシリコン酸化膜16表面、多結晶シリコン14表面を被覆
するように形成された後、電気炉又はランプアニール装
置を用いて、窒素雰囲気中で600℃の温度でアニールを
行ない、アンモニア水と過酸化水素水の混合液により処
理されて、N-拡散層15、及び多結晶シリコン14表面上に
のみチタンシリサイド膜17が形成される。First, as shown in FIG. 2A, an element isolation oxide film 12 is formed on a P-type Si substrate 11 by a selective oxidation method or the like, and a gate oxide film 13 is formed in an active region other than the element isolation oxide film 12. 200Å
And a polycrystalline silicon film 14 is formed thereon as a gate electrode to a thickness of 4000 Å by the CVD method.
Phosphorus (P) is doped into the polycrystalline silicon 14 by thermal diffusion to set a resistance value of 20 Ω / port, and then patterned by a method such as a reactive ion etching method to form a gate electrode. Next, P ions are added to the P-type Si substrate by the self-alignment method using the polycrystalline silicon 14 as a mask.
Then, the N - diffusion layer is formed by injecting into 11 and heat treatment at 900 ° C. After that, a silicon oxide film is formed to a thickness of 2000 Å by the CVD method, and etching back is performed by a method such as the reactive ion etching method to form the sidewall silicon oxide film 16. Next, as shown in FIG. 2B, a titanium (Ti) film is formed by sputtering or the like on the surface of the element isolation silicon oxide film 14, the surface of the N − diffusion layer 15 and the surface of the side wall silicon oxide film 16, and the polycrystalline silicon 14 After being formed so as to cover the surface, it is annealed at a temperature of 600 ° C. in a nitrogen atmosphere using an electric furnace or a lamp annealing device, and treated with a mixed solution of ammonia water and hydrogen peroxide water. - titanium silicide film 17 only on the diffusion layer 15, and the polycrystalline silicon 14 on the surface is formed.
次に第２図（ｃ）に示すように電気炉又はランプアニー
ル装置を用いて窒素中又は窒素と水素の混合ガス中又は
アンモニアガス中で850℃から950℃の温度でアニールす
ることにより、チタンシリサイド膜17を窒化し、膜表面
に窒化チタン膜18が形成される。次に、ボロンリンガラ
スからなる層間絶縁膜20が堆積され、その後、リアクテ
ィブエッチング法により層間絶縁膜20にコンタクトホー
ルがあけられる。その後、スパッタ法によりアルミを堆
積し、パターニングを行ない、アルミ配線21が形成され
て第１図に示す半導体装置が得られる。Next, as shown in FIG. 2 (c), titanium is annealed in a nitrogen gas, a mixed gas of nitrogen and hydrogen, or an ammonia gas at a temperature of 850 ° C. to 950 ° C. by using an electric furnace or a lamp annealing device. The silicide film 17 is nitrided, and the titanium nitride film 18 is formed on the film surface. Next, an interlayer insulating film 20 made of boron phosphorus glass is deposited, and then a contact hole is formed in the interlayer insulating film 20 by the reactive etching method. After that, aluminum is deposited by a sputtering method, and patterning is performed to form an aluminum wiring 21 to obtain the semiconductor device shown in FIG.
第３図は本発明の第２の実施例により製造したTiシリサ
イド配線が用いられた半導体装置の縦断面図である。10
1はＰ型Si基板、102は素子分離用シリコン酸化膜、103
はＮウエル、104はゲート酸化膜、105は多結晶シリコン
（ゲートポリシリ電極）、106はP+拡散層、107はN+拡散
層、108はシリコン酸化膜からなる層間絶縁膜、109はチ
タンシリサイド膜、110は窒化チタン膜、111はボロンリ
ンガラスからなる層間絶縁膜、112はアルミ配線であ
る。FIG. 3 is a longitudinal sectional view of a semiconductor device using Ti silicide wiring manufactured according to the second embodiment of the present invention. Ten
1 is a P-type Si substrate, 102 is a silicon oxide film for element isolation, 103
Is an N well, 104 is a gate oxide film, 105 is polycrystal silicon (gate polysilicon electrode), 106 is a P + diffusion layer, 107 is an N + diffusion layer, 108 is an interlayer insulating film made of a silicon oxide film, and 109 is a titanium silicide film. , 110 is a titanium nitride film, 111 is an interlayer insulating film made of boron phosphorus glass, and 112 is an aluminum wiring.
このように、構成された、半導体装置においては、チタ
ンシリサイド膜109上に窒化チタン膜110が形成されてい
るために、ボロンリンガラスからなる、層間絶縁膜111
からN+拡散層107、P+拡散層106へボロン又はリンは拡散
しない。したがって、この半導体装置の特性は変動せ
ず、信頼性の高いものとなる。In the semiconductor device thus configured, since the titanium nitride film 110 is formed on the titanium silicide film 109, the interlayer insulating film 111 made of boron phosphorus glass is formed.
Does not diffuse into the N + diffusion layer 107 and the P + diffusion layer 106 from boron or phosphorus. Therefore, the characteristics of this semiconductor device do not change, and the reliability is high.
次に本発明の半導体装置第２の実施例の製造方法につい
て説明する。Next, a manufacturing method of the second embodiment of the semiconductor device of the present invention will be described.
第４図（ａ）〜（ｃ）は本発明の第２の実施例による半
導体装置の製造方法を説明するための工程図である。FIGS. 4A to 4C are process drawings for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
まず、第４図（ａ）に示すように、選択酸化法等により
素子分離用酸化膜102がＰ型Si基板101上に形成され、素
子分離用酸化膜102以外の活性領域にＮウエル103が形成
された後、ゲート酸化膜104を200Åの膜厚に形成し、そ
の上にゲート電極として、多結晶シリコン105が4000Å
の膜厚にCVD法により形成される。この多結晶シリコン1
05中にリン（Ｐ）が熱拡散によりドープされ20Ω／口の
抵抗値に設定された後、リアクティブイオンエッチング
法等の方法によりパターニングされて、ゲート電極が形
成される。次に、P+拡散層に対してはボロン（Ｂ）、N+
拡散層に対してはヒ素（As）がイオン注入された後、90
0℃の熱処理が加えられてP+拡散層106、N+拡散層107が
形成される。この後、シリコン酸化膜からなる層間絶縁
膜108がCVD法により堆積され、コンタクトホールが形成
される。次に、第４図（ｂ）に示すように、チタン（T
i）シリサイドがスパッタ法等の方法により2000Åの膜
厚に形成された後、リアクティブイオンエッチング法等
の方法により、チタンシリサイド膜109が形成される。First, as shown in FIG. 4A, an element isolation oxide film 102 is formed on a P-type Si substrate 101 by a selective oxidation method or the like, and an N well 103 is formed in an active region other than the element isolation oxide film 102. After the formation, a gate oxide film 104 is formed to a film thickness of 200Å, and polycrystalline silicon 105 is formed on the film as a gate electrode on the surface of 4000Å
Is formed by the CVD method. This polycrystalline silicon 1
Phosphorus (P) is doped by thermal diffusion in 05 to set a resistance value of 20 Ω / port, and then patterned by a method such as a reactive ion etching method to form a gate electrode. Next, for the P + diffusion layer, boron (B), N +
After arsenic (As) is ion-implanted into the diffusion layer, 90
Heat treatment at 0 ° C. is applied to form the P + diffusion layer 106 and the N + diffusion layer 107. After that, an interlayer insulating film 108 made of a silicon oxide film is deposited by the CVD method to form a contact hole. Next, as shown in FIG. 4 (b), titanium (T
i) Titanium silicide film 109 is formed by a method such as reactive ion etching after silicide is formed to a thickness of 2000 Å by a method such as sputtering.
次に電気炉又はランプアニール装置を用いて、窒素中、
又は窒素と水素の混合ガス中又はアンモニアガス中で85
0℃から950℃の温度でチタンシリサイド膜109をアニー
ルすることにより膜表面に窒化チタン膜110が形成され
る。Next, using an electric furnace or a lamp annealing device, in nitrogen,
Or in a mixed gas of nitrogen and hydrogen or in ammonia gas 85
By annealing the titanium silicide film 109 at a temperature of 0 ° C. to 950 ° C., the titanium nitride film 110 is formed on the film surface.
次に第４図（ｃ）に示すように、ボロンリンガラスから
なる層間絶縁膜111がCVD法により堆積され、この層間絶
縁膜にコンタクトホール（図示せず）が形成される。こ
の後、スパッタ法によりアルミを堆積し、パターニング
を行ない、アルミ配線112が形成されて、第３図に示す
半導体装置が得られる。Next, as shown in FIG. 4C, an interlayer insulating film 111 made of boron phosphorus glass is deposited by the CVD method, and a contact hole (not shown) is formed in this interlayer insulating film. After that, aluminum is deposited by a sputtering method, and patterning is performed to form aluminum wiring 112, and the semiconductor device shown in FIG. 3 is obtained.
以上説明したように本発明は、ゲートポリシリ電極又は
ポリシリ配線又は拡散層表面又はシリコン酸化膜表面の
一部に形成されているチタンシリサイド膜表面にチタン
シリサイド膜の窒化反応により形成された窒化チタンが
形成されていることにより、このチタンシリサイド膜を
被覆するボロンリンガラスからなる層間絶縁膜をCVD法
により形成する時においても、チタンシリサイド膜は酸
化して、チタンとシリコンと酸素との化合物に変質せ
ず、また、層間絶縁膜中に含まれているボロン（Ｂ）、
リン（Ｐ）等の不純物がチタンシリサイド膜中に拡散し
て、下地のコンタクト、及び拡散層の特性を変えること
はない、すなわち、高い信頼性を有し、かつ、高い性能
をもつ半導体装置が製造できる効果がある。また、本発
明の製造方法は窒化チタン膜を作製する工程が簡単で、
かつ、質の良い膜が作れる特長がある。As described above, according to the present invention, the titanium nitride film formed by the nitriding reaction of the titanium silicide film is formed on the titanium silicide film surface formed on a part of the gate polysilicon electrode, the polysilicon wire, the diffusion layer surface or the silicon oxide film surface. Therefore, even when the interlayer insulating film made of boron phosphorus glass covering the titanium silicide film is formed by the CVD method, the titanium silicide film is oxidized and transformed into a compound of titanium, silicon and oxygen. In addition, boron (B) contained in the interlayer insulating film,
Impurities such as phosphorus (P) do not diffuse into the titanium silicide film to change the characteristics of the underlying contact and diffusion layer, that is, a semiconductor device having high reliability and high performance is provided. There is an effect that can be manufactured. In addition, the manufacturing method of the present invention is simple in the step of forming a titanium nitride film,
In addition, it has the feature that high quality films can be made.
第１図は本発明の第１の実施例による半導体装置の断面
図、第２図（ａ）〜（ｃ）は本発明の第１の実施例によ
る半導体装置の製造方法を説明するための工程図、第３
図は本発明の第２の実施例による半導体装置の断面図、
第４図（ａ）〜（ｃ）は本発明の第２の実施例による半
導体装置の製造方法を説明するための工程図である。 11…Ｐ型Si基板、12…素子分離用シリコン酸化膜、13…
ゲート酸化膜、14…多結晶シリコン、15…N-拡散層、16
…サイドウォールシリコン酸化膜、17…チタンシリサイ
ド膜、18…窒化チタン、19…N+拡散層、20…層間絶縁
膜、21…アルミ配線、101…Ｐ型Si基板、102…素子分離
用シリコン酸化膜、103…Ｎウエル、104…ゲート酸化
膜、105…多結晶シリコン、106…P+拡散層、107…N+拡
散層、108…シリコン酸化膜からなる層間絶縁膜、109…
チタンシリサイド膜、110…チタン、111…ボロンリンガ
ラスからなる層間絶縁膜、112…アルミ配線。FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, and FIGS. 2A to 2C are steps for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. Figure, third
FIG. 1 is a sectional view of a semiconductor device according to a second embodiment of the present invention,
FIGS. 4A to 4C are process drawings for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 11 ... P-type Si substrate, 12 ... Silicon oxide film for element isolation, 13 ...
Gate oxide film, 14 ... Polycrystalline silicon, 15 ... N - diffusion layer, 16
... Sidewall silicon oxide film, 17 ... Titanium silicide film, 18 ... Titanium nitride, 19 ... N + diffusion layer, 20 ... Interlayer insulating film, 21 ... Aluminum wiring, 101 ... P-type Si substrate, 102 ... Silicon oxide for element isolation Membrane, 103 ... N well, 104 ... Gate oxide film, 105 ... Polycrystalline silicon, 106 ... P + diffusion layer, 107 ... N + diffusion layer, 108 ... Interlayer insulating film made of silicon oxide film, 109 ...
Titanium silicide film, 110 ... Titanium, 111 ... Boron phosphorus glass interlayer insulating film, 112 ... Aluminum wiring.
Claims (1)
晶シリコン層表面上に、チタンシリサイド膜を形成する
工程と、窒素元素を構成元素の１つとして含んでいる雰
囲気中で前記チタンシリサイド膜を熱処理して窒化反応
を有機せしめて前記チタンシリサイド膜表面に窒化チタ
ン膜を形成する工程とを少なくとも備えていることを特
徴とする半導体装置の製造方法。1. A step of forming a titanium silicide film on at least a surface of an impurity diffusion layer or a surface of a polycrystalline silicon layer, and a heat treatment of the titanium silicide film in an atmosphere containing a nitrogen element as one of constituent elements. And then forming a titanium nitride film on the surface of the titanium silicide film by organically effecting the nitriding reaction, the method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62184796A JPH0748495B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62184796A JPH0748495B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6428842A JPS6428842A (en) | 1989-01-31 |
| JPH0748495B2 true JPH0748495B2 (en) | 1995-05-24 |
Family
ID=16159442
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62184796A Expired - Lifetime JPH0748495B2 (en) | 1987-07-23 | 1987-07-23 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0748495B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100365749B1 (en) * | 1995-12-29 | 2003-03-03 | 주식회사 하이닉스반도체 | A method for fabrication of semiconductor device |
| KR100238219B1 (en) * | 1996-12-13 | 2000-01-15 | 윤종용 | Gate pattern in silicon processing |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61137367A (en) * | 1984-12-10 | 1986-06-25 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
| JPS6261345A (en) * | 1985-09-11 | 1987-03-18 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0716000B2 (en) * | 1985-10-25 | 1995-02-22 | 株式会社日立製作所 | Method for manufacturing semiconductor integrated circuit device |
| JPS6312152A (en) * | 1986-07-02 | 1988-01-19 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPS6263448A (en) * | 1986-09-29 | 1987-03-20 | Hitachi Ltd | Wiring structure in semiconductor element |
-
1987
- 1987-07-23 JP JP62184796A patent/JPH0748495B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6428842A (en) | 1989-01-31 |
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