JPH05190855A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to improve electrical characteristics, such as carrier mobility of a thin-film transistor by hydrogenating the activated layer of the thin-film transistor without applying stress to the activated layer. CONSTITUTION:In a thin-film transistor 42 which is provided via gate insulating film 46 with a gate 47 on an activated layer 43 formed in a polycrystalline silicon region 41, sidewall insulating films 48, 49 composed of silicon nitride film are formed in the sidewall of the gate 47 and the activated layer 43 is hydrogenated by the sidewall insulating films 48, 49. Or the gate insulating film 46 is formed of silicon nitride film and the activated layer 43 is hydrogenated by the sidewall insulating films 48, 49 and gate insulating film 46. Or the sidewall insulating films 48, 49 are formed of silicon oxide film and silicon nitride film and the activated layer 43 is hydrogenated by the sidewall insulating films 48, 49.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art A thin film transistor having an active layer provided in a polycrystalline silicon region is an important technique for constructing a three-dimensional integrated circuit. Especially in SRAM, complete CMO
By forming the high resistance portion with a thin film transistor in order to realize S, it is possible to reduce the size of the memory cell.

The structure of the SRAM will be described with reference to the schematic sectional view of FIG. As shown in the figure, an element isolation region 72 is formed in the upper layer of the semiconductor substrate 71. An SRAM driver transistor 73 is formed on a part of the semiconductor substrate 71 separated into the element isolation regions 72. First to cover the driver transistor 73
The insulating film 74 is formed. A contact hole 76 is provided in the first insulating film 74 on the source / drain region 75 of the driver transistor 73.

Further, a polycrystalline silicon region 77 connected to the source / drain region 75 via the contact hole 76 is formed on the first insulating film 74. A thin film transistor 78 is formed in the polycrystalline silicon region 77. That is, the active layer 79 of the thin film transistor 78 is formed in the polycrystalline silicon region 77, and the polycrystalline silicon region 7 on both sides of the active layer 79 is formed.
7, the source / drain region 8 of the thin film transistor 78
0, 81 are formed. Furthermore, the thin film transistor 7
A second insulating film (interlayer insulating film) 82 is formed so as to cover the insulating film 8. A contact hole 83 is provided in the second insulating film 82 on the source / drain region 81. A wiring 84 of the first layer, which is connected to the source / drain region 81 through the contact hole 83, is formed on the second insulating film 82. The SRAM 70 is configured as described above.

FIG. 9 shows a method of manufacturing the SRAM 70 having the above structure.
Will be briefly described with reference to FIG. As shown in FIG. 9A, the element isolation region 72 is formed in the upper layer of the semiconductor substrate (for example, a single crystal silicon substrate) 71 by, for example, the LOCOS oxidation method. Then, a silicon oxide film (85) is formed by a thermal oxidation method, and then a polycrystalline silicon film (86) is formed by a chemical vapor deposition method. Subsequently, the gate 87 of the driver transistor is formed of the polycrystalline silicon film (86) by photolithography and etching. Further, the gate insulating film 88 of the driver transistor is formed of the silicon oxide film (85). Next, low concentration diffusion layers 89 and 90 are formed on the semiconductor substrate 71 on both sides of the gate 87 by ion implantation.

After that, as shown in FIG. 9B, a silicon oxide film (not shown) is formed by a chemical vapor deposition method, and the silicon oxide film is etched back to oxidize the side wall of the gate 87. A gate sidewall insulating film 91 of a silicon film is formed. Then, using the gate sidewall insulating film 91 and the gate 87 as ion implantation masks, the high concentration diffusion layers 92 and 93 are formed in a state deeper than the low concentration diffusion layers 89 and 90. Thus, the low-concentration diffusion layer 89 and the high-concentration diffusion layer 92 form the source / drain regions 94 of the driver transistor. Further, the low-concentration diffusion layer 90 and the high-concentration diffusion layer 93 form a source / drain region 75. The driver transistor 73 is formed as described above.

Subsequently, as shown in FIG. 9C, a first insulating film 74 made of a silicon oxide film is formed by chemical vapor deposition so as to cover the driver transistor 73.
To form. After that, a contact hole 76 is formed in the first insulating film 74 on the source / drain region 75 by photolithography and etching. Further, a polycrystalline silicon film (95) is formed on the inside of the contact hole 76 and on the upper surface of the first insulating film 74 by a chemical vapor deposition method, and then the polycrystalline silicon film (95) is formed by photolithography and etching. A polycrystalline silicon region 77 is formed from the crystalline silicon film (95).

Then, as shown in (4) of FIG. 10, a silicon oxide film (96) and a polycrystalline silicon film (9) are formed on the upper surface of the polycrystalline silicon region 77 by a chemical vapor deposition method.
7) and are formed into a film. Then, by photolithography and etching, the gate 98 of the thin film transistor is formed of the polycrystalline silicon film (97) and the gate insulating film 99 of the thin film transistor is formed of the silicon oxide film (96).

Then, as shown in FIG. 10 (5), the gate 98 and the first insulating film 74 are used as ion implantation masks to form the source / drain regions 80, in the polycrystalline silicon regions 77 on both sides of the gate 98. 81 is formed. In this way, the thin film transistor 78 is formed. After that, a second insulating film (interlayer insulating film) 82 made of a silicon oxide film is formed by chemical vapor deposition so as to cover the thin film transistor 78. Subsequently, the source / drain regions 8 are formed by photolithography and etching.
A contact hole 83 leading to 1 is formed.

Subsequently, as shown in FIG. 10 (6), after forming a wiring layer (100) by a sputtering method, the wiring layer (10) is formed by photolithography and etching.
In 0), the wiring 84 of the first layer is formed. The wiring layer (10
0) consists of, for example, a titanium oxynitride film, a titanium film, and an aluminum film containing 1% of silicon.

[0011]

However, in the polycrystalline silicon region forming the active layer of the above-mentioned thin film transistor, there are a large number of dumbling bonds of silicon at grain boundaries or in crystals. For this reason, the carrier mobility is significantly reduced, and thus the electrical characteristics of the thin film transistor are low.

Therefore, as a method for increasing the carrier mobility, hydrogenation treatment is performed in which hydrogen is introduced into the polycrystalline silicon region to fill the crystal grain boundaries in the polycrystalline silicon with monovalent hydrogen. The normal hydrogenation process uses a plasma silicon nitride film as passivation,
A method is employed in which hydrogen in the plasma silicon nitride film is diffused through the interlayer insulating film into the active layer in the polycrystalline silicon region by heat treatment. Another method that has been experimentally tried is to excite hydrogen plasma to hydrogenate the active layer. There is also a method of implanting hydrogen ions.

However, in the method of diffusing hydrogen from the plasma silicon nitride film to hydrogenate the active layer, the internal stress of the plasma silicon nitride film is large, and the stress is largely changed by the heat treatment during diffusion. Therefore, the stress of the plasma silicon nitride film used as the passivation (about 116 GPa) is applied to the silicon crystal in the polycrystalline silicon region, so that a crystal defect occurs in the silicon crystal. As a result, even if the active layer is hydrogenated, the performance of the thin film transistor is significantly deteriorated due to crystal defects generated in the active layer.

An object of the present invention is to provide a thin film transistor excellent in electrical characteristics, particularly carrier mobility characteristics, and a method for manufacturing the same.

[0015]

SUMMARY OF THE INVENTION The present invention is a thin film transistor and a method for manufacturing the thin film transistor, which are made to achieve the above object. That is, a polycrystalline silicon region was formed on a substrate, an active layer was provided in the polycrystalline silicon region, source / drain regions were provided on both sides of the active layer, and a gate was provided on the active layer via a gate insulating film. A thin film transistor obtained by hydrogenating the active layer,
A sidewall insulating film made of a silicon nitride film is formed on the side wall of the gate, and the active layer is hydrogenated with the sidewall insulating film. Alternatively, a sidewall insulating film formed of a silicon nitride film is provided on the sidewall of the gate of the thin film transistor, the gate insulating film of the thin film transistor is formed of a silicon nitride film, and the sidewall insulating film and the gate insulating film form the thin film transistor of the thin film transistor. The active layer is hydrotreated. Alternatively, a sidewall insulating film including a silicon oxide film and a silicon nitride film is provided on a sidewall of a gate of the thin film transistor, and the active layer of the thin film transistor is hydrogenated by the sidewall insulating film.

As a method of manufacturing a thin film transistor, a polycrystalline silicon region is formed on a substrate, a gate is formed on the polycrystalline silicon region of the thin film transistor through a gate insulating film, and then at least a part of the periphery of the gate is formed. A silicon nitride film is formed, and then hydrogen contained in the silicon nitride film is released to hydrogenate the active layer formed in the polycrystalline silicon region.

[0017]

In the thin film transistor having the above structure, the stress generated in the silicon nitride film is prevented from being applied to the thin film transistor by forming all or part of the sidewall insulating film formed on the side wall of the gate of the thin film transistor with the silicon nitride film. Reduce. Therefore, crystal defects do not occur in the active layer of the thin film transistor. Furthermore, since the silicon nitride film is provided on the silicon oxide film, the silicon oxide film alleviates the stress generated in the silicon nitride film. Further, in the above manufacturing method, after forming a gate on the polycrystalline silicon region via the gate insulating film of the thin film transistor, at least a silicon nitride film is formed on a part of the periphery of the gate, thereby forming an active layer of the thin film transistor. Almost no stress generated by the silicon nitride film is applied to the crystalline silicon region.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, the SRAM 10 in which the high resistance portion is formed of a thin film transistor is shown. As shown in the figure,
An element isolation region 12 is formed in an upper layer of a substrate (for example, a semiconductor substrate) 11 (hereinafter referred to as the semiconductor substrate 11). The semiconductor substrate 11 is formed of, for example, a single crystal silicon substrate. A driver transistor 21 of SRAM is formed on the semiconductor substrate 11 divided into the element isolation regions 12. The driver transistor 21
The first insulating film 13 is formed so as to cover the. In addition, the contact hole 1 is formed in the first insulating film 13 on the source / drain region 22 of the driver transistor 21.
4 are provided.

Further, a polycrystalline silicon region 41 connected to the source / drain region 22 through the contact hole 14 is formed on the first insulating film 13. A thin film transistor 42 is formed in the polycrystalline silicon region 41. That is, the active layer 43 of the thin film transistor 42 is formed in the polycrystalline silicon region 41. Source / drain regions 44 and 45 of the thin film transistor 42 are formed in the polycrystalline silicon region 41 on both sides of the active layer 43. Further, a gate 47 of the thin film transistor 42 is formed on the active layer 43 via a gate insulating film 46. The gate insulating film 46 is made of, for example, a silicon oxide film. Sidewall insulating films 48 and 49 are formed on both side walls of the gate 47. Each sidewall insulating film 48, 49
Are formed of a silicon nitride film. This silicon nitride film is formed of, for example, a plasma silicon nitride film (P-SiN) formed by a plasma chemical vapor deposition method.

Further, low resistance layers 50, 51 and 52 are formed on the upper layer of the gate 47 and the polycrystalline silicon region 41. Each of the low resistance layers 50 to 52 is made of, for example, titanium silicide (TiSi ₂ ). The low resistance layers 50 to 52 do not necessarily have to be formed. Further, hydrogen contained in the silicon nitride film is diffused in the active layer 43 to enhance the carrier mobility of the active layer 43. As described above, the thin film transistor 42
Is configured.

Further, a second insulating film (interlayer insulating film) 15 is formed so as to cover the thin film transistor 42. Source / drain regions 45 of the thin film transistor
A contact hole 16 is provided in the upper second insulating film 15. And through the contact hole 16,
A first-layer wiring 17 connected to the low resistance layer 52 on the source / drain region 45 of the thin film transistor is formed. The first-layer wiring 17 is formed of, for example, a barrier metal layer 18 and an aluminum layer 19 containing 1% of silicon.

As described above, the sidewall insulating film 4
By forming the silicon nitride films 8 and 49, the active layer 43 is hydrogenated without stressing the polycrystalline silicon region 41 in which the source / drain regions 44 and 45 are formed.

Next, the SRAM described in the first embodiment
The manufacturing method of 10 is a manufacturing process drawing of FIG.
(Part 3) will be described. As shown in (1) of FIG. 2, an element isolation region 12 is formed in an upper layer of a semiconductor substrate (for example, a single crystal silicon substrate) 11 by, for example, a normal LOCOS oxidation method. Then, a silicon oxide film 23 is formed on the exposed surface layer of the semiconductor substrate 11 by a normal thermal oxidation method to have a thickness of 16 nm, for example. As an oxidizing condition at this time, for example, the temperature is kept in a hydrogen peroxide (H ₂ O ₂ ) atmosphere of 850 ° C.

After that, the polycrystalline silicon film 2 is formed on the entire surface on the silicon oxide film 23 side by, for example, a chemical vapor deposition method.
4 is deposited to a thickness of 200 nm, for example. The film forming conditions at this time are, for example, a reaction gas flow rate of 500 s.
ccm silane (SiH ₄ ) and flow rate is 0.35 sccm
Of phosphine (PH ₃ ) and hydrogen (H ₂ ) having a flow rate of 50 sccm are used, the film forming temperature is set to 580 ° C., and the pressure of the film forming atmosphere is set to 79.8 Pa.

Further, for example, by chemical vapor deposition,
A tungsten silicide (WSi ₂ ) film 25 is formed on the upper surface of the polycrystalline silicon film 24 to a thickness of 100 nm, for example. The film forming conditions at this time are, for example, a reaction gas containing tungsten hexafluoride (W with a flow rate of 10 sccm).
F ₆ ) and silane (SiH ₄ ) with a flow rate of 1000 sccm
And a flow rate of 360 sccm of helium (He) are used as a mixed gas, and the film forming temperature is set to 360 ° C. and the pressure of the film forming atmosphere is set to 26.6 Pa.

Then, the portion shown by the broken line of the tungsten silicide film 25 and the portion shown by the chain double-dashed line of the polycrystalline silicon film 24 are removed by usual photolithography and etching, and the gate 26 of the driver transistor 21 is formed. Form. The etching conditions include, for example, boron trichloride (BCl ₃ ) having a flow rate of 60 sccm and chlorine (Cl) having a flow rate of 90 sccm in the etching gas.
₂ ) with a mixed gas consisting of
kW and high frequency power are set to 50W.

Then, using the gate 26 as an ion implantation mask, the low-concentration diffusion layers 27 and 28 are formed on the semiconductor substrate 11 on both sides of the gate 26. As the ion implantation conditions, when an NMOS transistor is formed, for example, phosphorus (P ⁺ ) is used as an ion implantation impurity, the implantation energy is 20 keV, and the dose amount is 2 × 10 ¹³ /
Set to cm ² . When forming a PMOS transistor, boron fluoride (BF ⁺ ) is used as the ion-implanted impurity, and the implantation energy is 30 keV.
The dose amount is set to 3 × 10 ¹³ pieces / cm ² .

Then, as shown in FIG. 2B, a silicon oxide film 29 is formed to a thickness of 250 nm, for example, on the entire surface on the gate 26 side by a normal chemical vapor deposition method.
The film forming conditions at this time are silane (SiH ₄ ) with a flow rate of 250 sccm and oxygen (O ₂ ) with a flow rate of 250 sccm.
₂₎ the flow rate with more becomes mixed gas 100sccm of nitrogen (N _2), a deposition temperature, for example 420 ° C., to set the pressure of the deposition atmosphere to 13.3 Pa.

Then, by a normal etch back process,
The portion indicated by the chain double-dashed line of the silicon oxide film 29 is removed. Then, the gate sidewall insulating films 30 and 31 made of the silicon oxide film 29 are formed on the sidewalls of the gate 26. As the etch back conditions at this time, for example, octafluorocyclobutane (C ₄ F ₈ ) having a flow rate of 50 sccm is used as the etching gas, and the high frequency power is 1.2.
kW and the pressure of the etching atmosphere are set to 2 Pa.

Next, the gate sidewall insulating film 30,
An impurity is introduced into the upper layer of the semiconductor substrate 11 by a normal ion implantation method using the gate 31 and the gate 26 as an ion implantation mask, and the high concentration diffusion layers 32 and 33 are deeper than the low concentration diffusion layers 27 and 28. To form. The low-concentration diffusion layer 27 and the high-concentration diffusion layer 32 cause the source
The drain region 34 is formed. The source / drain regions 22 are formed by the low concentration diffusion layer 28 and the high concentration diffusion layer 33. As the implantation conditions of this ion implantation method, for example, when an NMOS transistor is formed,
Arsenic (As ⁺ ) is used as the ion-implanted impurity, the implantation energy is 50 keV, and the dose is 3 × 10 ^15.
Set to pieces / cm ² . When forming a PMOS transistor, boron fluoride (BF ⁺ ) is used as the ion implantation impurity, and the implantation energy is 20 ke.
V and dose amount are set to 2 × 10 ¹⁵ pieces / cm ² . The driver transistor 21 is formed as described above.

Then, as shown in FIG. 2C, the first insulating film 13 is formed in a state of covering the driver transistor 21 by, for example, a normal chemical vapor deposition method, for example, 50.
A film is formed to a thickness of 0 nm. The film forming conditions at this time are, for example, silane (SiH ₄ ) having a flow rate of 250 sccm and a flow rate of 25 as in the case described in (3) of FIG.
Using a mixed gas of 0 sccm of oxygen (O ₂ ) and a flow rate of 100 sccm of nitrogen (N ₂ ), the film forming temperature is set to 420 ° C. and the pressure of the film forming atmosphere is set to 13.3 Pa.

After that, a contact hole 14 is formed in the first insulating film 13 on the source / drain region 22 by usual photolithography and etching. The etching conditions at this time are, for example, 50 sccc of etching gas, as described in (3) of FIG. 2 above.
Octafluorocyclobutane (C ₄ F ₈ ) having a flow rate of m is used to set the high frequency power to 1.2 kW and the etching atmosphere pressure to 2 Pa.

Then, as shown in FIG. 2 (4), the contact hole 14 is formed by an ordinary chemical vapor deposition method.
A polycrystalline silicon film 53 is formed to a thickness of, for example, 200 nm inside the substrate and on the upper surface of the first insulating film 13. The film forming conditions at this time are, for example, (1) in FIG.
As described above, the reaction gas has a flow rate of 500 sccc.
m of silane (SiH ₄ ), a flow rate of 0.35 sccm of phosphine (PH ₃ ) and a flow rate of 50 sccm of hydrogen (H ₂ ), a film forming temperature is set to, for example, 580 ° C., and a pressure of a film forming atmosphere is used. Is set to 79.8 Pa.

Then, the portion indicated by the chain double-dashed line of the polycrystalline silicon film 53 is removed by ordinary photolithography and etching to form a polycrystalline silicon region 41. The etching conditions at this time are, for example, that the etching gas is boron trichloride (B
Cl ₃ ), hydrogen chloride (HCl) having a flow rate of 20 sccm, and chlorine (Cl ₂ ) having a flow rate of 10 sccm are used, and the pressure of the etching atmosphere is set to 7.98 Pa and the etching power is set to 1.5 kW.

Then, as shown in FIG. 3 (5), a silicon oxide film 54 is formed on the surface of the polycrystalline silicon region 41 by, eg, thermal oxidation to have a thickness of 16 nm, for example. As the thermal oxidation conditions at this time, for example, the oxidizing atmosphere is a mixed gas of hydrogen (H ₂ ) having a flow rate of 6 sccm and oxygen (O ₂ ) having a flow rate of 6 sccm,
The temperature atmosphere is set to 850 ° C.

Subsequently, a polycrystalline silicon film 55 is formed on the surface of the silicon oxide film 54 to a thickness of, for example, 200 nm by a normal chemical vapor deposition method. As the film forming conditions at this time, for example, as described in (1) of FIG. 2 above, silane (SiH ₄ ) having a flow rate of 500 sccm and phosphine (PH ₃ ) having a flow rate of 0.35 sccm are used as the reaction gas. And a flow rate of 50 sccm of hydrogen (H ₂ ) are used as a mixed gas, and the film formation temperature is set to 580 ° C. and the pressure of the film formation atmosphere is set to 79.8 Pa.

After that, the portion indicated by the chain double-dashed line of the polycrystalline silicon film 55 is removed by usual photolithography and etching, and the gate 4 of the thin film transistor is formed.
Form 7. Further, etching is performed to remove the portion indicated by the one-dot chain line of the silicon oxide film 54, and the gate insulating film 46 is formed from the silicon oxide film 54. The etching conditions of the polycrystalline silicon film 55 at this time are, for example, boron trichloride (BCl ₃ ) with a flow rate of 50 sccm, hydrogen chloride (HCl) with a flow rate of 20 sccm, and chlorine (Cl ₂ with a flow rate of 10 sccm) as etching gas. ) And a pressure of the etching atmosphere of 7.
98 Pa and etching power are set to 1.5 kW.
The etching conditions for the silicon oxide film 54 are, for example, an etching gas of trifluoromethane (CHF ₃ ) with a flow rate of 75 sccm and a flow rate of 25 sccm.
Using a mixed gas of oxygen and oxygen, the etching atmosphere pressure is set to 5.32 Pa and the etching power is set to 800 W.

Then, the source / drain regions 44 and 45 are formed in the polycrystalline silicon region 41 on both sides of the gate 47 by the ordinary ion implantation method using the gate 47 and the first insulating film 13 as an ion implantation mask. To do. As the ion implantation conditions at this time, for example, in the case of a thin film transistor of an NMOS transistor, for example, arsenic (As ⁺ ) is used as an ion implantation impurity, the implantation energy is 50 keV, and the dose amount is 3 × 10 ¹⁵ / cm ² . Set. Alternatively, when forming a PMOS transistor, for example, boron fluoride (B
F ⁺ ) is used to set the implantation energy to 20 keV and the dose amount to 2 × 10 ¹⁵ pieces / cm ² .

Thereafter, as shown in FIG. 3 (6), a silicon nitride (P-) is formed so as to cover the entire surface of the gate 47 side by a chemical vapor deposition method (P-CVD method) using ordinary plasma. The SiN) film 56 has a thickness of, for example, 300 nm.
To form a film. The film forming conditions at this time are, for example, silane (SiH ₄ ) with a reaction gas flow rate of 180 sccm.
And a mixed gas of ammonia (NH ₃ ) having a flow rate of 500 sccm and nitrogen (N ₂ ) having a flow rate of 720 sccm, the film forming temperature is 200 ° C., and the pressure of the film forming atmosphere is 39.
Set to 9 Pa.

Then, by a normal etch back process,
The portion of the silicon nitride film 56 indicated by the chain double-dashed line is removed, and sidewall insulating films 48 and 49 made of the silicon nitride film 56 are formed on the sidewalls of the gate 47. The conditions for the etch back process include, for example, trifluoromethane (CHF) with a flow rate of 75 sccm in the etching gas.
₃ ) and oxygen at a flow rate of 25 sccm are used to set the pressure of the etching atmosphere to 5.32 Pa and the etching power to 800 W. Usually, the silicon nitride film 56 contains about 20 at% hydrogen.

Thereafter, heat treatment is performed to diffuse the hydrogen contained in the silicon nitride film 56 into the active layer 43 formed in the polycrystalline silicon region 41 below the gate 47. The heat treatment at this time is, for example, 150 ° C. to 380.
It is carried out in an inert gas atmosphere having a temperature atmosphere of ° C. By performing the heat treatment, hydrogen in the silicon nitride film 56 is released and diffused into the polycrystalline silicon region 41. The crystal grain boundaries generated in the active layer 43 are filled with hydrogen atoms. In this way, the active layer 43 is hydrogenated. As described above, the thin film transistor 42 is formed.

Then, as shown in (7) of FIG. 3, a titanium film 57 is formed to a thickness of, for example, 30 nm on the entire surface on which the thin film transistor 42 is formed by, for example, an ordinary sputtering method.
To the thickness of. The sputtering conditions at this time are:
Argon (Ar) having a flow rate of 40 sccm is used as a sputtering gas, a high frequency bias is set to -50 W, a DC sputtering power is set to 1 kW, a sputtering temperature is set to 200 ° C, and a sputtering rate is set to 60 nm / min.

Thereafter, as shown in (8) of FIG. 4, for example, an annealing process for rapidly heating (hereinafter abbreviated as RTA)
By the titanium of the titanium film (57) and the gate 47
Silicon of the titanium film (57) and the silicon of the polycrystalline silicon region 41 are silicidized with the silicon of the low resistance layer 50-.
A titanium silicide (TiSi ₂ ) film to be 52 is formed. As the condition of the RTA, for example, the temperature is 650.
Conducted in an inert gas atmosphere at ℃.

After that, the titanium film (57) which has not reacted is removed by immersing it in, for example, ammonia-hydrogen peroxide mixture for 10 minutes. Then, the titanium silicide (TiSi ₂ ) film is stabilized by annealing in an inert gas [for example, nitrogen (N ₂ )] at 900 ° C.
Low resistance layers 50 to 52 are formed on the drain layers 44 and 45 and the gate 47. During RTA for silicidation, usually, silicon of the sidewall insulating film formed on the sidewall of the gate reacts with titanium of the titanium film to generate titanium silicide. At this time,
Titanium silicide is generated in a state of creeping up on the sidewall insulating film. However, since the sidewall insulating films 48 and 49 of this embodiment are formed of the silicon nitride film, the titanium of the titanium film (57) and the silicon of the sidewall insulating films 48 and 49 do not undergo a silicidation reaction.
Therefore, the gate 47-the source / drain regions 44, 4
The leak current between 5 does not increase. Therefore, the electrical characteristics of the thin film transistor 42 are improved.

Thereafter, by the usual chemical vapor deposition method,
A second insulating film (interlayer insulating film) 15 made of a silicon oxide film is formed with a thickness of, for example, 500 nm so as to cover the thin film transistor 42. As the film forming conditions at this time, for example, the reaction gas is a mixed gas of silane (SiH ₄ ) having a flow rate of 250 sccm, oxygen (O ₂ ) having a flow rate of 250 sccm, and nitrogen (N ₂ ) having a flow rate of 100 sccm. The film forming temperature is set to 420 ° C. and the pressure of the film forming atmosphere is set to 13.3 Pa.

Then, for example, an annealing treatment is performed for 10 seconds in a nitrogen (N ₂ ) atmosphere at a temperature of 1100 ° C. to activate the active layer 43 in the polycrystalline silicon region 41 and the low resistance layers 50 to 52. And the impurities in the polycrystalline silicon region 42 are diffused to form a junction region.

Then, contact holes 16 communicating with the source / drain regions 45 are formed by ordinary photolithography and etching. The etching conditions are, for example, an etching gas flow rate of 50 sc.
cm octafluorocyclobutane (C ₄ F ₈ ) is used, the high frequency power is set to 1.2 kW, and the etching atmosphere pressure is set to 2 Pa.

Thereafter, as shown in FIG. 4 (9), a titanium film (not shown) which is a lower layer of the barrier metal layer 18 is formed inside the contact hole 16 and on the upper surface of the second insulating film 15 by an ordinary sputtering method. Is formed to have a thickness of, for example, 50 nm. As the sputtering conditions at this time, argon (Ar) having a flow rate of 40 sccm is used as the sputtering gas, the pressure of the sputtering atmosphere is 0.4 Pa, the DC sputtering power is 1 kW, and the sputtering rate is 90 nm / min. Then, a titanium oxide film (not shown) to be an upper layer of the barrier metal layer 18 is formed by an ordinary sputtering method.
For example, it is formed to a thickness of 100 nm. As the sputtering conditions at this time, for example, the flow rate of the sputtering gas is 47 s.
Using a mixed gas of ccm of nitrogen (N ₂ ) and a flow rate of 3 sccm of oxygen (O ₂ ), the pressure of the sputtering atmosphere is set to 0.5 Pa, the DC sputtering power is set to 3 kW, and the sputtering rate is set to 60 nm / min. Then, an aluminum film 19 containing 1% of silicon is formed on the surface of the barrier metal layer 18 by, for example, 80 by a normal sputtering method.
It is formed to a thickness of 0 nm. As the sputtering conditions at this time, for example, argon (Ar) having a flow rate of 40 sccm is used as the sputtering gas, and the pressure of the sputtering atmosphere is 0.4.
Pa, DC sputter power is set to 0.6 kW, and sputter speed is set to 800 nm / min.

Thereafter, the portion of the aluminum film 19 indicated by the two-dot chain line and the portion of the barrier metal layer 18 indicated by the one-dot chain line are removed by ordinary photolithography and etching to form the wiring 17 of the first layer. To do. In the above etching, for example, an RF application type microwave etching device is used. Then, the flow rate of the etching gas is 60
Sccm Boron trichloride (BCl ₃ ) and flow rate 90 sc
cm 2 of chlorine (Cl ₂ ) and a microwave power of 1 kW, a high frequency power of 50 W, and an etching atmosphere pressure of 2.13 Pa.

In the manufacturing method described above, the crystal defects in the active layer 43 of the thin film transistor 42 are filled with hydrogen by the hydrogenation process. Therefore, the generation of leak current is suppressed. Further, the gate 47 and the source / drain regions 44 and 45 of the thin film transistor 42 are the low resistance layer 50.
~ 52 results in low resistance. Therefore, the sheet resistance on the source / drain regions 44 and 45 and the gate 47 is lowered to, for example, 8 Ω / □ or less. Therefore, the high speed operation of the thin film transistor 42 becomes possible.

Next, a second embodiment will be described with reference to the schematic cross-sectional view of FIG. In the figure, the same components as those described in the first embodiment are designated by the same reference numerals. As shown in the figure, the configuration of the SRAM 10 is the same as that of FIG. 1 except for the gate insulating film 46 of the thin film transistor 42, and therefore the description thereof is omitted here. The gate insulating film 46 of the thin film transistor 42 in the present embodiment is made of silicon nitride (Si
₃ N ₄ ) film. Further, the sidewall insulating films 48 and 49 are formed of a silicon nitride (P-SiN) film as in the first embodiment. Gate insulating film 46 formed of the above silicon nitride (Si ₃ N ₄ ) film
Usually contains about 5 wt% of hydrogen. Further, the sidewall insulating films 48 and 49 contain hydrogen of about 20 at% as in the case of the first embodiment.

As described above, the gate insulating film 46 and the sidewall insulating films 48, 4 are made of the silicon nitride film containing hydrogen.
9 is formed, it is possible to perform a hydrogenation process of diffusing sufficient hydrogen into the active layer 43 without stressing the polycrystalline silicon region 41 forming the source / drain regions 44 and 45.

To manufacture the thin film transistor of the second embodiment, the gate insulating film 46 described in (5) of FIG. 3 may be formed of a silicon nitride film. That is, instead of the silicon oxide film (54), the silicon nitride (Si ₃ N 4) is formed by, for example, an ordinary low pressure chemical vapor deposition method.
₄ ) The film (58) is formed to have a film thickness of 16 nm, for example.
The film forming conditions of the silicon nitride film (58) at this time are, for example, dichlorosilane (SiH ₂ Cl ₂ ) having a flow rate of 50 sccm, ammonia (NH ₃ ) having a flow rate of 200 sccm, and nitrogen (N) having a flow rate of 200 sccm.
₂ ) using a mixed gas consisting of
The pressure of the film forming atmosphere is set to 70 Pa. As the etching conditions for forming the gate insulating film 46 with the silicon nitride film, for example, a mixed gas of trifluoromethane (CHF ₃ ) having a flow rate of 75 sccm and oxygen having a flow rate of 25 sccm is used as the etching gas. The pressure of the etching atmosphere is set to 5.32 Pa and the etching power is set to 800 W.

Next, a third embodiment will be described with reference to the schematic sectional view of FIG. In the figure, the same components as those described in the first embodiment are designated by the same reference numerals. As shown in the figure, the gate insulating film 46 of the thin film transistor 42 is formed of a silicon nitride (for example, Si ₃ N ₄ ) film (58). The sidewall insulating film 48 is formed of a silicon oxide film 61 formed on one side wall of the gate 47 and a silicon nitride (eg, P-SiN) film 62 formed on the surface of the silicon oxide film 61. .. Similarly, the sidewall insulating film 49 includes a silicon oxide film 61 formed on the other side wall of the gate 47 and a silicon nitride film formed on the surface of the silicon oxide film 61 (for example, P
-SiN) film 62.

As described above, the sidewall insulating film 4
As a result of forming Nos. 8 and 49, each silicon nitride film 62
The stress generated at 1 is relaxed by the silicon oxide film 61. Therefore, the active layer 43 and the source / drain regions 4
Almost no stress is applied to the polycrystalline silicon region 41 in which 4, 45 are formed. Therefore, the effect of the hydrogenation process of diffusing the hydrogen contained in the sidewall insulating films 48 and 49 and diffusing the hydrogen released into the active layer 43 formed in the polycrystalline silicon region 41 is further enhanced.

A method of manufacturing the thin film transistor described in the third embodiment will be described with reference to FIG. (1) of FIG.
As shown in, the driver transistor 21 is formed on the semiconductor substrate 11, and the first insulating film 13 is further formed. Then, the contact hole 14 is provided in the first insulating film 13. Subsequently, a polycrystalline silicon region 41 is formed inside the contact hole 14 and on the upper surface of the first insulating film 13. Up to this point, it is manufactured in the same manner as described in (4) of FIG.

Then, as shown in FIG. 7B, silicon nitride (for example, Si ₃ N 4) is formed to cover the polycrystalline silicon region 41 by, for example, a normal low pressure chemical vapor deposition method.
₄ ) The film 58 is formed to have a thickness of 16 nm, for example. The conditions for forming the silicon nitride film 58 at this time are, for example, dichlorosilane (SiH ₂ Cl ₂ ) having a flow rate of 50 sccm, ammonia (NH ₃ ) having a flow rate of 200 sccm, and nitrogen (N ₂ ) having a flow rate of 200 sccm in the reaction gas. Using a mixed gas consisting of, the film forming temperature is set to 760 ° C. and the pressure of the film forming atmosphere is set to 70 Pa.

Then, by the ordinary chemical vapor deposition method,
A polycrystalline silicon film 55 is formed on the surface of the silicon nitride film 58.
Is formed into a film having a thickness of, for example, 200 nm. The film forming conditions at this time are, for example, the same as those described in (5) of FIG. 3 above, and thus the description thereof is omitted here.

After that, the portion indicated by the chain double-dashed line of the polycrystalline silicon film 55 is removed by ordinary photolithography and etching, and the gate 4 of the thin film transistor is removed.
Form 7. Further, etching is performed to remove the portion indicated by the alternate long and short dash line of the silicon nitride film 58, and the gate insulating film 46 of the thin film transistor is formed by the silicon nitride film 56. The etching conditions of the polycrystalline silicon film 55 at this time are the same as those described in (5) of FIG.
The description here is omitted. Further, the etching conditions of the silicon nitride film 58 are the same as those of the silicon nitride film (56) described in the second embodiment, so the description thereof is omitted here.

Then, in the same manner as described with reference to FIG. 3 (5), the source / drain regions 4 are formed in the polycrystalline silicon regions 41 on both sides of the gate 47 by the normal ion implantation method.
4, 45 are formed. Since the ion implantation conditions at this time are the same as those described in (5) of FIG. 3, the description thereof is omitted here. Thereafter, as shown in (3) of FIG. 7, a silicon oxide film 61 is formed to a thickness of, for example, 50 nm on the entire surface on the gate 47 side by a normal chemical vapor deposition method. The film forming conditions at this time are, for example, silane (S) with a flow rate of 250 sccm as described in (2) of FIG.
iH ₄ ), oxygen (O ₂ ) having a flow rate of 250 sccm, and nitrogen (N ₂ ) having a flow rate of 100 sccm are used, the film forming temperature is 420 ° C., and the pressure of the film forming atmosphere is 13.
Set to 3 Pa.

Then, a silicon nitride (eg P-SiN) film 62 is formed on the surface of the silicon oxide film 61 by a chemical vapor deposition method (P-CVD method) using ordinary plasma.
Is formed to have a thickness of 300 nm, for example. The film forming conditions at this time are, for example, as described in (6) of FIG. 3 above, in the reaction gas, silane (SiH ₄ ) having a flow rate of 180 sccm and ammonia (N
H ₃ ) and nitrogen (N ₂ ) with a flow rate of 720 sccm are used, the film forming temperature is set to 200 ° C., and the pressure of the film forming atmosphere is set to 39.9 Pa.

Then, by a normal etch-back process,
A portion of the silicon nitride film 62 indicated by a two-dot chain line and a portion of the silicon oxide film 61 indicated by a one-dot chain line are removed, and a sidewall formed of the silicon nitride film 62 and the silicon oxide film 61 on the side wall of the gate 47. Insulating films 48 and 49 are formed. At this time, sidewalls made of the silicon nitride film 62 and the silicon oxide film 61 are also formed on the step portion of the polycrystalline silicon region 41. The conditions for the etch back process are, for example, an etching gas flow rate of 75 sc.
cm Trifluoromethane (CHF ₃ ) and flow rate 25s
Using a mixed gas of ccm oxygen and an etching atmosphere with a pressure of 5.32 Pa and an etching power of 800
Set to W.

Thereafter, heat treatment is performed to allow hydrogen contained in the silicon nitride (P-SiN) film 62 of the sidewall insulating films 48 and 49 to pass through the silicon oxide film 61 and pass through the polycrystalline film below the gate 47. It diffuses into the active layer 43 formed by the silicon region 41. The heat treatment at this time is
For example, it is performed in an inert gas atmosphere having a temperature atmosphere of 150 ° C. to 380 ° C. By performing the heat treatment as described above, hydrogen in the sidewall insulating films 48 and 49 and hydrogen in the gate insulating film 46 are released and taken into the polycrystalline silicon region 41. Then, a portion of the polycrystalline silicon region 41 where the active layer 43 is formed is hydrogenated. In this way, the thin film transistor 42 is formed.

Thereafter, the same steps as those shown in FIGS. 3 (7) to 4 (9) are performed to form a low resistance layer (not shown), an interlayer insulating film (not shown), and a first layer. Wiring (not shown) and the like are formed.

[0065]

As described above, according to the inventions of claims 1 to 3, as a portion near the active layer of the thin film transistor, a sidewall insulating film made of a silicon nitride film is formed on the sidewall of the gate of the thin film transistor. Since it is formed, the stress applied to the thin film transistor by the silicon nitride film can be reduced. Furthermore, by forming the gate insulating film of the thin film transistor with a silicon nitride film, it becomes possible to diffuse a sufficient amount of hydrogen into the active layer. Further, since the sidewall insulating film is formed of the silicon oxide film and the silicon nitride film, the stress applied to the thin film transistor by the silicon nitride film can be relieved by the silicon oxide film. Therefore, the stress applied to the thin film transistor can be significantly reduced. Further, according to the invention of claim 4, after forming the gate, at least a silicon nitride film is formed on a part of the periphery of the gate, and hydrogen contained in the silicon nitride film is released, whereby the polycrystalline silicon region is formed. Since the active layer formed in the above is hydrogenated, the stress of the silicon nitride film is hardly applied to the active layer of the thin film transistor. Therefore, crystal defects do not occur in the active layer of the thin film transistor. Therefore, among the electrical characteristics of the thin film transistor, the carrier mobility characteristic can be particularly improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram (1) of the first embodiment.

FIG. 3 is a manufacturing process diagram (2) of the first embodiment.

FIG. 4 is a manufacturing process diagram (3) of the first embodiment.

FIG. 5 is a schematic configuration sectional view of a second embodiment.

FIG. 6 is a schematic structural cross-sectional view of a third embodiment.

FIG. 7 is a manufacturing process diagram of the third embodiment.

FIG. 8 is a schematic configuration sectional view of a conventional example.

FIG. 9 is a manufacturing process diagram (1) of a conventional example.

FIG. 10 is a manufacturing process diagram (2) of the conventional example.

[Explanation of symbols]

11 semiconductor substrate 41 polycrystalline silicon region 42 thin film transistor 43 active layer 44 source / drain region 45 source / drain region 46 gate insulating film 47 gate 48 sidewall insulating film 49 sidewall insulating film 56 silicon nitride film 58 silicon nitride film 61 silicon oxide Film 62 Silicon nitride film

Claims (4)

[Claims] 1. A polycrystalline silicon region provided on a substrate, an active layer formed in the polycrystalline silicon region, source / drain regions provided in the polycrystalline silicon region on both sides of the active layer, and the active region. A thin film transistor formed of a gate provided on a layer through a gate insulating film, wherein the active layer is hydrogenated, and a sidewall insulating film made of a silicon nitride film is formed on a side wall of the gate. Is a thin film transistor. 2. A polycrystalline silicon region provided on a substrate, an active layer formed in the polycrystalline silicon region, source / drain regions provided in the polycrystalline silicon region on both sides of the active layer, and the active region. A gate provided on the layer through a gate insulating film, wherein a sidewall insulating film made of a silicon nitride film is formed on a side wall of the gate in a thin film transistor formed by hydrogenating the active layer, A thin film transistor in which the gate insulating film of the thin film transistor is formed of a silicon nitride film. 3. A polycrystalline silicon region provided on a substrate, an active layer formed in the polycrystalline silicon region, source / drain regions provided in the polycrystalline silicon region on both sides of the active layer, and the active region. A thin film transistor formed by hydrogenating the active layer, wherein a sidewall insulating film is formed on a sidewall of the gate and the sidewall insulating film is formed. A thin film transistor, wherein the film is formed of a silicon oxide film formed on a sidewall of the gate and a polycrystalline silicon region in the vicinity thereof, and a silicon nitride film formed on a surface of the silicon oxide film. 4. Forming a polycrystalline silicon region on a substrate,
Next, in a method of manufacturing a thin film transistor, wherein a gate is formed on the polycrystalline silicon region via a gate insulating film, and then an active layer formed on the polycrystalline silicon region is hydrogenated, wherein a gate insulating film is formed on the polycrystalline silicon region. After forming the gate through the film, a silicon nitride film is formed on at least a part of the periphery of the gate, and then hydrogen contained in the silicon nitride film is released to form an active region in the polycrystalline silicon region. A method of manufacturing a thin film transistor, which comprises hydrotreating a layer.