JPH02172218A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a double-layer structure composed of a shallow conductive impurity diffused layer and a metal or metal silicide film formed on it with good controllability by a method wherein impurity compound gas is decomposed on the metal or metal silicide thin film and the impurity is selectively adsorbed and diffused into the metal or metal silicide thin film only. CONSTITUTION:After a metal or metal silicide thin film 17 is formed on the surface of a silicon layer 11, the surface is kept at a temperature at which compound gas of impurity for forming a P-type or N-type conductive layer can be decomposed in an atmosphere containing the impurity compound gas. The impurity compound gas is decomposed on the metal or metal silicide thin film 17 and the impurity produced by decomposition is selectively adsorbed and diffused into the metal or metal silicide thin film 17 only. With this constitution, double-layer structures composed of shallow P-type or N-type conductive layers 19 and 20 and the metal silicide thin films 17 formed on it can be formed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device, for example, in which a conductive material is formed in a metal formed on a semiconductor surface or in a semiconductor under a metal silicide film. Relating to a method of introducing impurities.

(Prior Art) Conventionally, in semiconductor devices, impurity diffusion layers with low electrical resistance, which are formed by introducing impurities into a silicon substrate or a silicon thin film, have been used for elements and wiring. However, as elements are becoming increasingly finer due to demands for higher integration and higher speed, it is necessary to reduce the dimensions of this impurity diffusion layer as well. In this case, the problem is that the resistance of the diffusion layer increases due to the reduction in dimensions. As a means to prevent this increase in resistance, a well-known method is to form a metal or metal silicide layer with low electrical resistance on top of an impurity diffusion layer formed on a silicon substrate or silicon thin film to create a two-layer structure. It is being

The process of forming a metal or metal silicide layer on this impurity diffusion layer to form a two-layer structure is shown in FIG. 3, taking the manufacturing process of a MOSFET as an example. Using an n-type silicon substrate, first, element isolation is performed by a normal process to form an element region, and then a gate oxide film 13 and a gate electrode 14 made of a polycrystalline silicon film are formed.

Furthermore, a silicon oxide film 15 is formed on the side walls of the gate electrode by depositing a CVD silicon oxide film and subsequent reactive ion etching (FIG. 3(a)).

Next, boron is introduced into the silicon substrate by ion implantation, followed by heat treatment at 950° C. for 60 minutes to form P-type impurity diffusion layers 19, 20. That is, source/drain regions are formed. Thereafter, a titanium film 16 is deposited on the entire surface (FIG. 3(b)), and then heat treatment is performed at 700° C. for 10 minutes to cause the titanium film 16 to react with the silicon substrate 11 and the polycrystalline silicon film 14.

A titanium silicide film 17 is formed on the P-type impurity diffusion layers 19 and 20 and the gate electrode 14. Subsequently, unreacted titanium film 16 due to silicon oxidation is removed by acid treatment (FIG. 3(C)). Thereafter, a well-known metallization process was performed to form an extraction electrode and wiring 22, and a titanium silicide film 17 was formed on the P-type impurity diffusion layer 19, 20 and the polycrystalline silicon gate electrode 14. - The transistor is completed (Fig. 3(d)).

In this example, if the P-type impurity diffusion layers 19 and 20 are not formed to a certain depth, the P-type impurity diffusion layer will be completely consumed by the reaction with the titanium film during silicide formation, and the substrate will become N-type conductive. There is a risk of short circuit with the layer. However, increasing the depth of the P-type impurity diffusion layer becomes a major hindrance to device miniaturization.

In the above example, a metal silicide layer is formed on the impurity diffusion layer, but FIG. 4 shows an example in which a metal layer is formed on the impurity diffusion layer. The steps up to the formation of the P-type impurity layers 19 and 20 are carried out in the same manner as in the example of FIG. 3 (FIG. 4(a)).

Next, tungsten l1%23 is selectively formed on the P-type impurity diffusion layer 19,20 and the gate electrode 14 by low pressure chemical vapor deposition (LP-CVD) using tungsten hexafluoride and silane as source gases. (Figure 4(b))
.

Thereafter, a well-known metallization process is performed as in the example shown in FIG. 3 to form an extraction electrode and wiring 22 to complete a P-channel MOS transistor (see
C)).

Even in this example, if the P-type impurity diffusion layers 19 and 20 are not formed to a certain depth, the substrate and tungsten hexafluoride will react when forming the tungsten film, and the tungsten will penetrate through the P-type impurity diffusion layer. There is a risk of formation, which becomes an obstacle to miniaturization of elements.

Furthermore, even when a conductive layer is formed by introducing impurities after forming a metal or metal silicide thin film as in the present invention, the conventional ion implantation method for introducing impurities is based on the projected range determined by the implantation energy. Metal over a certain thickness considered.

Alternatively, since a metal silicide film must be formed, it is necessary to increase the effective depth of the conductive layer, including the thickness of the metal or metal silicide thin film. Furthermore, if the thickness of the metal or metal silicide thin film is increased, the thickness of the polycrystalline silicon gate electrode of the MOS transistor as in the above example must also be increased to a certain extent, otherwise the gate electrode will be damaged due to the reaction during silicide formation or tungsten film formation. There is a risk of damaging the underlying gate oxide film.

This also impairs the flatness of the element and becomes an obstacle to miniaturization.

(Problems to be Solved by the Invention) In this way, in the conventional method, when forming a two-layer structure of a conductive impurity diffusion layer on the surface of a silicon substrate or a silicon thin film and a metal or metal silicide film thereon, It was difficult to form a shallow impurity diffusion layer with good reproducibility.

The present invention has been made in consideration of the above circumstances, and its purpose is to
It is possible to form a two-layer structure with metal or metal silicide film with good controllability, and by miniaturizing the elements, it is possible to increase the density of integrated circuits.

Another object of the present invention is to provide a method for manufacturing a semiconductor device that can contribute to increased speed.

[Structure of the invention]

(Means for Solving the Problems) The gist of the present invention is to form a metal or metal silicide thin film on the surface of a silicon substrate or a silicon thin film, and then to form a conductive layer in an atmosphere containing impurity compound gas. , the impurity compound gas is decomposed on the metal or metal silicide thin film to selectively adsorb and diffuse the impurity only on the metal or metal silicide thin film.

(Function) By using the present invention, shallow P type or N type
It becomes possible to form a two-layer structure having a metal or metal silicide thin film on the conductive layer.

That is, in the present invention, impurities for forming a P-type or N-type conductive layer are introduced after forming a metal or metal silicide thin film on the silicon surface in advance, so unlike the conventional example, during the metal or metal silicide forming reaction, Since silicon in the formed conductive layer is not consumed, there is no need to increase the depth of the conductive layer.

Furthermore, the present invention employs a method of forming a conductive layer by introducing impurities after forming a metal or metal silicide thin film. It is necessary to form a metal or metal silicide film with a certain thickness or more in consideration of the range, but as in the present invention, the impurity compound gas is decomposed on the metal or metal silicide thin film to remove the impurities. Because this method selectively adsorbs and diffuses only into metal or metal silicide thin films, it is possible to form metal or metal silicide thin films relatively thin, and the effective effect including the metal or metal silicide thin film thickness can be reduced. There is no need to increase the depth of the conductive layer. Furthermore, metal
Alternatively, since there is no need to increase the thickness of the metal silicide thin film, in the case of MOS transistors, polycrystalline silicon There is no need to increase the thickness of the gate electrode.

For these reasons, the present invention is extremely effective for miniaturizing elements and increasing the density of integrated circuits.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 1(a) to 1(d) are cross-sectional views showing a MOS transistor manufacturing process according to an embodiment of the present invention. First, as shown in FIG. 1(a), a field insulating film 12 is selectively formed on an n-type single crystal silicon substrate 11 by a well-known process, and an element region surrounded by the insulating film 12 is formed.

Subsequently, a gate oxide film 13 and a gate electrode 14 made of a crystalline silicon film are formed on the element region. Furthermore, C.V.
D A silicon oxide film 15 is formed on the sidewalls of the gate electrode 14 by depositing a silicon oxide film and subsequent reactive ion etching. after that.

A titanium film 16 with a thickness of 1000 Å is formed on the entire surface by sputtering.

Next, heat treatment was performed at 700°C for 30 minutes in a vacuum,
A titanium silicide film 17 is formed only on the silicon base [11] and on the polycrystalline silicon gate electrode 14. The unreacted titanium film on the insulating film is removed by subsequent acid treatment.

Next, the silicon substrate 11 is heated to 600° C. in a helium gas atmosphere, and then heated to a pressure 1 containing 0.25% diborane (sallG) while being maintained at that temperature.
B11. is decomposed, and boron 18 is selectively adsorbed only onto the titanium silicide film 17. The pressure here is preferably set in the range of 10-2 to 102 torr (FIG. 1(b)).

Next, the titanium silicide film 17 is heated at 900° C. for 60 minutes in an argon gas atmosphere.
The adsorbed boron 18 on the top is passed through the titanium silicide layer to the silicon substrate 11 and the polycrystalline silicon gate electrode 1.
4 to form a P-type conductive layer 19°20.

It is preferable that the temperature here be maintained at or above the temperature (decomposition temperature) in the step shown in FIG. 1(b) (FIG. 1(C)).

Note that if the temperature in the above-mentioned diffusion heat treatment is too low, the diffusion will be insufficient, and if it is too high, the diffusion distance will become long, so a temperature range of 600 to 1200° C. may be selected as a practical temperature range.

Next, as shown in FIG. 1(d), a CVD silicon oxide film 21 was deposited on the entire surface and holes for electrodes were made.

The electrode layer 22 is formed of aluminum. As a result, a silicide film 17 is formed at the source, drain, and gate, and a p-channel MOS transistor having shallow P-type trench conductive layers 19 and 20 thereunder is completed.

Thus, according to the method of this embodiment, the regions that will become the source and drain of the MOS transistor are formed in the shallow P-type trench layer 1.
9.20 and a titanium silicide film 17, and is extremely effective in forming low resistance and fine transistors.

In the above example, an example was shown in which impurities are adsorbed onto a metal silicide layer. However, as an example of adsorbing impurities onto a metal layer, for example, low pressure vapor phase chemical growth using tungsten hexafluoride and silane as raw material gases can be used. There is a MOS transistor manufacturing process in which a tungsten film is selectively formed on the source/train region and gate electrode of a silicon substrate by (LP-CVD). In this example, for example, after heating the silicon substrate 11 to 600° C. in a helium gas atmosphere, and keeping it at that temperature, diborane (B, H
,) is exposed to a helium gas atmosphere at a pressure of 1 torr containing 0.25% of tungsten film 23, H2H is decomposed on the surface, and boron 18 is selectively adsorbed only on the tungsten film 23 (see Fig. 2). a)), then by performing a heat treatment at 900 ° C. for 60 minutes in an argon gas atmosphere,
Adsorbed boron 18 on the tungsten film 23 is diffused into the silicon substrate 11 and the polycrystalline silicon gate electrode 14 through the tungsten film.

P-type trench layers 19 and 20 are formed (FIG. 2(b)). After this, the shallow P-type trench conductor layer 19, 20 and the tungsten film 23 are formed through a well-known metallization process in the same manner as in the above example.
A low-resistance, microscopic transistor is completed (Figure 2 (C)).

In the above embodiment, boron was used as the impurity and diborane (Bwns) was used as the impurity gas, but any boron compound gas may be used. In addition, impurities are not limited to impurities that form P- and N-type conductive layers, including boron, but also properties of silicon substrates, metals, or metal silicides (e.g., electrical resistance, defect suppression, ease of processing, heat resistance, chemical resistance). For example, hydrides, halogen compounds, or organic compounds of potassium, arsenic, phosphorus, and antimony may be used as long as the compound gas decomposes and adsorbs on the metal or metal silicide. etc.

Further, in the above embodiments, the compound gas is decomposed and adsorbed by thermal decomposition, but it may also be decomposed and adsorbed by light energy. Furthermore, by converting compound gas into plasma, metals,
Alternatively, it may be decomposed and adsorbed onto metal silicide.

〔Effect of the invention〕

According to the present invention, after forming a metal or metal silicide layer, an impurity compound gas is decomposed, adsorbed, and diffused on the metal or metal silicide.

There is a shallow P in the underlying silicon substrate or silicon thin film.
, or an N-type conductive layer, it is possible to form a low-resistance, fine wiring layer with a two-layer structure of a shallow conductive layer, a metal, and a metal silicide layer. Therefore, it is highly effective in manufacturing various semiconductor devices whose elements are increasingly miniaturized, including submicron transistors.

[Brief explanation of the drawing]

1 and 2 are process cross-sectional views of a MOS transistor according to an embodiment of the present invention, and FIGS. 3 and 4 are process cross-sectional views of a MOS transistor according to a conventional example. 11...Silicon substrate 12...Field oxide film 13...Gate oxide film 14...Polycrystalline silicon gate electrode 15...Side wall oxide film 16...Titanium film 17...Titanium silicide film 18 ... Adsorbed boron layers 19, 20 ... P-type trench conductor layer 21 ... CVD silicon oxide film 22 ... Electrode layer 23 ... Tungsten film Agent Patent attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama figure

Claims (1)

[Claims] A step of forming a metal or metal silicide thin film on the surface of a silicon layer, the formed metal,
Or in the silicon layer under the metal silicide thin film,
In the method of manufacturing a semiconductor device, the step of forming the P-type or N-type conductive layer includes forming the metal or metal silicide thin film on the surface of the silicon layer. After forming the P-type or N-type conductive layer, the metal or metal silicide thin film is heated by maintaining the surface at a temperature that can decompose the impurity compound gas in an atmosphere containing the impurity compound gas forming the P-type or N-type conductive layer. A method for manufacturing a semiconductor device, comprising the steps of thermally decomposing the impurity compound gas, and selectively adsorbing and diffusing the decomposed impurities only into the metal or metal silicide thin film.