JPH01295427A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent change of properties of a lower thin film layer due to heat treatment in forming an upper thin film layer effectively, by performing the final heat treatment at steps for forming the upper thin film layer at the temperature condition which is sequentially lower than that in the final heat treatment in steps for forming the lower thin film layer. CONSTITUTION:The characteristics of a thin film which undergoes heat treatment at a specified temperature are hardly changed even if heat treatment is performed at a temperature lower than said temperature in the succeeding steps. When, various kinds of thin films 2, 3, 5-8 are sequentially laminated on a semiconductor substrate 1, the temperature at the final heat treatment in the steps for forming each of the thin films 2, 3, 5-8 is made lower than the temperature at the final heat treatment of the thin film which is lower than said film. In this way, the change of properties of the lower thin film due to the heat treatment for forming the upper thin film layer can be effectively prevented. Thus, a highly reliable semiconductor device is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and in particular to a technology that is effective when applied to a heat treatment technology for thin films laminated on a semiconductor substrate.

[Conventional technology]

In the manufacturing process of semiconductor devices, thermal oxidation, CVD (che
vapor deposition), P
V D (physical vapor depos.
Forming various thin films such as insulating films, semiconductor films, and metal films on semiconductor substrates using various film formation technologies such as By doing so, a desired semiconductor integrated circuit is manufactured.

Regarding the above-mentioned film formation technology and impurity ion implantation/diffusion technology, see, for example, Science Forum Co., Ltd., published November 28, 1980, "Very LSI Handbook J.
There is a description on pages P106 to P121.

[Problem to be solved by the invention]

In the process of forming a thin film on a semiconductor substrate, heat treatment is performed at different temperatures depending on the film type and application, and the temperature range is wide ranging from room temperature to 1000° C. or higher.

However, the inventors have found that if heat treatment is performed at different temperatures in each step of forming a thin film, the film characteristics of the underlying thin film will change due to repeated heat treatments, causing device characteristics to fluctuate. Served.

In particular, in high-density, highly integrated semiconductor devices where the processing line width of various thin films is 1 μm or less, stress in the thin film caused by repeated heat treatments, changes in impurity profiles and crystals in the thin film, etc. have a significant effect on device characteristics. This results in a decrease in the reliability of the semiconductor device.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can effectively prevent deterioration of the lower layer thin film due to heat treatment during the formation of the upper layer thin film. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when a predetermined integrated circuit is formed by sequentially stacking a plurality of thin films on a semiconductor substrate, the final heat treatment in the step of forming the upper thin film is performed at a lower temperature than the final heat treatment in the step of forming the lower thin film. This is done in

[Effect]

The film characteristics of a thin film that has been heat-treated at a predetermined temperature will hardly change even if it is subsequently heat-treated at a temperature below that temperature.

Therefore, when various thin films are sequentially laminated on a semiconductor substrate, deterioration of each thin film can be effectively prevented by setting the final heat treatment temperature of each thin film forming process lower than the final heat treatment temperature of the thin film below the thin film. Ru.

〔Example〕

FIGS. 1(a) to 1(e) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

This example is applied to a method of manufacturing a MOS-FET, and the manufacturing method will be explained below in order of steps.

First, 5i
After depositing the ns film 2 and the SI3N4 film 3, etching is performed using a photoresist as a mask, leaving the S+aNa film 3 in a region where a transistor will be formed later.

Next, boron (B) ions are implanted from the surface of the substrate 10 to form a channel stopper region 4, and then the substrate 1 is wet-oxidized to form a field oxide film 5 for element isolation (FIG. 1(a)).

Next, after removing the show film 2 and 513N4 film 3 on the surface of the substrate 1 by etching, the surface of the transistor formation region surrounded by the field oxide film 5 is etched using a dry method or HC.
A gate oxide film 6 is formed using the I oxidation method.

Here, the heat treatment temperature T1 when forming the gate oxide film 6 is approximately 1000°C.

Next, a polysilicon film 7 is deposited on the surface of the substrate 1 by a thermal CVD method using a reactive gas such as S+Ha (FIGS. 1 and 7). Note that the temperature conditions for this thermal CVD step are, for example, 5.
The temperature is 50-650°C.

Next, in order to impart conductivity to the polysilicon film 7,
For example, about 10 ffl of phosphorus (P) is added.

The heat treatment temperature T2 at this time is around 1000°C, but in order to suppress the deterioration of the gate oxide film 6 formed in the lower layer, the heat treatment temperature T2 when forming the gate oxide film 6 is
lower temperature than

Next, a silicide film 8 such as Mo51 or W Si 2 is deposited on the surface of the substrate 1 using the CVD method.

The temperature conditions for this CVD process are, for example, 300 to 500°C.
It is.

Next, heat treatment is performed to stabilize the quality of the silicide film 8. The heat treatment temperature T at this time.

In order to suppress deterioration of the underlying gate oxide film 6 and polysilicon film 7, the heat treatment temperature T2 during the phosphorus treatment is
(for example, around 950°C).

Next, the polysilicon film 7 and the silicide film 8 are etched using a photoresist as a mask to form a gate electrode 9 having a polycide structure consisting of two layers of the polysilicon film 7 and the silicide film 8 (see FIG. 1). (C)).

Next, using the gate electrode 9 as a mask, phosphorus ions or the like are implanted from the surface of the substrate 1 to form low concentration diffusion regions 10 in the substrate 1 on both sides of the gate electrode 90. Deposit the membrane. The temperature conditions for this CVD step are, for example, 700 to 750°C.

Next, the SiO2 film is processed by an etch-back method using anisotropic etching such as reactive ion etching (RIE) to form a spacer 11 on the side wall of the gate electrode 9. Heat treatment is performed to stabilize the film quality.

The heat treatment temperature T4 at this time is lower than the heat treatment temperature T of the silicide film 8 (for example, 920 to 930°C
degree).

Next, using the gate electrode 9 and the spacer 11 on its side wall as a mask, arsenic (As) ions or the like are implanted into the surface of the substrate 10 to form high concentration diffusion regions 12 on both sides of the gate electrode 9, and then a CVD method is performed. An interlayer insulating film 13 made of phosphosilicate glass (PSG) or the like is deposited on the surface of the substrate 1 using a method (FIG. 1(d)). The temperature conditions for this CVD step are, for example, 350 to 450°C.

Next, the substrate 1 is heated in a reflow oven to planarize the interlayer insulating film 13. The heat treatment temperature T at this time is the lower layer gate oxidation WX6, the gate electrode 9 and the spacer 11.
Due to the need to suppress the deterioration of the spacer 11, the heat treatment temperature T of the spacer 11 is
4 (for example, around 900°C).

Next, contact holes 14 are formed by drilling at predetermined locations in the planarized interlayer insulating film 13, and then an Al film is deposited on the surface of the substrate 1 by sputtering. The temperature conditions for this sputtering process are, for example, around 350°C.

Next, the Al film is etched to form the Al wiring 15.
After forming, heat treatment temperature TI is applied in a reducing atmosphere.
A heat treatment is performed at a temperature of 400 to 500° C. to stabilize the bond between the Al wiring 15 and the high concentration diffusion region 12 connected through the contact hole 14.

Finally, after depositing a passivation film 16 made of 3102 on the surface of the substrate 1 using the CVD method, holes are formed at predetermined locations to form electrode pads (not shown), thereby completing the MOS-FET. (Figure 1(e)).

In this embodiment, which consists of the above steps, a MOS-FET is formed by sequentially stacking a gate oxide film 6, a gate electrode 9, a spacer 11, an interlayer insulating film 13, and an Al wiring 15 on the surface of the substrate 1 from the bottom layer. In this case, since the final heat treatment temperature (T, ~Ts) of each thin film forming step was gradually lowered, deterioration of each thin film due to repeated heat treatments is effectively prevented, and a highly reliable MOS-FET can be obtained.

As above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

For example, in the embodiment described above, the case where the present invention is applied to a method of manufacturing a MOS-FET has been described, but the present invention is not limited to this, and can be applied to a method of manufacturing various semiconductor devices such as a bipolar type semiconductor device.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when forming a predetermined integrated circuit by sequentially stacking a plurality of thin films on a semiconductor substrate, the final heat treatment temperature in the step of forming the upper layer thin film is successively lower than the final heat treatment temperature in the step of forming the lower layer thin film. By doing so, deterioration of the lower thin film due to heat treatment during formation of the upper thin film can be effectively prevented, and a highly reliable semiconductor device can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are sectional views of essential parts of a semiconductor substrate showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1... Semiconductor substrate, 2... SiO2 film, 3...5
13N4 film, 4... channel stopper region, 5...
Field oxide film, 6... Gate oxide film, 7... Polyrecon film, 8... N-IJ side film, 9... Gate electrode, 10... Low concentration diffusion region, 11... Spacer, 12...High concentration diffusion region, 13...Interlayer insulating film, 14...Contact hole, 15...Al wiring,
16... Passivation film. Agent Patent Attorney Daiwa Tsutsui Figure 1

Claims (1)

[Claims] 1. When forming a predetermined integrated circuit by sequentially laminating multiple thin films on a semiconductor substrate, the final heat treatment temperature in the process of forming the upper layer thin film is set to be lower than the final heat treatment temperature in the process of forming the lower layer thin film. A method of manufacturing a semiconductor device, characterized in that the manufacturing method of the semiconductor device is made low.