JPH03214735A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent oxidation of the surface of a silicide and eliminate contact failure between a silicide surface wire and a polycrystalline silicon layer by directly depositing a polycrystalline silicon film onto a wiring layer consisting of a high melt-point metal silicide using the sputtering method within an inactive gas environment. CONSTITUTION:After forming an element such as a transistor onto a semiconductor substrate 1, a first interlayer insulation film 2 is allowed to grow and a tungsten silicide (WSi2) is deposited on the entire surface. Then, a patterning is made for forming a wire 3 and then a second-layer interlayer insulation film 4 is allowed to grow. And then, a contact hole 5 is formed. Then, after performing RF etching, a polycrystalline silicon film 6 is deposited by the sputtering method within Ar gas environment. Then, a highly dense phosphor is ion-impregnated into the entire substrate surface and then etching is performed by a low-concentration hydrofluoric acid. After that, a polycrystal silicon film 7 is allowed to grow by the CVD method and then the polycrystal silicon films 6 and 7 are subjected to patterning for forming an upper-layer wire, thus preventing generation of an oxide at the interface between a tungsten silicide wire and the polycrystalline silicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of connecting a wiring made of high melting point metal silicide and a polycrystalline silicon layer.

[Conventional technology]

A conventional semiconductor device manufacturing method that includes a process of connecting wiring made of high-melting point metal silicide and a polycrystalline silicon layer,
This will be explained using FIG. First, as shown in FIG. 2(a), a first interlayer insulating film 2 such as a silicon oxide film is formed on a semiconductor substrate 1, and then a wiring 3 of high melting point metal silizite such as W Si 2 is formed. Next, a second interlayer insulating film 4 made of phosphorus glass or the like is formed. Thereafter, the contact hole 5 is etched using ordinary lithography and etching techniques.
Drill a hole.

Next, as shown in Fig. 2(b), this contact 1/hole 5
A polycrystalline silicon film 7 is grown over the entire surface by CVD so as to fill the area.

CVD growth of a polycrystalline silicon layer is usually performed in a low-pressure furnace, but the temperature is relatively high and the wafer is exposed to an oxygen atmosphere when entering the furnace. Oxide 8 may be formed,
This caused contact failure.

[Problem to be solved by the invention]

In the conventional method of connecting a high-melting point metal silicide wiring and a polycrystalline silicon layer as described above, a polycrystalline silicon layer is grown by CVD while the surface of the high-melting point metal silicide wiring is damaged by etching. CVD furnaces have relatively high temperatures, and the wafers are exposed to an oxygen atmosphere when entering the furnace, so silicide oxides are generated on the surface of high-melting point metal silicide wiring, which tends to cause contact failures and reduce the reliability of semiconductor devices. It has the disadvantage of reducing condylarity and yield.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a wiring made of high melting point metal silicide on a semiconductor substrate, forming an insulating film on the entire surface including the wiring, and forming a contact hole in the insulating film. and a step of depositing a polycrystalline silicon layer over the entire surface including the contact hole by sputtering in an inert gas atmosphere.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention.

First, as shown in FIG. 1 (a), elements such as transistors and diodes are formed on a semiconductor substrate 1, and then a silicon oxide film is deposited as a first interlayer insulating film 2 at approximately 2000 A by a normal CVD method. Next, tank stencil silicide (WSi2) is deposited on the entire surface by the normal sputter link method to a thickness of approximately 0008 cm, and then patterned using lithographing technology to form a tank sten silicide. A wiring 3 is formed. Then, a phosphorus glass film (PSG film) is formed as a second interlayer insulating film 4 to a thickness of about 4
After 00OA growth, contacts 1 and holes 5 are formed using lithography and etching techniques.

Next, as shown in FIG. 1(b), after performing surface treatment (RF etching) using high frequency in a near-vacuum state, the sputter link method was subsequently performed in an Ar gas atmosphere.
A polycrystalline silicon film 6 is deposited to a thickness of approximately 500 mm.

Next, as shown in Figure 1(c), in order to obtain conductivity,
High-concentration phosphorus (1016 cm'') is ion-implanted over the entire surface of the substrate. Thereafter, the surface is etched for several tens of seconds with low concentration hydrofluoric acid, and then a polycrystalline silicon film 7 is grown to a thickness of about 1 μm by the usual CVD method. In this state, polycrystalline silicon II! 6.7 is patterned to form upper layer wiring.

Note that the polycrystalline silicon films 6 and 7 are etched using an isotropic dry etching technique until the surface of the second interlayer insulating film 4 is exposed, so that the contact hole 5 is filled with polycrystalline silicon, and then, A metal such as aluminum is deposited by sputtering and patterned by lithography to form an upper layer wiring made of aluminum.

As described above, according to this embodiment, it is possible to prevent the formation of oxides at the interface between the wiring made of tungsten silicide and the polycrystalline silicon film, thereby eliminating contact defects.

5. In the above embodiment, a wiring made of only tank stencil silicide has been described, but it goes without saying that the wiring may have a multilayer structure (polysite) consisting of a polycrystalline silicon layer and a high melting point metal silicide layer.

〔Effect of the invention〕

As explained above, the present invention deposits a polycrystalline silicon film directly on a wiring layer made of high-melting point metal silicide by sputtering in an inert gas atmosphere, thereby preventing oxidation of the silicide surface and connecting the silicide wiring and polycrystalline silicon. Contact defects between layers can be eliminated.

Therefore, reliability and yield of semiconductor devices can be improved.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1<a> to (C) are cross-sectional views of a semiconductor chip for explaining one embodiment of the present invention, and FIGS. 2(a> and (1+) are cross-sectional views of a conventional semiconductor device. 6 is a cross-sectional view of a semiconductor chip for explaining an example of a manufacturing method.]...semiconductor substrate, 2. first interlayer insulating film, 3.
... Wiring, 4... Second interlayer insulating film, 5... Contact hole, 6, 7... Polycrystalline silicon film, 8... Silicide oxide.

Claims (1)

[Claims] forming a wiring made of high melting point metal silicide on a semiconductor substrate; forming an insulating film over the entire surface including the wiring; forming a contact hole in the insulating film;
A method for manufacturing a semiconductor device, comprising the step of depositing a polycrystalline silicon layer over the entire surface including the contact hole by sputtering in an inert gas atmosphere.