JPS639925A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS639925A JPS639925A JP15437686A JP15437686A JPS639925A JP S639925 A JPS639925 A JP S639925A JP 15437686 A JP15437686 A JP 15437686A JP 15437686 A JP15437686 A JP 15437686A JP S639925 A JPS639925 A JP S639925A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- contact hole
- titanium
- film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000012298 atmosphere Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 13
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 239000010936 titanium Substances 0.000 abstract description 5
- 229910052719 titanium Inorganic materials 0.000 abstract description 5
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に電極取り出
し部における配線用金属の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming wiring metal in an electrode lead-out portion.
従来、この種の電極取出し部は配線用金属に主にアルミ
ニウムを用い、スパッタ法に工って、コンタクト用の開
孔が形成されている絶縁膜上に一様に被着し次後パター
ニングすることにより、半導体基板の能動素子、受動素
子とコンタクトを取っている。Conventionally, this type of electrode lead-out part mainly uses aluminum as the wiring metal, is made by sputtering, and is uniformly deposited on an insulating film in which contact holes are formed, and then patterned. This makes contact with the active elements and passive elements of the semiconductor substrate.
近年、半導体集積回路の高密度集積化に伴って素子の微
細化が進み、設計ルールは今やサブミクロンオーダーに
なろうとしている。その為゛ｍ電極取出部の開孔、即ち
コンタクト孔は、断面アスペクト比が増大の一途を辿っ
ている。なぜならば、コンタクト孔を開ける絶Ｒ膜の厚
さは、線間容量増大を避けるため薄くすることかで＠な
いのに、コンタクト孔の平面的寸法が上述の理由で減少
するからである。そして、この断面アスペクト比が大き
いコンタクト孔は「日影効果」に工９従来のスパッタ法
では埋められなくなってきている。そこで金属の選択ｅ
ｖ ＩＪ−？ Ｌｉ’ｅｖｂ多結晶ケイ多結晶ケイン
タクト孔埋め込み等が提案されているが、いずれもまだ
開発段階であり、現在のところ高断面アスペクト比のコ
ンタクト孔を埋め込む技術は無いに等しいといって良い
。In recent years, as semiconductor integrated circuits have become more densely integrated, elements have become smaller and smaller, and design rules are now on the order of submicrons. Therefore, the cross-sectional aspect ratio of the opening of the electrode extraction portion, that is, the contact hole, continues to increase. This is because, although the thickness of the absolute R film that forms the contact hole should be made thinner in order to avoid an increase in line capacitance, the planar dimensions of the contact hole are reduced for the above-mentioned reasons. Contact holes with a large cross-sectional aspect ratio cannot be filled by conventional sputtering methods due to the "shadow effect." Therefore, the choice of metal
v IJ-? Li'evb polycrystalline silica polycrystalline contact hole burying has been proposed, but all of them are still in the development stage, and it can be said that there is currently no technology for burying contact holes with high cross-sectional aspect ratios.
本発明の半導体装董の製造方法は、半導体基板の一主面
に形成した能動素子、受動素子と配線体との接続点の絶
縁膜に開孔を形成する工程と、少なくとも開孔の口が完
全に塞がる姿態で金属を形成する工程と、金属形既工程
より高い気圧の雰囲気において金属が流動する温度で熱
処理する工程とを有することを特徴とする。The method for manufacturing a semiconductor device of the present invention includes a step of forming an opening in an insulating film at a connection point between an active element, a passive element, and a wiring body formed on one main surface of a semiconductor substrate, and at least forming an opening of the opening. It is characterized by having a step of forming the metal in a completely closed state, and a step of heat-treating it at a temperature at which the metal flows in an atmosphere with a higher pressure than the metal forming process.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の製造工程断面図である
。まず、第１図（ａ）に示すように、例えば単結晶ケイ
素基板１０１上に酸化ケイ素１０２のような絶縁膜全厚
さ１．５μｍ程度形成し、直径α８μ程度の開孔１０３
ｉ７オトリソグラ７お工ひ反応性スパッタエツチングに
Ｌシ形成する。次に第１図（ｂ）に示すようにアルミニ
ウム１０４をスパッタ法で数１０ｍＴｏｒｒの圧力で厚
さ１μｍ８度底長すると開孔肩部にアルミが異常底長し
、口は完全に塞がれるが中に「す」ができる。次に、大
気圧状態のＮ２雰囲気で約５００℃の熱処理を数１０秒
間行うと、第１図（Ｃ）に示すようにアルミニウム１０
４は開孔部の「す」に押し込まれ開孔はほぼアルミ１０
４で埋め込まれる。FIG. 1 is a sectional view of the manufacturing process of the first embodiment of the present invention. First, as shown in FIG. 1(a), an insulating film such as silicon oxide 102 with a total thickness of about 1.5 μm is formed on a single crystal silicon substrate 101, and an opening 103 with a diameter of about α8 μm is formed.
i7 Otolithography 7 is used to form an L-shape using reactive sputter etching. Next, as shown in Fig. 1(b), when aluminum 104 is sputtered to a thickness of 1 μm and lengthened by 8 degrees at a pressure of several tens of mTorr, the aluminum becomes abnormally long at the shoulder of the opening, and the opening is completely closed. ``su'' is formed inside. Next, when heat treatment is performed at about 500°C for several tens of seconds in an N2 atmosphere at atmospheric pressure, aluminum 10
4 is pushed into the "s" of the hole and the hole is almost aluminum 10
Embedded in 4.
第１の５ｊ！施例ではアルミニウムを直接基板に接続さ
せ友が、この５００℃の熱処理の際アルミニウムは基板
のシリコンに溶は込み、コンタクト部に接合が形成され
ている場合、この接合を破壊する。First 5j! In this embodiment, aluminum is directly connected to the substrate, but during this heat treatment at 500° C., the aluminum melts into the silicon of the substrate, and if a bond is formed at the contact portion, this bond is destroyed.
そこでこの接合破壊を避けるには、耐熱性に優れ次バリ
アメタルを用いれば良い。Therefore, in order to avoid this joint breakdown, a barrier metal with excellent heat resistance may be used.
第２図ゆ本発明の第２の実施例の製造工程断面図である
。FIG. 2 is a sectional view of the manufacturing process of a second embodiment of the present invention.
第２の実施例では窒化チタンをバリアメタルに使用しｔ
場合につき説明する。まず、第２図（ａｌに示す工うに
、第１の実施例同様単結晶ケイ素基板２０１上に絶縁膜
２０２を形成し、コンタクトの開孔２０３を形成する。In the second embodiment, titanium nitride is used as the barrier metal.
I will explain each case. First, as shown in FIG. 2 (al), an insulating film 202 is formed on a single-crystal silicon substrate 201 as in the first embodiment, and a contact opening 203 is formed.
続いてチタン２０４を厚さ０．１μｍ程度ｅＶＤ法によ
り成長し、窒素雰囲気中で９００上程度の熱処理を行う
と、チタン２０４は第２図（ｂ）に示すＬうに窒化チタ
ン２０５になる。Subsequently, titanium 204 is grown to a thickness of about 0.1 μm by the eVD method and heat-treated at about 900 nm or more in a nitrogen atmosphere, so that titanium 204 becomes titanium nitride 205 as shown in FIG. 2(b).
但し、基板表面ではチタンシリサイド２０６も同時に形
成され、この部分では窒化チタン２０５゜チタンシリサ
イド２０６の２層構造となる。以下筒１の実施例と同様
にアルミニウムｔ−埋め込んで第２図（Ｃ）に示す工う
に配線用金属であるアルミニウム２０７を形成する。However, titanium silicide 206 is also formed on the substrate surface at the same time, resulting in a two-layer structure of titanium nitride 205° and titanium silicide 206 in this portion. Thereafter, in the same manner as in the embodiment of cylinder 1, aluminum t-embedding is performed to form aluminum 207, which is a metal for wiring, in the structure shown in FIG. 2(C).
以上筒１お工び第２の実施例では配線用金属としてアル
ミニウム、バリアメタルとして窒化チタンを挙げたが、
本発明はこれらの材料に限定するものではなく他の金属
やバリアメタルを用いても同様に有効であることはいう
までもない。In the above second example of manufacturing the tube 1, aluminum was used as the wiring metal and titanium nitride was used as the barrier metal.
It goes without saying that the present invention is not limited to these materials, and is equally effective using other metals or barrier metals.
以上説明した通り本発明は、電極取り出しに用いる金属
を接続孔に被着後溶融温度で熱処理することに工夛高断
面アスペクト比の接続孔を配線金属で埋め込み、信頼性
の高い半導体装置を得ることができる効果がある。As explained above, the present invention provides a highly reliable semiconductor device by heat-treating the metal used for electrode extraction at a melting temperature after depositing on the contact hole, and filling the contact hole with a high cross-sectional aspect ratio with wiring metal. There is an effect that can be done.
第１図は本発明の第１の実施例の製造工程断面図、第２
図は本発明の第２の実施例の製造工程断面図である。
１０１．２０１・・・単結晶ケイ素基板、１０２・・・
酸化ケイ素、２０２・・・絶縁膜、１０３，２０３・・
・開孔、１０４．２０７・・・アルミ、２０４・・・チ
タン、２０５・・・窒化チタン、２０６・・・チタンシ
リサイド。
代理人 弁理士 内 原 ２ 町。
錦 １ 図
（α）
（し）
＜Ｃ）
端２図FIG. 1 is a sectional view of the manufacturing process of the first embodiment of the present invention, and the second
The figure is a sectional view of the manufacturing process of the second embodiment of the present invention. 101.201... Single crystal silicon substrate, 102...
Silicon oxide, 202... Insulating film, 103, 203...
- Open hole, 104.207...aluminum, 204...titanium, 205...titanium nitride, 206...titanium silicide. Agent Patent Attorney Uchihara 2 Town. Nishiki 1 figure (α) (shi) <C) Edge 2 figure
Claims (1)
線体との接続点の絶縁膜に開孔を形成する工程と、少な
くとも該開孔の口を完全に塞ぐ姿態で金属を形成する工
程と、前記金属形成工程より高い気圧の雰囲気において
該金属が流動する温度で熱処理する工程とを有すること
を特徴とする半導体装置の製造方法。A process of forming an opening in an insulating film at a connection point between an active element, a passive element, and a wiring body formed on one main surface of a semiconductor substrate, and a process of forming a metal in such a manner as to completely close at least the opening of the opening. and a step of heat-treating at a temperature at which the metal flows in an atmosphere with a higher pressure than the metal forming step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15437686A JPS639925A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15437686A JPS639925A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639925A true JPS639925A (en) | 1988-01-16 |
Family
ID=15582800
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15437686A Pending JPS639925A (en) | 1986-06-30 | 1986-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639925A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0226052A (en) * | 1988-07-14 | 1990-01-29 | Seiko Epson Corp | Semiconductor device |
| JPH04128101U (en) * | 1991-05-14 | 1992-11-24 | ナシヨナル住宅産業株式会社 | cutting equipment |
| US5221853A (en) * | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
| US5250467A (en) * | 1991-03-29 | 1993-10-05 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
| US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| US5877086A (en) * | 1996-07-12 | 1999-03-02 | Applied Materials, Inc. | Metal planarization using a CVD wetting film |
| US5989623A (en) * | 1997-08-19 | 1999-11-23 | Applied Materials, Inc. | Dual damascene metallization |
| US6001420A (en) * | 1996-09-23 | 1999-12-14 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
| US6066358A (en) * | 1995-11-21 | 2000-05-23 | Applied Materials, Inc. | Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer |
| US6139905A (en) * | 1997-04-11 | 2000-10-31 | Applied Materials, Inc. | Integrated CVD/PVD Al planarization using ultra-thin nucleation layers |
| US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
| US6207558B1 (en) | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
| US6458684B1 (en) | 1995-11-21 | 2002-10-01 | Applied Materials, Inc. | Single step process for blanket-selective CVD aluminum deposition |
| US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
| US6656831B1 (en) | 2000-01-26 | 2003-12-02 | Applied Materials, Inc. | Plasma-enhanced chemical vapor deposition of a metal nitride layer |
| US6726776B1 (en) | 1995-11-21 | 2004-04-27 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104165A (en) * | 1985-10-31 | 1987-05-14 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-06-30 JP JP15437686A patent/JPS639925A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104165A (en) * | 1985-10-31 | 1987-05-14 | Toshiba Corp | Semiconductor device |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174319A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Manufacture of semiconductor device |
| JPH0226052A (en) * | 1988-07-14 | 1990-01-29 | Seiko Epson Corp | Semiconductor device |
| US5221853A (en) * | 1989-01-06 | 1993-06-22 | International Business Machines Corporation | MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region |
| US5250467A (en) * | 1991-03-29 | 1993-10-05 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
| US5356835A (en) * | 1991-03-29 | 1994-10-18 | Applied Materials, Inc. | Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer |
| JPH04128101U (en) * | 1991-05-14 | 1992-11-24 | ナシヨナル住宅産業株式会社 | cutting equipment |
| US6066358A (en) * | 1995-11-21 | 2000-05-23 | Applied Materials, Inc. | Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer |
| US6355560B1 (en) | 1995-11-21 | 2002-03-12 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| US6726776B1 (en) | 1995-11-21 | 2004-04-27 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| US5877087A (en) * | 1995-11-21 | 1999-03-02 | Applied Materials, Inc. | Low temperature integrated metallization process and apparatus |
| US6458684B1 (en) | 1995-11-21 | 2002-10-01 | Applied Materials, Inc. | Single step process for blanket-selective CVD aluminum deposition |
| US5877086A (en) * | 1996-07-12 | 1999-03-02 | Applied Materials, Inc. | Metal planarization using a CVD wetting film |
| US6001420A (en) * | 1996-09-23 | 1999-12-14 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
| US6430458B1 (en) | 1996-09-23 | 2002-08-06 | Applied Materials, Inc. | Semi-selective chemical vapor deposition |
| US6537905B1 (en) | 1996-12-30 | 2003-03-25 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
| US7112528B2 (en) | 1996-12-30 | 2006-09-26 | Applied Materials, Inc. | Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug |
| US6139697A (en) * | 1997-01-31 | 2000-10-31 | Applied Materials, Inc. | Low temperature integrated via and trench fill process and apparatus |
| US6139905A (en) * | 1997-04-11 | 2000-10-31 | Applied Materials, Inc. | Integrated CVD/PVD Al planarization using ultra-thin nucleation layers |
| US6207222B1 (en) | 1997-08-19 | 2001-03-27 | Applied Materials, Inc. | Dual damascene metallization |
| US5989623A (en) * | 1997-08-19 | 1999-11-23 | Applied Materials, Inc. | Dual damascene metallization |
| US6368880B2 (en) * | 1999-10-21 | 2002-04-09 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
| US6207558B1 (en) | 1999-10-21 | 2001-03-27 | Applied Materials, Inc. | Barrier applications for aluminum planarization |
| US6656831B1 (en) | 2000-01-26 | 2003-12-02 | Applied Materials, Inc. | Plasma-enhanced chemical vapor deposition of a metal nitride layer |
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