JPS62104165A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPS62104165A
JPS62104165A JP24432585A JP24432585A JPS62104165A JP S62104165 A JPS62104165 A JP S62104165A JP 24432585 A JP24432585 A JP 24432585A JP 24432585 A JP24432585 A JP 24432585A JP S62104165 A JPS62104165 A JP S62104165A
Authority
JP
Japan
Prior art keywords
film
alloy
contact hole
tin
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24432585A
Other languages
Japanese (ja)
Other versions
JPH0719885B2 (en
Inventor
Katsuya Okumura
勝弥 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60244325A priority Critical patent/JPH0719885B2/en
Publication of JPS62104165A publication Critical patent/JPS62104165A/en
Publication of JPH0719885B2 publication Critical patent/JPH0719885B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To take out highly reliable electrodes even from minute contact holes, by providing a barrier layer at the bottom part of each contact hole, which is provided in an insulating film formed on a semiconductor substrate, and fusing and burying Al alloy in the contact hole. CONSTITUTION:On an Si substrate 11, and SiO2 film 12 is formed. Contact holes 13 are selectively formed. A TiN film 14 as a barrier layer and a 30% Mg-Al alloy film 15 are sequentially deposited. The Mg-Al alloy film 15 and the TiN film 14 are patterned so that the films remain only in and around the contact holes 13. Thus an Mg-Al alloy pattern 16 and a TiN pattern 17 are formed. When, the Si substrate undergoes heat treatment at 510 deg.C, the Mg-Al alloy pattern 16 is fused, and the contact holes 13 are buried with an Mg-Al alloy body 18. Then, a Tin film 19 is deposited on the SiO2 film 12 including the Mg-Al alloy body 18. Thereafter, an Al film is deposited on the entire surface of the film 19. Patterning is performed, and an Al wiring 20 is formed.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関し、特に微小なコンタクトホ
ールで信頼性の高い電極の取出しが可能な半導体装置に
係わる。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which electrodes can be reliably extracted through a minute contact hole.

〔発明の技術的背景〕[Technical background of the invention]

半導体装置においては、コンタクトホールを介して電極
の取出しがなされている。こうした電極の取出しは、従
来、コンタクトホールを形成した優、アルミニウム膜を
形成し、該アルミニウム膜を配線として用いると同時に
、電極取出しとしても使用していた。
In semiconductor devices, electrodes are taken out through contact holes. Conventionally, to take out such an electrode, an aluminum film with a contact hole formed therein has been formed, and the aluminum film has been used as a wiring and at the same time as an electrode lead out.

〔背景技術の問題点〕[Problems with background technology]

ところで、半導体素子の高密度化に伴ってコンタクトホ
ールも縮小化されるが、コンタクトホールの深さは略一
定である。このため、アルミニウム膜が該コンタクトホ
ール内に被着されにくくなり、特にコンタクトホール側
壁での被着率(ステップ力バレイジ)が悪化するという
問題があった。
Incidentally, as the density of semiconductor devices increases, the contact holes are also reduced in size, but the depth of the contact holes remains approximately constant. For this reason, there is a problem in that the aluminum film is difficult to be deposited inside the contact hole, and the deposition rate (step force balayage) particularly on the side wall of the contact hole is deteriorated.

これについて、第4図を参照して詳細に説明する。This will be explained in detail with reference to FIG.

図中の1は、シリコン基板であり、この基板1上にはシ
リコン酸化lI2が形成されている。この酸化膜2には
、コンタクトホール3a、3b・・・が開孔されている
。コンタクトホール3aは4μmx4μm1コンタクト
ホール3bは1μmx1μmの大きさである。こうした
開口寸法の異なるコンタクトホール3a、3bを有する
シリコン酸化膜2上にスパッタリング技術により厚さ1
μmのアルミニウム膜4を堆積すると、開口寸法の大き
いコンタクトホール3aではアルミニウム膜4のステッ
プ力バレイジが80%以上で良好であるが、開口寸法の
小さいコンタクトホール3bでは10%にも満たない。
1 in the figure is a silicon substrate, and silicon oxide lI2 is formed on this substrate 1. This oxide film 2 has contact holes 3a, 3b, . . . formed therein. The contact hole 3a has a size of 4 μm×4 μm, and the contact hole 3b has a size of 1 μm×1 μm. The silicon oxide film 2 having the contact holes 3a and 3b with different opening sizes is coated with a sputtering technique to form a 1-thick film.
When an aluminum film 4 of μm thickness is deposited, the step force burrage of the aluminum film 4 is good at 80% or more in the contact hole 3a with a large opening size, but it is less than 10% in the contact hole 3b with a small opening size.

その結果、コンタクトホール3bでの電極取出しは信頼
性が著・しく低下する。
As a result, the reliability of taking out the electrode through the contact hole 3b is significantly reduced.

〔発明の目的〕[Purpose of the invention]

本発明は、微小なコンタクトホールでも信頼性の高い電
極を取出すことが可能な構造を有する半導体装置を提供
しようとするものである。
The present invention aims to provide a semiconductor device having a structure in which highly reliable electrodes can be taken out even through minute contact holes.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板上に設けられた絶縁膜と、この絶
縁膜に開孔されたコンタクトホールと、このコンタクト
ホールの少なくとも底部に設けられたバリア層と、前記
コンタクトホール内に溶融により埋込まれたアルミニウ
ム合金とを具備したことを特徴とするものである。かか
る本発明によれば、既述の如く微小なコンタクトホール
でも信頼性の高い電極を取出すことが可能な構造を有す
る半導体装置を得ることができる。
The present invention includes an insulating film provided on a semiconductor substrate, a contact hole formed in the insulating film, a barrier layer provided at least at the bottom of the contact hole, and a barrier layer embedded in the contact hole by melting. The invention is characterized by comprising an aluminum alloy made of aluminum alloy. According to the present invention, as described above, it is possible to obtain a semiconductor device having a structure in which highly reliable electrodes can be taken out even through a minute contact hole.

上記バリア層としては、高融点金属の窒化物等を用いる
ことができ、特にTiNが好適である。
As the barrier layer, a nitride of a high melting point metal or the like can be used, and TiN is particularly suitable.

上記アルミニウム合金としては、純アルミニウムに比べ
て極めて低温度での溶融が可能なMQを含むAR金合金
適している。かかるAn−Ma金合金、含有するMOに
よる^抵抗化等の電極取出しとして悪影響を及ぼさない
範囲である35重量%において、溶融温度が最も低くな
る(約450℃)ため、Mg含有量が35重急%以下の
△2合金を用いることが望まC叶′特にMg含有量が2
0重量%(溶融温度約550℃)〜35重量%の範囲に
することが好ましい。
As the aluminum alloy, an AR gold alloy containing MQ, which can be melted at a much lower temperature than pure aluminum, is suitable. In this An-Ma gold alloy, the melting temperature is the lowest (approximately 450°C) at 35% by weight, which is a range that does not have any adverse effects on electrode extraction such as resistance due to the MO contained. It is preferable to use a △2 alloy with an Mg content of less than 2%.
The range is preferably from 0% by weight (melting temperature about 550°C) to 35% by weight.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面に示す製造工程を併記して
詳細に説明する。
Hereinafter, embodiments of the present invention will be described in detail together with manufacturing steps shown in the drawings.

実施例1 まず、半導体素子(図示せず)が形成されたシリコン基
板11上に厚さ約1μmのシリコン酸化膜12を形成し
た後、該酸化1112に例えば開口寸法が1μm×1μ
mのコンタクトホール13をフォトエツチング技術によ
り選択的に形成した。
Example 1 First, a silicon oxide film 12 with a thickness of about 1 μm is formed on a silicon substrate 11 on which a semiconductor element (not shown) is formed, and then a silicon oxide film 12 with an opening size of, for example, 1 μm×1 μm is formed in the oxide film 1112.
A contact hole 13 of m in diameter was selectively formed by photoetching technology.

つづいて、コンタクトホール13を含むシリコン酸化膜
12上に厚さ約1000人のバリア層としてのTiNl
l114を堆積した後、全面にスパッタリングにより厚
さ8000人の30%Mg−へ2合金膜15を堆積した
く第1図(a)図示)。この30%MO−A℃合金の融
点は、500℃である。
Next, a TiNl barrier layer with a thickness of approximately 1000 nm is formed on the silicon oxide film 12 including the contact hole 13.
After depositing 114, a 30% Mg-2 alloy film 15 is deposited on the entire surface by sputtering to a thickness of 8,000 mm (as shown in FIG. 1(a)). The melting point of this 30% MO-A°C alloy is 500°C.

次いで、前記MO−AR合金膜15とTiN膜14を、
コンタクトホール13及びその周辺にのみ残存するよう
にバターニングしてMO−AR合金パターン16及びT
iNパターン17を形成した(同図(b)図示)。つづ
いて、シリコン基板11をMO−AJ2合金の融点より
少し高い510℃で熱処理した。この時、Mg−Afi
合金パターン16が溶融し、その後の冷却によりコンタ
クトホール13がMO−AQ合金体18で埋込まれた(
同図(C)図示)。また、コンタクトホール13の内面
にはTiNパターン17が形成されているため、30%
Mg−A/!、合金パターン16の溶融時にそのA℃と
シリコン基板11とが反応するのを阻止し、コンタクト
ホール13下の基板11表面にA2の突複は等が発生す
るのを防止される。
Next, the MO-AR alloy film 15 and the TiN film 14 are
The MO-AR alloy pattern 16 and T are patterned so that they remain only in the contact hole 13 and its surroundings.
An iN pattern 17 was formed (as shown in FIG. 3(b)). Subsequently, the silicon substrate 11 was heat-treated at 510° C., which is slightly higher than the melting point of the MO-AJ2 alloy. At this time, Mg-Afi
The alloy pattern 16 was melted, and the contact hole 13 was filled with the MO-AQ alloy body 18 by subsequent cooling (
Figure (C) shown). Furthermore, since the TiN pattern 17 is formed on the inner surface of the contact hole 13, 30%
Mg-A/! When the alloy pattern 16 is melted, the reaction between the A° C. and the silicon substrate 11 is prevented, and the occurrence of A2 protrusions, etc. on the surface of the substrate 11 under the contact hole 13 is prevented.

次いで、MO−AR合金体18を含むシリコン酸化膜1
2上にスパッタリングにより再度、厚さ1000人の1
Nl119を堆積した後、スパッタリングにより全面に
厚さ1μmのへ2膜を堆積し、パターニングしてへλ配
線20を形成したく同図(d)図示)。
Next, the silicon oxide film 1 containing the MO-AR alloy body 18 is
2 again by sputtering to a thickness of 1000 mm
After depositing Nl 119, a 1 μm thick film is deposited on the entire surface by sputtering, and patterned to form a λ wiring 20 (as shown in FIG. 2D).

本発明の半導体装置は、第1図(d)に示すようにシリ
コン基板11上に設けられたシリコン酸化膜12と、こ
の酸化膜12に開孔された微小なコンタクトホール13
と、このコンタクトホール13の少なくとも底部に設け
られたバリア層としてのTiNパターン17と、前記コ
ンタクトホール13内に溶融により埋込まれたMCI−
Aλ合金体18と、このMO−Aり合金体18にTiN
膿19を介して接続するA2配線2oとから構成されて
いる。
As shown in FIG. 1(d), the semiconductor device of the present invention includes a silicon oxide film 12 provided on a silicon substrate 11, and a minute contact hole 13 formed in this oxide film 12.
A TiN pattern 17 as a barrier layer provided at least at the bottom of the contact hole 13, and an MCI-
Aλ alloy body 18 and this MO-A alloy body 18 are coated with TiN.
It is composed of an A2 wiring 2o connected via a wire 19.

従って、微小なコンタクトホール13内に溶融により形
成されたMO−Ag合金体18が埋込まれ、このMQ−
Ag合金体18を介して基板表面の図示しない半導体素
子とA2配置!20を接続するため、従来のようなコン
タクトホールの微小化に伴う該コンタクトホールの側壁
部での段切れ等を防止できる。しかも、コンタクトホー
ル13の底部には低抵抗のTiNパターン(バリア層)
17が設けられ、かつコンタクトホール13の全体にM
g−A42合金体18が埋込まれているため、へ2配線
20をシリコン基板の図示しない半導体素子に低抵抗接
続できる。
Therefore, the MO-Ag alloy body 18 formed by melting is embedded in the minute contact hole 13, and this MQ-
A2 arrangement with a semiconductor element (not shown) on the substrate surface via the Ag alloy body 18! 20, it is possible to prevent breakage at the side wall of the contact hole, which is caused by the miniaturization of the contact hole as in the prior art. Moreover, a low resistance TiN pattern (barrier layer) is provided at the bottom of the contact hole 13.
17 is provided, and M is provided throughout the contact hole 13.
Since the g-A42 alloy body 18 is embedded, the H2 wiring 20 can be connected with low resistance to a semiconductor element (not shown) on the silicon substrate.

また、コンタクトホール13内に溶融により埋込むMC
J−A4合金体18は、純アルミニウムするため、該M
O−A℃合金の溶融時における基板11に形成された半
導体素子の熱影響を著しく低減できる。
In addition, the MC embedded in the contact hole 13 by melting
Since the J-A4 alloy body 18 is made of pure aluminum, the M
The thermal influence on the semiconductor element formed on the substrate 11 during melting of the O-A°C alloy can be significantly reduced.

更に、前記MO−Ag合金を溶融する温度において安定
で、かつ低抵抗のTiNパターン17をバリア層として
コンタクトホール13の少なくとも底部に設けているた
め、該MO−Ag合金の溶融時におけるAgと基板11
のシリコンとの反応を阻止し、Agの文法は等を防止で
きる。
Furthermore, since the TiN pattern 17, which is stable and has a low resistance at the temperature at which the MO-Ag alloy is melted, is provided as a barrier layer at least at the bottom of the contact hole 13, the Ag and the substrate will be separated when the MO-Ag alloy is melted. 11
reaction with silicon, Ag grammar, etc. can be prevented.

実施例2 まず、半導体素子(図示せず)が形成されたシリコン基
板11上に厚さ約1μmのシリコン酸化1112を形成
した後、該酸化膜12に例えば開口寸法が1μm×1μ
mのコンタクトホール13をフォトエツチング技術によ
り選択的に形成した。
Example 2 First, silicon oxide 1112 with a thickness of about 1 μm is formed on a silicon substrate 11 on which a semiconductor element (not shown) is formed, and then a silicon oxide film 1112 with an opening size of, for example, 1 μm×1 μm is formed in the oxide film 12.
A contact hole 13 of m in diameter was selectively formed by photoetching technology.

つづいて、タングステンを減圧CVD技術により堆積す
ることにより、コンタクトホール13の底部のみに厚さ
約1000人のバリア層としてのW膜21を形成した後
、コンタクトホール13内に直径0.7〜0.8umの
30%Mq−Affiからなる合金球22を挿入した(
第2図(a)図示)。
Subsequently, by depositing tungsten using low pressure CVD technology, a W film 21 as a barrier layer with a thickness of approximately 1000 mm is formed only at the bottom of the contact hole 13, and then a W film 21 with a diameter of 0.7 to 0.0 mm is formed in the contact hole 13. An alloy ball 22 made of 30% Mq-Affi of .8 um was inserted (
FIG. 2(a) diagram).

次いで、シリコン基板11をMg−Aρ金合金融点より
少し高い510℃で熱処理した。この時、MQ−AQの
合金球22が溶融し、その後の冷却によりコンタクトホ
ール13がMQ−A(1合金体18で埋込まれたく同図
(b)図示)。
Next, the silicon substrate 11 was heat-treated at 510° C., which is slightly higher than the Mg-Aρ gold alloy melting point. At this time, the MQ-AQ alloy ball 22 is melted, and the contact hole 13 is filled with the MQ-A (1 alloy body 18) by subsequent cooling, as shown in FIG.

しかして、本実施例2によれば実施例1のようにMQA
ffilli及びTiNIIIのパターニングを行なう
ことなく、コンタクトホール13内をMO=AQ、合金
体18で埋込むことができる。
According to the second embodiment, unlike the first embodiment, MQA
The inside of the contact hole 13 can be filled with MO=AQ and the alloy body 18 without patterning ffilli and TiNIII.

実施例3 まず、半導体素子(図示せず)が形成されたシリコン基
板11上に厚さ約1μmのシリコン酸化膜12を形成し
た後、該酸化11112に例えば開口寸法が1μmx1
μmのコンタクトホール13をフォトエツチング技術に
より選択的に形成した。
Example 3 First, a silicon oxide film 12 with a thickness of about 1 μm is formed on a silicon substrate 11 on which a semiconductor element (not shown) is formed, and then a silicon oxide film 12 with an opening size of, for example, 1 μm×1 is formed in the oxide film 11112.
A contact hole 13 with a diameter of .mu.m was selectively formed using a photoetching technique.

つづいて、コンタクトホール13を含むシリコン酸化膜
12上に厚さ約1000人のバリア層としてのTiN膜
14を堆積した後、全面にスパッタリングにより厚さ1
.5μmの30%Mg−Aff合金g!15を堆積した
(第3図(a)図示)。この時、コンタクトホール13
内の30%MQ−に加熱しながら、前記fvl−Aff
i合金膜15上に厚さ0.5μmの純ARをスパッタリ
ングした。
Subsequently, after depositing a TiN film 14 as a barrier layer with a thickness of about 1000 on the silicon oxide film 12 including the contact hole 13, a TiN film 14 with a thickness of about 1000 is deposited on the entire surface by sputtering.
.. 5 μm 30% Mg-Aff alloy g! 15 was deposited (as shown in FIG. 3(a)). At this time, contact hole 13
While heating to 30% MQ- in the fvl-Aff
Pure AR was sputtered onto the i-alloy film 15 to a thickness of 0.5 μm.

この時、MO−Affi合金膜が溶融して前記空洞部2
3が消滅してコンタクトホール13内がMQ−A2合金
膜で埋込まれた。同時に、純Afill124が堆積さ
れると共に、溶融したM(ll−A2合金膜中のMOが
純AR1I!24に拡散してMQ含有量が20%のMQ
−AI2合金穫25となった(同図(b)図示)。この
MO−A2合金11!25の融点は550℃であった。
At this time, the MO-Affi alloy film melts and the cavity 2
3 disappeared and the inside of the contact hole 13 was filled with the MQ-A2 alloy film. At the same time, pure Afill124 is deposited, and the molten M(MO in the ll-A2 alloy film diffuses into pure AR1I!24, resulting in MQ with an MQ content of 20%.
-AI2 alloy yield was 25 (as shown in Figure (b)). The melting point of this MO-A2 alloy 11!25 was 550°C.

次いで、シリコン酸化膜12上の純A2膜24及びMQ
−Affi合金膜25をエッチバックして除去し、更に
シリコン酸化l1112上のTiNIII4を除去して
コンタクトホール13の内面のみにT + Nl114
−を残存させると共に、同コンタクトホール13内にM
O含有量が20%のtvl−Affi合金体26を埋込
んだ(同図(C)図示)。
Next, the pure A2 film 24 and the MQ film on the silicon oxide film 12 are
- The Affi alloy film 25 is etched back and removed, and the TiNIII4 on the silicon oxide l1112 is removed to form T + Nl114 only on the inner surface of the contact hole 13.
- remains in the same contact hole 13, and M
A tvl-Affi alloy body 26 with an O content of 20% was embedded (as shown in the same figure (C)).

つづいて、MCI−A2合金体26を含むシリコン酸化
l!12上にスパッタリングにより厚さ1μmのへ2膜
を堆積し、パターニングして前記MO−AR合金体26
と直接接続するA2配線20を形成した(同図(d)図
示)。
Next, silicon oxide l containing the MCI-A2 alloy body 26! A 1 μm thick film is deposited on the MO-AR alloy body 26 by sputtering and patterned.
An A2 wiring 20 was formed to be directly connected to the A2 wiring 20 (as shown in FIG. 2(d)).

しかして、本実施例3によればMCJ−Aj2合金g1
15の溶融、コンタクトホール13内への埋込み時に、
該Mg−Aff合金膜15上に純A2膜24を堆積する
ため、MにI−AR合金膜中のMgが純A2膜24に拡
散してMOの含有量の低い(例えばMCI : 20%
)、つまり融点が初期堆積時より高いMg−AR合金膜
25となり、その後のエッチバックによりコンタクトホ
ール13内にMg含有量が20%のMO−Affi合金
体26を埋込むことができる。従って、コンタクトホー
ル13内に埋込まれたMO−Affi合金体26は前述
した実施例1のMa−A1合金体18に比べて融点が高
いため、配線20の形成後の熱処理温度を実施例1より
高くできる。また、MO−A℃合金体26のMQ含有量
を低減でき、かつ融点を高くできるため、該MQ−△λ
合金体26にA2配線20を直接設けても、該配線20
の形成後の熱処理時においてMgのA2配線20への拡
散を抑制でき、ひいては実施例1のようなバリア層とし
のTiN膜19の形成を省略できる。
According to Example 3, MCJ-Aj2 alloy g1
When melting 15 and embedding it in the contact hole 13,
Since the pure A2 film 24 is deposited on the Mg-Aff alloy film 15, Mg in the I-AR alloy film is diffused into the pure A2 film 24, resulting in a low MO content (for example, MCI: 20%).
), that is, the Mg-AR alloy film 25 has a melting point higher than that at the time of initial deposition, and the contact hole 13 can be filled with the MO-Affi alloy body 26 having an Mg content of 20% by subsequent etchback. Therefore, since the MO-Affi alloy body 26 embedded in the contact hole 13 has a higher melting point than the Ma-A1 alloy body 18 of Example 1 described above, the heat treatment temperature after forming the wiring 20 was set as in Example 1. Can be made higher. Moreover, since the MQ content of the MO-A°C alloy body 26 can be reduced and the melting point can be increased, the MQ-Δλ
Even if the A2 wiring 20 is directly provided on the alloy body 26, the wiring 20
It is possible to suppress the diffusion of Mg into the A2 wiring 20 during the heat treatment after the formation of the TiN film 19 as in the first embodiment.

なお、上記実施例2ではコンタクトホールにMQ−A(
lからなる合金球を挿入した後、熱処理を行なって該合
金球を溶融したが、合金球の代わりに他の形状の塊状合
金をコンタクトホール内に挿入してもよい。
In addition, in the above-mentioned Example 2, MQ-A (
After inserting the alloy ball made of 1, the alloy ball was melted by heat treatment, but instead of the alloy ball, a lump alloy having another shape may be inserted into the contact hole.

上記実施例3では、MQ−AM合金腹中のMO含有量を
低減するために、該Mq−An合金膜の堆積にひきつづ
いて純AQMをスパッタリングする際、基板温度を同M
l;l−Aλ合金膜の融点より少し高い温度に設定する
方法を採用したが、これに限定されない。例えば、Mg
−Affi合金膜上に純A2膜を堆積した後、基板を大
気中に取出し、該Mg−An合金膜の融点より少し高い
温度で熱処理してMg−A42合金膜の溶融、該合金中
のMQの純Aβ膜への拡散、これによるMg含有量の低
減を行なってもよい。
In the above Example 3, in order to reduce the MO content in the MQ-AM alloy film, when sputtering pure AQM subsequent to the deposition of the Mq-An alloy film, the substrate temperature was kept at the same MQ.
Although a method of setting the temperature slightly higher than the melting point of the l;l-Aλ alloy film was adopted, the method is not limited thereto. For example, Mg
- After depositing a pure A2 film on the Affi alloy film, the substrate is taken out into the atmosphere and heat treated at a temperature slightly higher than the melting point of the Mg-An alloy film to melt the Mg-A42 alloy film and MQ in the alloy. may be diffused into the pure Aβ film, thereby reducing the Mg content.

上記実施例3では、M(J−Affi合金膜上にスパッ
タリングにより純AQ膜を堆積したが、該合金膜をバタ
ーニングしてコンタクトホール及びのその周辺に残存さ
せた後、スパッタリングにより純Aj2膜を堆積しても
よい。
In the above Example 3, a pure AQ film was deposited by sputtering on the M(J-Affi alloy film, but after the alloy film was patterned and left in the contact hole and its surroundings, a pure Aj2 film was deposited by sputtering. may be deposited.

上記実施例3において、純AI2膜のスパッタリング中
の温度、膜厚及び時間を変えることによって、純AR膜
下のtvl−A2合金膜のM9含有量を任意に低減でき
る。
In Example 3, the M9 content of the tvl-A2 alloy film under the pure AR film can be arbitrarily reduced by changing the temperature, film thickness, and time during sputtering of the pure AI2 film.

上記各実施例では、絶縁膜としてシリコン酸化膜を使用
したが、SiN膜等の他の絶縁膜を使用してもよい。
In each of the above embodiments, a silicon oxide film is used as the insulating film, but other insulating films such as a SiN film may also be used.

上記各実施例では、半導体基板の半導体素子とのへ2配
線とのコンタクトを行なう場合について説明したが、第
1層配線と第2層配線とを接続する等の多層配線構造に
も同様に適用できる。
In each of the above embodiments, a case has been described in which contact is made with two wirings to a semiconductor element on a semiconductor substrate, but the same applies to a multilayer wiring structure such as connecting a first layer wiring and a second layer wiring. can.

(発明の効果) 以上詳述した如く、本発明によれば微小なコンタクトホ
ールでも信頼性の高い電極を取出すことが可能な高信頼
性、高集積度の半導体装置を提供できる。
(Effects of the Invention) As detailed above, according to the present invention, it is possible to provide a highly reliable and highly integrated semiconductor device from which highly reliable electrodes can be taken out even through minute contact holes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例1における半導
体装置の製造工程を示す断面図、第2図(a)、(b)
は本発明の実施例2におけるMgる半導体装置の製造工
程を示す断面図、第4図は従来の半導体装置を示す断面
図である。 11・・・シリコン基板、12・・・シリコン酸化膜、
13・・・コンタクトホール、14・・・TiNII!
、15.25・・・1vl−Affi合金膜、18.2
6・・・MQ−A2合金体、20・・・A2配線、21
・・・WIl!i!、22・・・fvl−Affiから
なる合金球、24・・・純A fil。 出願人代理人 弁理士  鈴江武彦 (a) (b) (c) 第1図 (a) (b) 第2図 第3図 第3図 第4図
FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process of a semiconductor device in Example 1 of the present invention, and FIGS. 2(a) and (b)
FIG. 4 is a cross-sectional view showing the manufacturing process of a Mg semiconductor device in Example 2 of the present invention, and FIG. 4 is a cross-sectional view showing a conventional semiconductor device. 11... Silicon substrate, 12... Silicon oxide film,
13...Contact hole, 14...TiNII!
, 15.25...1vl-Affi alloy film, 18.2
6...MQ-A2 alloy body, 20...A2 wiring, 21
...WIl! i! , 22... alloy ball made of fvl-Affi, 24... pure A fil. Applicant's agent Patent attorney Takehiko Suzue (a) (b) (c) Figure 1 (a) (b) Figure 2 Figure 3 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)、半導体基板上に設けられた絶縁膜と、この絶縁
膜に開孔されたコンタクトホールと、このコンタクトホ
ールの少なくとも底部に設けられたバリア層と、前記コ
ンタクトホール内に溶融により埋込まれたアルミニウム
合金とを具備したことを特徴とする半導体装置。
(1) An insulating film provided on a semiconductor substrate, a contact hole formed in this insulating film, a barrier layer provided at least at the bottom of this contact hole, and a layer embedded in the contact hole by melting. 1. A semiconductor device comprising: an aluminum alloy made of aluminum.
(2)、バリア層が少なくとも高融点金属の窒化物を含
む膜からなり、かつアルミニウム合金がマグネシウムを
含んだものからなることを特徴とする特許請求の範囲第
1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the barrier layer is made of a film containing at least a nitride of a high-melting point metal, and the aluminum alloy contains magnesium.
JP60244325A 1985-10-31 1985-10-31 Method for manufacturing semiconductor device Expired - Lifetime JPH0719885B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60244325A JPH0719885B2 (en) 1985-10-31 1985-10-31 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60244325A JPH0719885B2 (en) 1985-10-31 1985-10-31 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS62104165A true JPS62104165A (en) 1987-05-14
JPH0719885B2 JPH0719885B2 (en) 1995-03-06

Family

ID=17117032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60244325A Expired - Lifetime JPH0719885B2 (en) 1985-10-31 1985-10-31 Method for manufacturing semiconductor device

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Country Link
JP (1) JPH0719885B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639925A (en) * 1986-06-30 1988-01-16 Nec Corp Manufacture of semiconductor device
JPS63166246A (en) * 1986-12-27 1988-07-09 Nec Corp Interlayer connection of semiconductor device
JPS6476736A (en) * 1987-09-17 1989-03-22 Tokyo Electron Ltd Manufacture of semiconductor device
JPH01264258A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Semiconductor device and its manufacture
JPH02239665A (en) * 1989-03-14 1990-09-21 Toshiba Corp Semiconductor device and manufacture thereof
JPH04209572A (en) * 1990-12-07 1992-07-30 Nec Corp Semiconductor device
JPH08330427A (en) * 1995-05-27 1996-12-13 Lg Semicon Co Ltd Wiring formation of semiconductor element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4810897U (en) * 1971-06-04 1973-02-07
JPS50159259A (en) * 1974-06-12 1975-12-23
JPS609159A (en) * 1983-06-29 1985-01-18 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4810897U (en) * 1971-06-04 1973-02-07
JPS50159259A (en) * 1974-06-12 1975-12-23
JPS609159A (en) * 1983-06-29 1985-01-18 Fujitsu Ltd Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639925A (en) * 1986-06-30 1988-01-16 Nec Corp Manufacture of semiconductor device
JPS63166246A (en) * 1986-12-27 1988-07-09 Nec Corp Interlayer connection of semiconductor device
JPS6476736A (en) * 1987-09-17 1989-03-22 Tokyo Electron Ltd Manufacture of semiconductor device
JPH01264258A (en) * 1988-04-15 1989-10-20 Hitachi Ltd Semiconductor device and its manufacture
JPH02239665A (en) * 1989-03-14 1990-09-21 Toshiba Corp Semiconductor device and manufacture thereof
JPH04209572A (en) * 1990-12-07 1992-07-30 Nec Corp Semiconductor device
JPH08330427A (en) * 1995-05-27 1996-12-13 Lg Semicon Co Ltd Wiring formation of semiconductor element

Also Published As

Publication number Publication date
JPH0719885B2 (en) 1995-03-06

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