JPH06163720A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to obtain a highly reliable, low-resistance fine wiring, which is resistant to stress-migration by providing a low-melting-point metal layer such as Pb so as to fill the recess part around a connecting hole on a wiring layer comprising Al or Al alloy, and smoothing the surface of the wiring layer. CONSTITUTION:A low-melting-point metal layer 22 such as Pb is formed so as to fill the recess part around a connecting hole on a wiring layer 18. Therefore, the thickness of the wiring around the connecting hole becomes sufficient, and stress-migration resistance is further improved. An Al or Al alloy layer 24 is formed so as to cover the low-melting-point metal layer 22 on a wiring layer 26 by low-temperature sputtering. Then, the flatness and the smoothness on the upper surface of the wiring layer 24 become excellent, and the wiring resistance is decreased. Furthermore, the Al or Al alloy layer 24 is formed in small grain size, and the possibility of the occurrence of a bump structure is rare. Thus the stress-migration resistance is further improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an L having fine wiring.
The present invention relates to a semiconductor device such as SI and the manufacturing method thereof, and in particular, the stress migration resistance is improved by filling a recess formed in a wiring layer around a connection hole with a low melting point metal such as lead (Pb).

[0002]

2. Description of the Related Art Conventionally, a method shown in FIGS. 6 to 8 has been known as a method for forming fine wiring of an LSI or the like.

In FIGS. 6 to 8, after an impurity-doped region 13 of N ⁺ type or the like is formed on the surface of the semiconductor substrate 10,
The insulating film 14 is formed. Then, the connection hole 1 is formed in the insulating film 14.
After forming 4a and 14b, a barrier metal layer 16 is deposited on the upper surface of the substrate, and a wiring material layer 18 made of Al is formed thereon by a high temperature sputtering process. The high temperature sputtering process
Sputtering is performed while maintaining the substrate at a temperature of 400 ° C. or higher and a temperature lower than 660 ° C. (Al melting point) (for example, 500 to 550 ° C.), and Al is formed so as to flow into a fine connection hole and fill it. It After that, the laminated structure of the barrier metal layer 16 and the wiring material layer 18 is patterned to obtain the wiring layer 20.

[0004]

According to the above-mentioned conventional method, the wiring material layer 18 becomes thinner than the desired thickness t around the connection holes 14a and 14b. In particular, as shown in FIG. 9, in the fine wiring layer 20 having a width of about 1.0 [μm], A
The region 18S in which the film thickness is 1/2 or less than t is the connection hole 14
It is formed so as to spread around a and 14b. The reduction in wiring thickness causes an increase in wiring resistance.

FIG. 10 shows a wiring layer 2 having a width of 1.0 [μm].
2 shows an example of Al grain arrangement in No. 0.
Each of the plurality of Al grains G _{1 to} G ₄ had a size of about 10 μm when deposited by high temperature sputtering. When the grain size is large as described above, a bamboo structure is likely to appear at a portion where a grain boundary GB crosses the wiring (for example, a boundary between Al grains G ₁ and G ₂ ).

FIG. 11 shows a slit-shaped void V due to stress migration. Such a void is generated from a grain boundary GB having a bamboo structure that crosses a wiring. The stress migration resistance is lower as the Al film thickness is smaller. That is, when n = 3 to 5, the relationship of (stress migration resistance) ∝ (Al film thickness) ⁿ is widely known.

Therefore, the thin region 18S of FIG.
If there is a grain boundary with a bamboo structure in, the resistance to stress migration is reduced and disconnection failure is likely to occur. Further, even if the wire is not broken, the wiring resistance increases if the slit-shaped void V is generated on the barrier metal layer 16 as shown in FIG.

By the way, there has been proposed a method of depositing an Al alloy on the wiring material layer 18 by a low temperature sputtering process in order to compensate for the thinning of the Al film thickness around the connection hole (for example, Japanese Unexamined Patent Publication No. Hei 4). -61118). In the low temperature sputtering process, the substrate is processed at a relatively low temperature of 350 ° C. or lower (for example, 20
Since the sputtering is performed while maintaining the temperature at 0 to 250 ° C., an Al alloy film having a desired thickness and good smoothness can be obtained.

However, even if the low temperature sputtering process is added, as shown by the chain line 18 'in FIG.
However, the increase in thickness around the connection hole was not sufficient, and the stress migration resistance could not be improved so much.

An object of the present invention is to provide a semiconductor device having fine wiring with low resistance and high reliability, and a manufacturing method thereof.

[0011]

A semiconductor device according to the present invention comprises a substrate having a contacted portion, and an insulating film formed on the substrate to cover the contacted portion. And a wiring layer made of Al or an Al alloy formed on the insulating film so as to be connected to the contacted portion via the connection hole. And a metal layer provided on the wiring layer so as to fill the recess, which is lower than the material forming the wiring layer. And those having a melting point.

In such a structure, the wiring layer is
It can be formed by a high temperature sputtering process. Also,
The metal layer can be formed by depositing a metal such as Pb on the wiring layer and heat-treating it. It is preferable that an Al or Al alloy layer is formed on the wiring layer by low temperature sputtering to cover the metal layer.

[0013]

According to the structure of the present invention, since the low melting point metal layer is provided on the wiring layer so as to fill the concave portion around the connection hole, the wiring thickness becomes sufficient around the connection hole and the stress migration resistance is significantly improved. Can be improved.

When the Al or Al alloy layer is formed on the wiring layer by the low temperature sputtering process so as to cover the low melting point metal layer as described above, the flatness or smoothness of the upper surface of the wiring layer is improved and the wiring resistance is improved. Will be reduced. Moreover, since the Al or Al alloy layer is formed with a small grain size and rarely has a bamboo structure, the stress migration resistance is further improved.

[0015]

1 to 5 show a wiring forming method according to an embodiment of the present invention. Steps (1) to
(5) will be sequentially described.

(1) After a field insulating film 12 of silicon oxide or the like is formed on the surface of a semiconductor substrate 10 of silicon or the like by a selective oxidation process, an impurity doping process of N ⁺ type or the like is performed by an impurity doping process using the insulating film 12 as a mask. Region 13 is formed. Then, the insulating film 14 is formed flat on the upper surface of the substrate. The insulating film 14 can be formed by, for example, appropriately combining a deposited insulating film by a CVD method or the like and a coated insulating film by a spin coating method or the like. After that, the contact holes 14a, 1a reaching the surface of the impurity-doped region 13 are formed in the insulating film 14 by a dry etching process using the resist layer as a mask.
4b and 14c are formed.

(2) Ti is deposited on the upper surface of the substrate by the sputtering process.
And TiN are sequentially deposited to form a barrier metal layer 16 having a thickness of about 100 [nm]. Then, the substrate temperature is set to 5
Al alloy (for example, Al-Si
By performing a high-temperature sputtering process of (Cu or the like), a wiring material layer 18 made of an Al alloy having a thickness T = 700 [nm] is formed on the upper surface of the substrate. The wiring material layer 18 becomes thin around the connection hole to form a recess.

(3) After depositing Pb (melting point 327.4 ° C.) on the upper surface of the substrate by sputtering or vapor deposition, about 4
The deposited Pb is melted by heat treatment at 00 ° C. to form the metal layer 22 that fills the concave portion around the connection hole. Then, the metal layer 22 is etched back until the thick portion of the wiring material layer 18 is exposed as shown by the broken line BL. As a result,
The metal layer 22 remains only in the concave portion around the connection hole, and the upper surface of the wiring material layer 18 is flattened.

(4) Set the substrate temperature to about 200 ° C.
The wiring material layer 24 made of an Al alloy having a thickness of 300 [nm] is formed on the upper surface of the substrate by performing a low temperature sputtering process of an alloy (for example, Al—Si—Cu).

(5) Then, the layers 16, 18, 22, 24 are dry-etched by using the resist layer as a mask.
The wiring layer 26 is obtained by patterning the laminated layer including.

According to the above-mentioned wiring forming method, the wiring material layer 1
By embedding the low melting point metal in the recess formed in FIG. 8, the coverage rate of the wiring is improved from 30 to 50% to 90 to 100%. Where (stress migration resistance)
∝ (wiring film thickness) ⁿ [where n = 3 to 5] improves stress migration resistance by at least one digit.

Since the wiring material layer 24 is formed by the low temperature sputtering process, the grain size is about 2 [μm]. Therefore, the probability of the bamboo structure is reduced, and the bamboo structure does not appear at the same place as the wiring material layer 18. As a result, the resistance to stress migration is further improved. Moreover, when the wiring material layer 24 is provided, the smoothness of the wiring surface is improved and the wiring resistance is reduced.

The present invention is not limited to the above embodiment, but may be applied to, for example, a second or higher layer wiring in a multilayer wiring.

[0024]

As described above, according to the present invention, Al
Alternatively, a low-melting-point metal layer such as Pb is provided on the wiring layer made of Al alloy so as to fill the concave portion around the connection hole, and the upper surface of the wiring layer is flattened. The effect that the fine wiring of can be realized can be obtained.

Further, when an Al or Al alloy layer is formed on the wiring layer through the low melting point metal layer by the low temperature sputtering process, the stress migration resistance and the smoothness of the wiring surface can be further improved and the wiring resistance can be further reduced. There is also an effect.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a connection hole forming step in a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a substrate cross-sectional view showing a wiring material depositing step following the step of FIG.

FIG. 3 is a substrate cross-sectional view showing a metal deposition / etchback process following the process of FIG.

FIG. 4 is a substrate cross-sectional view showing a wiring material depositing step following the step of FIG.

5 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

FIG. 6 is a top view for explaining a conventional wiring forming method.

7 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 8 is a cross-sectional view taken along the line B-B ′ of FIG.

FIG. 9 is a top view showing a region where a wiring material is thin around a connection hole.

FIG. 10 is a top view showing an Al grain arrangement of a wiring layer.

FIG. 11 is a substrate cross-sectional view showing slit-shaped voids between Al grains.

[Explanation of symbols]

10: semiconductor substrate, 12, 14: insulating film, 16: barrier metal layer, 18, 24: wiring material layer, 22: metal layer, 2
6: Wiring layer.

Claims (2)

[Claims] 1. A substrate having a contacted portion, an insulating film formed on the substrate to cover the contacted portion, and having a connection hole corresponding to the contacted portion; A wiring layer made of Al or an Al alloy formed on the film so as to be connected to the contacted portion through the connection hole, the recess being formed by reducing the thickness around the connection hole. A semiconductor device comprising: a formed layer; and a metal layer provided on the wiring layer so as to fill the recess and having a melting point lower than that of a material forming the wiring layer. 2. A step of forming an insulating film on a substrate so as to cover the contacted portion, a step of forming a connection hole corresponding to the contacted portion in the insulating film, and a step of forming the insulating film by a high temperature sputtering process. A step of forming a first wiring material layer made of Al or an Al alloy so as to fill the connection hole, and a metal having a melting point lower than that of the first wiring material layer on the first wiring material layer. A step of depositing and heat-treating to form a metal layer that fills the recesses around the connection hole; and a low-temperature sputter treatment to cover the metal layer on the first wiring material layer and form an Al or Al alloy. Forming a second wiring material layer, and patterning a stack including the first wiring material layer, the metal layer and the second wiring material layer to form the connection hole on the insulating film. Connected to the contacted part via Preparation of a semiconductor device and forming a wiring layer.