JP2914047B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a noble metal wiring having excellent flatness.

[0002]

2. Description of the Related Art Recent VLSIs have high performance, high density,
In order to respond to the demand for higher speed, multilayer wiring and miniaturization of wiring are rapidly progressing, and not only three-layer wiring products but also four-layer wiring products are about to be commercialized. Further, submicron wirings having a wiring width of less than 1.0 μm have been used in various places. Conventionally, from the viewpoint of good workability and low cost,
As a material, Al (aluminum) or an Al alloy is generally used. The manufacturing method will be briefly described below.

[0003] First, an Al film is deposited on the entire surface of a silicon wafer on which a device has been formed by a sputtering method.
The resist pattern is changed to Al by photolithography.
The Al film is formed on the film and the Al film is etched by RIE (reactive ion etching) using the resist film as a mask. Next, after removing the resist film, an interlayer insulating film is formed, a through hole is formed at a predetermined position, and a second-layer Al wiring is formed by the above-described method. By repeating this, a multilayer wiring has been realized.

Here, the interlayer insulating film is formed so as to flatten a step generated in the lower wiring and to prevent disconnection or the like of the upper wiring. For example, plasma chemical vapor deposition (PC
VD) grown oxide film (P.SiO ₂ ) and SOG
In general, a film obtained by combining a (spin-on-glass) film is used. Depending on the thickness of the Al wiring, several types of SOG films may be formed in multiple layers, or the flatness may be improved in combination with an etch-back method. This method is indispensable for the flattening of the upper wiring where the steps become severe. ing.

[0005]

The conventional Al wiring has a problem that the required reliability and performance cannot be satisfied. One of the major factors that determine the product life of an LSI is the life of the wiring.
Generally, the life of wiring is electromigration (E /
M), and is determined by a phenomenon called stress migration (S / M). The E / M and S / M resistance depends on the properties of the insulating film covering the wiring, but is basically caused by the wiring material itself. Al as a wiring material has a property that a creep phenomenon is easily generated as compared with other metal materials, so that the S / M life is generally short. To supplement this, Cu is added, and TiN
Although measures have been taken such as sandwiching between high melting point metals such as Ti and TiW, wiring resistance increases and wiring steps increase. An increase in the wiring resistance causes an increase in the RC delay (R: wiring resistance, C: parasitic capacitance) and determines the speed performance. An increase in the wiring step directly leads to an increase in flattening cost.

In other words, at present, the design of the LSI is optimized by optimizing the trade-off relationship between reliability, performance and cost.
Manufacturing is underway, and further miniaturization and performance improvement are extremely difficult.

[0007]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention has been conceived in order to overcome the above-mentioned situation, and a groove having a predetermined shape is formed in an insulating film on a silicon substrate on which elements have been formed. Forming step and forming Ti only in the vicinity of the bottom of the groove.
Or a step of forming TiN and TiWN, a step of converting only the surface layer of the metal film into an alloy layer with a noble metal, and a step of filling the groove by plating the noble metal film by an electroless plating method using the alloy layer as a base metal. It is characterized by including the step of performing.

According to the present invention, the E /
It is noted that the M and S / M lifetimes are several tens of times longer than that of Al and the specific resistance ρ is lower by about 20%.

That is, according to the present invention, Au is used as a wiring material.
Is to dramatically improve the E / M and S / M lifetimes, and at the same time, to achieve flattening.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip according to a first embodiment of the present invention. First, as shown in FIG. 1A, a resist pattern 3 is formed on a plasma silicon oxide (P-SiO ₂ ) film 2 on a silicon substrate 1 on which device formation has been completed. Next, the P-SiO ₂ film 2 is etched by RIE using the resist pattern 3 as a mask to form a groove 4. Subsequently, the thickness of the Ti film 5 is set to 30 to 50 nm (nanometer).
It is applied by a sputtering method. Next, as shown in FIG. 2B, after a resist film 6 is applied, the film is etched back using O ₂ plasma and is left only inside the groove. Next, using a mixed gas plasma of Cl ₂ / Ar / O ₂ ,
The film 5 is removed, and the Ti film 5 is left only at the bottom of the groove. This situation is shown in FIG. Next, the resist films 3 and 6 are removed, and an Au film is sputter-deposited on the entire surface by about 10 nm.
When heat treatment is performed at 0 to 500 ° C. in an N ₂ atmosphere, an alloy layer 7 is formed as shown in FIG. Next, when etching is performed using aqua regia, unreacted Au on P-SiO ₂ is obtained.
The film is removed. Then, Au plating is performed using, for example, a Super Mex solution, which is an electroless plating solution manufactured by NE-Chem Cat Co., Ltd., and the inside of the groove 4 is filled to form the first layer as shown in FIG. Completely planarized Au wiring 8 is completed. This may be repeated for the second and subsequent layers.

The feature of this plating solution is that the deposition property is extremely good, and if only 1 to 2 Au atoms are present, the deposition of Au can be sufficiently performed. Therefore, the alloy layer may be extremely thin, and it is sufficient that even a small amount of Au atoms diffuse into the Ti film 5 even if it is not an alloy layer.

In the above description, it is apparent that the Ti film 5 may be made of another material. For example, Ti
A film, a TiW film and a nitride thereof, such as TiWN, may be used.

In order to ensure the heat resistance with the underlying material, a TiN or TiWN film is suitable, and these metals can be similarly removed by the above-mentioned Cl ₂ / Ar / O ₂ mixed gas plasma.

In this embodiment, the Au sputtered film 7 has been described as an example, but Pt may be used. In the case of Pt, since plating activity is stronger, there is an advantage that the initial plating rate is high.
Is better. However, at this time, if Pt atoms diffuse into the Au film, there is a disadvantage that the layer resistance increases, so that careful use is required. The resist film 6 may be an organic film such as polyimide as long as it can be removed by O ₂ plasma.

Next, a second embodiment of the present invention will be described. The second embodiment is an effective method for widening the manufacturing margin of the first embodiment. In the first embodiment, Ti
The film 5 was removed to the bottom of the groove. However, if the subsequent process is performed with the Ti film remaining on the side wall due to variations or the like, an alloy layer is also formed on the side wall.
The second embodiment is effective in the case where the plating film grows, resulting in a wiring shape in which both ends are raised, and there is a concern that the flatness is greatly impaired.

FIG. 2A is a cross-sectional view showing a state where the Ti film 5a remains on the side wall. From this state, a 50 to 100 nm thick P-
When the SiO ₂ film 2a is grown and etched back by RIE using a mixed gas plasma of CHF ₃ / O ₂ , the P-SiO ₂ film 2a remains only on the side wall and covers the remaining Ti film 5a. As a result, Au deposition from the side wall is prevented, and complete planarization becomes possible. And FIG. 1 (d),
The same step as (e) is performed.

[0018]

As described above, according to the present invention, a completely flat Au wiring can be realized, so that the E / M and S / M resistance, which has been a problem in the conventional Al wiring, is at least several tens times or more. This can be solved by dramatically increasing the length, and the RC delay can be improved by lowering the wiring resistance. Further, since there is no need for the cost for flattening which has been conventionally used, there is a great merit in terms of cost.

[Brief description of the drawings]

FIG. 1 is a sectional view showing main steps of a manufacturing method according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing some steps of a manufacturing method according to a second embodiment of the present invention in the order of steps.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2, 2a P-SiO ₂ substrate 3 resist film 4 groove 5, 5a Ti film 6 resist film 7 alloy layer 8 Au wiring

Claims (5)

(57) [Claims] 1. A step of forming a resist pattern having a predetermined shape on an insulating film on a main surface of a semiconductor substrate on which an element has been formed, and removing a part of the insulating film in a thickness direction using the resist pattern as a mask. Forming a groove having a substantially vertical side wall surface, forming a coating film after applying a first metal film over the entire surface, and forming the first metal film except for the inside of the groove.
Removing a part of the coating film so that the metal film is exposed;
Removing the metal film, applying a second metal film over the entire surface after removing the resist film and the coating film, and subjecting the first and second metal films to a heat treatment to cause an alloy to react. Forming a layer, removing the unreacted second metal film, and growing a third metal film by electroless plating using the alloy layer as a growth nucleus to fill the groove. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1, wherein the first metal film is Ti or a nitride thereof. 3. The method according to claim 1, wherein the first metal film is TiW or a nitride thereof. 4. The method according to claim 1, wherein the coating film is an organic film. 5. The method according to claim 1, wherein the second metal film and the third metal film are made of a noble metal.