JPH0878437A - Manufacture of semiconductor device and semiconductor device - Google Patents

Abstract

PURPOSE: To shorten a plating wiring process, improve heat dissipation efficiency of semiconductor by PHS, and enhance mechanical strength of semiconductor, by forming plating electrodes and plating wiring on the substrate surface, and forming a metal film on the inner surfaces of viaholes and the back of the substrate. CONSTITUTION: Source electrodes 102, drain electrodes 103 and gate electrodes 104 of FET's formed on the surface of a GaAs substrate 101, and dry-etching type viaholes 105 which penetrate the GaAs substrate from the surface to the back and are adjacent to the source electrodes 102 are formed. Power supplying layers 106 for plating the viahole part which cover the surface aperture part and are connected with the source electrodes 102 are formed. Plating electrodes 107 which are stacked on the layers 106 so as to cover them and are connected with the source electrodes 102 via the power supplying layer 106 are formed. PHS is formed on the back and in the viaholes 105 by an electrolytic plating method, and come into contact with the power supplying layer 106, in the viahole 105 surface aperture part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and particularly to a GaAs device which is essential for microwave communication such as mobile phones and satellite communication.
A via hole that is effective in reducing the source inductance in the high frequency band and that can efficiently dissipate heat so as to reduce the effect of heat generated during operation, which is a problem for high output and high performance devices. The present invention relates to the structure of the GaAs device and the manufacturing method.

[0002]

2. Description of the Related Art Normally, a via hole used in a GaAs device is intended only to connect an electrode formed on the front surface side of a substrate and a ground electrode on the rear surface side of the substrate. Are not particularly problematic, and they are rather determined by the constraints on the manufacturing process.

On the other hand, on the other hand, in order to improve the performance of the FET, a small via hole is formed in the immediate vicinity of the source electrode and connected to the back electrode, so that the phase difference between the FETs arranged in high density is increased. , And the source inductance is reduced. In this way, the via hole is not simply a through hole for the substrate to connect the electrode on the front side of the substrate and the ground electrode on the back side of the substrate in order to realize a high-performance FET.
It also plays an important role in improving the performance and characteristics of T.

FIG. 17 is a sectional structure view of a GaAs device having a dry etch type via hole of a conventional structure which is a first conventional example. In the figure, 501 is a GaAs substrate and 502 is a surface of the GaAs substrate 501. Source electrode of formed FET,
503 is a drain electrode, 504 is a gate electrode, 505 is a dry etch type via hole (Dry V / H) that penetrates from the front surface to the back surface of the GaAs substrate 501 and is adjacent to the source electrode 502, and 506 is the inner surface and back surface of the via hole 505. A plating power supply layer for the via hole which covers the opening and is in contact with the source electrode 502,
Reference numeral 507 denotes a plating electrode of a dry-etch type via hole portion which overlaps with the power supply layer 506 for plating from inside and is connected to the source electrode 502 through the power supply layer 506 for plating.
1 A heat dissipation electrode (Platform) formed on the back surface by electroplating and in contact with the plating power supply layer 506 at the via hole 505 back surface opening.
ed Heat Sink, hereinafter referred to as PHS).

18 to 20 show a method of manufacturing a GaAs device having a via hole of a conventional structure which is a first conventional example. In the drawings, the same reference numerals as those in FIG. 17 indicate the same or corresponding portions. , 509 is a photoresist pattern serving as a mask for forming a via hole from the substrate surface, 510 is a via hole forming hole, and 511 is a source electrode
Reference numeral 502 is a lower layer resist for forming the plated electrode 507 in the via hole portion, and 512 is an upper layer resist for forming the plated electrode 507 in the via hole portion.

Next, a manufacturing method will be described with reference to FIGS. First, as shown in FIG. 18, a GaAs substrate
501 source electrode 502, drain electrode 503,
A gate electrode 504 and a plated wiring are formed (FIG. 18).
(a)). The detailed process of forming the plated wiring will be described later.

Next, a resist for forming a hole for forming a via hole, which is highly accurately aligned with the source electrode 502.
509 is formed (FIG. 18 (b)). Next, this resist 50
The GaAs substrate 501 is etched by using 9 as a mask to form a via hole forming hole 510 (FIG. 18 (c)). The via hole forming hole 510 has, for example, a depth of 30 μm and a diameter of the opening.
8 to 10 μm.

Next, after removing the resist 509 (FIG. 18 (d)), a plating lower layer resist 511 for forming a plating electrode is formed in the via hole forming hole 510 (FIG. 18 (e)). The resist used here is the GaAs substrate 50.
1 Since a via hole forming hole 510 is formed on the surface, it is difficult for the positive type resist that exposes unnecessary parts to reach the resist in the via hole forming hole 510 during exposure, and the via hole forming hole is formed during development. Only the negative type resist can be used because the resist remains in the 510.

Next, a power supply layer 506 for plating is formed on the entire surface of the substrate for use in electrolytic plating in the next step (FIG. 19).
(a)). Since this power supply layer uses gold-based plating for electrolytic plating, a gold-based metal thin film such as TiAu that can be stably formed in the process is used. In addition, the formation method is
The sputtering method is adopted so that the bottom of the via hole forming hole 510 and the step of the plating lower layer resist 511 can be surely covered.

Next, an upper layer resist 512 is formed on the plating power supply layer 506 as a mask for electrolytic plating when forming a plating electrode in a via hole portion (FIG. 19 (b)).
As the resist used at this time, only a negative type resist can be used for the same reason as the lower layer resist.

Next, using the upper layer resist 512 formed as described above, the plating electrode 507 of the dry-etch type via hole portion connected to the source electrode 502 of the FET through the power feeding layer 506 for plating is formed (see FIG. c)). The wiring thickness to be formed should be at least to prevent electromigration.
2 μm or more is required.

Next, the upper layer resist 512 is removed (see FIG. 19).
(d)), the unnecessary power feeding layer 506 is removed by ion milling or the like, and the lower layer resist 511 is removed (FIG. 19 (e)), and the process of the surface process of the substrate 501 is completed.

Next, regarding the processing on the back surface side of the substrate 501,
Substrate 501 After applying an adhesive (for example, wax) on the surface side and sticking it to a reinforcing plate such as a glass plate (not shown), the substrate
501 A plating power supply layer 506 appears at the bottom of the via hole forming hole 510 from the back surface side.
By processing 501, a via hole 505 is formed (Fig. 20).
(a)). Lastly, PHS is applied to the back surface of the substrate 501 by electrolytic plating.
Ga with 508 forming a via-hole electrode with a conventional structure
The As device is completed (Fig. 20 (b)).

Here, using FIGS. 21 to 22 showing plated wirings omitted in FIGS. 17 to 20 for simplification of the drawings, a GaAs having a via hole of a conventional structure which is a first conventional example is used. For the method of forming the plated wiring of the device,
A more detailed description will be given.

In the figure, the same reference numerals as in FIG. 17 designate the same or corresponding parts, 513 is a plated wiring connected to the drain electrode 503, 514 is a lower resist for plating wiring for forming the plated wiring 513, and 515 is a plated wiring. 513 is a power supply layer for plating, and 516 is an upper layer resist for plating wiring for forming the plating wiring 513.

Next, a forming method will be described with reference to FIGS. 21 to 22. First, the GaAs substrate 50 on which the source electrode 502, drain electrode 503, and gate electrode 504 of the FET are formed.
1 On the surface (FIG. 21 (a)), a lower resist 514 for plating wiring for forming a plating wiring 513 connected to the drain electrode 503 is formed (FIG. 21 (b)). The resist used here is a hole 510 for forming a via hole on the surface of the GaAs substrate 501.
Since it is not formed yet, it is possible to use a positive type resist that can realize the high resolution required for plated wiring.

Next, a power supply layer 515 for plating is formed on the entire surface of the substrate for use in electrolytic plating in the next step (FIG. 21).
(c)). As a forming method, a sputtering method is adopted so that the step of the lower resist 514 for plated wiring can be surely covered.

Next, an upper layer resist 516 for plating wiring, which serves as a mask for electrolytic plating when forming the plating wiring 513, is formed on the power supply layer 515 for plating (FIG. 21 (d)).
As the resist used at this time, a positive type resist can be used for the same reason as the lower layer resist. Next, the upper layer resist 51 for plated wiring formed above
Use 6 to connect the plated wiring 51 to the drain electrode 503.
3 is formed (FIG. 21 (e)).

Next, the upper layer resist 516 is removed (see FIG. 22).
(a)), the unnecessary power supply layer 515 is removed by ion milling or the like, and the lower layer resist 514 is removed (FIG. 22 (b)), and the formation of the plated wiring 513 is completed. After this, the processes of FIGS. 18 (b) to 20 (b) are performed to complete a GaAs device having a via hole electrode of a conventional structure.

FIG. 23 shows a second conventional example. For example, a via hole forming hole formed by etching from the substrate surface side, which is disclosed in Japanese Patent Laid-Open No. 47845, is temporarily provisionally filled with a resist. FIG. 3 is a cross-sectional structural view of a GaAs device having a dry-etch type via hole that can be considered from the method of manufacturing a semiconductor device including steps, in which 501 is a GaAs substrate and 502 is a source of FET formed on the surface of the GaAs substrate 501. Electrode, 503 is drain electrode, 504
Is a gate electrode, 505 is a dry-etch type via hole that penetrates from the front surface to the back surface of the GaAs substrate 501 and is adjacent to the source electrode 502, and 506 covers the surface opening of the via hole 505.
In addition, the plating power feeding layer in the via hole that is in contact with the source electrode 502, 507 overlaps so as to cover the plating power feeding layer 506, and the source electrode 502 is interposed via the plating power feeding layer 506.
Reference numeral 508 denotes a dry etching type via hole portion connected to the substrate, and 508 is a PHS which is formed on the back surface of the substrate 501 and the inside of the via hole 505 by an electrolytic plating method and contacts the plating power supply layer 506 at the via hole 505 surface opening.

24 to 26 show a method of manufacturing the GaAs device shown in FIG. 23 which is a second conventional example, in which the same reference numerals as those in FIG. 23 designate the same or corresponding portions, and 509 designates a substrate. A resist pattern that serves as a mask for forming a via hole from the surface, 510 is a hole for forming a via hole, 511 is a lower layer resist for connecting to the source electrode 502 to form a plated electrode 507 in the via hole, and 511 is Upper layer resist for forming the plated electrode 507 in the via hole portion, 517 is a hole for forming a via hole 510.
Is a filling resist for filling.

Next, the manufacturing method will be described with reference to FIGS. First, as shown in FIG. 24, a GaAs substrate
501 source electrode 502, drain electrode 503,
A gate electrode 504 is formed (FIG. 24 (a)).

Next, a resist 50 for forming a via hole is accurately aligned with the source electrode 502.
9 is formed (FIG. 24 (b)). Then this resist 509
The GaAs substrate 501 is etched using the mask as a mask to form a via hole forming hole 510 (FIG. 24 (c)). Next, after removing the resist 509 (FIG. 24 (d)), a filling resist 517 is filled in the via hole forming hole 510 (FIG. 2).
4 (e)).

The filling resist 517 needs to have a high viscosity in order to fill a via hole forming hole having a depth of 30 μm, for example. A low-viscosity resist is more likely to flow into the via-hole forming hole, but when the heat treatment is applied to the resist to evaporate the solvent, the resist thickness cannot be gained and a deep step like a via-hole forming hole is formed. The resist cannot be filled.

Next, a lower layer resist 511 for plating is formed in order to form a plated wiring in the via hole 505 (FIG. 2).
5 (a)). The resist used here has the holes 510 for forming via holes on the surface of the GaAs substrate 501 temporarily filled.
Unlike the first conventional example, it is possible to use a positive type resist capable of realizing high resolution.

Next, as in the first conventional example, a plating power supply layer 50 for use in electrolytic plating in the next step on the entire surface of the substrate.
6 is formed (FIG. 25 (b)). Next, the power supply layer 50 for plating
An upper layer resist 512, which serves as a mask for electrolytic plating when forming the plated electrode 507 in the via hole and the plated wiring of each electrode, is formed on 6 (FIG. 25 (c)). As the resist used at this time, a high-resolution positive type resist can be used like the lower layer resist for plating, and therefore a highly accurate wiring pattern can be formed. Next, using the upper layer resist 512 formed as described above, the plating electrode 507 of the dry-etch type via hole portion connected to the source electrode 502 of the FET through the feeding layer 506 for plating is formed (FIG. 25 (d)). .
Although not shown in the figure, plated wirings connected to the respective electrodes are also formed here.

Next, the upper resist 512 is removed (see FIG. 25).
(e)), the unnecessary part of the power supply layer 506 is removed by ion milling or the like, and the lower layer resist 511 is removed (FIG. 26 (a)), and the process of the surface process of the substrate 501 is completed.

Next, regarding the processing on the back surface side of the substrate 501,
Substrate 501 After applying an adhesive (for example, wax) on the surface side and sticking it to a reinforcing plate such as a glass plate (not shown), the substrate
501 A resist 517 filled in the via-hole forming hole 510 appears from the back surface side, for example, a GaAs substrate 50 is ground or etched from the back surface until the thickness becomes 30 μm.
1 is processed to form a via hole 505 (Fig. 26 (b))
). Next, the resist 5 filled in the via hole 505 is filled.
17 is removed from the back surface of the substrate 501 with a resist stripping solution (FIG. 26 (c)).

Finally, the back surface of the substrate 501 and the via hole 505.
PHS508 is formed inside by electrolytic plating to complete a GaAs device having a via hole electrode of the second conventional example (FIG. 26 (d)).

[0030]

In the first conventional manufacturing method, when the lower resist for plating is formed (see FIG. 18).
(e)), such as a hole for forming a via hole, for example, a depth of 30
If there are deep and small depressions with a diameter of 8 μm and an opening diameter of 8-10 μm on the substrate surface, the solid components of the resist will flow into the depressions when the solvent is volatilized in the baking process after resist application, so the resist portion on the upper surface of the depressions It gets depressed. Therefore, the resist cannot be uniformly applied to the surface of the substrate, resulting in insufficient coverage of active elements and the like as shown in FIG.
The underlying pattern such as the active element may be exposed.

Further, when the lower layer resist for plating and the upper layer resist for plating are exposed and developed to remove unnecessary portions, even if a negative type resist for exposing necessary portions is used, the holes for forming via holes are deep, and Since the opening diameter is also small, the resist easily remains in the via hole forming hole,
It became a factor of concern in the subsequent process.

Further, in the past, in order to ensure the accuracy of the plated wiring, it is not possible to simultaneously form the plated wiring in the step of forming the plated electrode in the via hole where only a negative resist having poor accuracy can be used, and an active element is formed on the surface of the semiconductor substrate. After that, before forming the via hole forming hole, the plated wiring is formed in a separate step using a positive type photoresist for the plated wiring, which requires a long number of steps.

Further, in a semiconductor device having a via hole, it is necessary to grind the entire substrate to, for example, about 30 μm in order to penetrate the via hole. Therefore, a semiconductor device of a GaAs substrate, which is particularly fragile in material, has been hitherto known. The mechanical strength during the handling of the substrate has been a problem.

Further, in a semiconductor device having a via hole, a method of efficiently radiating the heat generated from the active element portion on the front surface of the semiconductor substrate to the back surface side of the substrate may be a method of filling the inside of the via hole with a metal film.

However, in the manufacturing method of the first conventional example, when the plating power supply layer in the via hole and the plating electrode in the via hole portion are thickened in order to fill the inside of the via hole with the metal film, the processing is performed from the substrate surface. Since the thickness of the plating layer on the entire substrate surface increases, the step on the substrate surface becomes large.

Therefore, when processing the back side of the substrate, the step on the substrate surface becomes a problem when the substrate front side is attached to the reinforcing plate. Therefore, the inside of the via hole must be left hollow, and its heat dissipation efficiency is not sufficient. I couldn't say that there was.

In the second conventional manufacturing method, the via hole forming hole is filled with resist. However, this filling resist is used to fill the via hole forming hole having a depth of 30 μm, for example. However, it is necessary that the solid component has a high viscosity of, for example, 50% or more. A low-viscosity resist with a normal solid content of a few percent is more likely to flow into the via-hole forming hole, but when the solvent is volatilized by applying heat treatment to the resist, the resist thickness will increase if the solid content is low. Therefore, the resist cannot be filled into a deep step like a via hole forming hole.

However, for example, a highly viscous resist having a solid content of, for example, 50% or more is formed on a semiconductor substrate surface having a via hole forming hole having a depth of 30 μm and an opening diameter of about 8 to 10 μm by a usual method. Even if applied, it is difficult to completely fill the resist in a fine place such as a hole for forming a via hole without a gap due to the viscosity of the resist,
For example, a cavity 520 as shown in FIG. 28 is often formed inside the via hole forming hole.

Therefore, in the subsequent heat treatment step, the cavity 520 inside the via hole forming hole contracts, or the cavity 520 expands when sucked in a vacuum, which is a major cause of concern in the manufacturing process. .

The present invention has been made to solve the above problems, and even if a recess such as a hole for forming a via hole exists, the resist can be applied uniformly, and the resist does not remain in the recess. , Shortens the plating wiring process, improves the heat dissipation efficiency of PHS of the semiconductor, enhances the mechanical strength of the semiconductor, and completely removes the high-viscosity resist in a deep recess with a small opening diameter such as a via hole formation hole without gaps. An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device which can be filled.

[0041]

According to a method of manufacturing a semiconductor device according to the present invention (claim 1), a recess is formed on the surface of a semiconductor substrate on which an active element is formed, and a resist is filled in the recess, and It is applied so as to cover the entire surface of the substrate, exposed and developed using a mask having an opening in a required portion, and the resist is left only in the concave portion, and heat treatment is performed to deform the resist to form a concave portion of the concave portion of the substrate surface. Flatten the steps,
The plating electrode and the plating wiring are formed on the surface of the substrate, and the resist filled in the recess is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 2), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist which does not glass transition at the temperature of the subsequent heat treatment is formed inside the recess. Substrate, and coated so as to cover the entire surface of the substrate, exposed and developed using a mask having an opening in a required portion, leaving the resist only in the concave portion, and performing heat treatment to deform the resist to form a substrate. The steps of the recesses on the surface are made flat, the plating electrodes and the plating wirings are formed on the substrate surface, and the resist filled in the recesses is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 3), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to remove the resist component. The solvent of the same component as that of the above solvent is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the resist is exposed and developed using a mask having an opening in a required portion to form the above-mentioned concave portion. Only the resist is left, and heat treatment is performed to deform the resist to flatten the step of the recess on the substrate surface, form a plating electrode and plating wiring on the substrate surface, and remove the resist filled in the recess. It is the one.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 4), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W for 10 seconds. ~ 30 seconds, apply the same solvent as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, using a mask with openings in the required parts After exposure and development, the resist is left only in the recesses, and heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, and to form plating electrodes and plating wirings on the substrate surface. The filled resist is removed.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 5), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening at a required portion, leaving the resist only in the hole for forming a via hole, and performing heat treatment. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, a lower layer resist for plating is formed on the active element forming portion, and the entire surface of the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the upper layer, an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole. The resist filled in the via hole is removed to form a metal film on the inner surface of the via hole and the back surface of the substrate.

In the method for manufacturing a semiconductor device according to the present invention (claim 6), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening at a required portion, leaving the resist only in the hole for forming a via hole, and performing heat treatment. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, a lower layer resist for plating is formed on the active element forming portion, and the entire surface of the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the upper layer, an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface. To form
The resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 7), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening at a required portion, leaving the resist only in the hole for forming a via hole, and performing heat treatment. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, a lower layer resist for plating is formed on the active element forming portion, and the entire surface of the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the upper layer, and an upper layer resist serving as a mask for electrolytic plating for forming a plating electrode and a plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. The upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Only the portion directly below the forming hole is processed until the via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, the inner surface of the via hole, and the substrate. A metal film is formed on the back surface.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 8), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening at a required portion, leaving the resist only in the hole for forming a via hole, and performing heat treatment. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, a lower layer resist for plating is formed on the active element forming portion, and the entire surface of the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the upper layer, an upper layer resist is formed which serves as a mask during electrolytic plating for forming a plating electrode and plated wiring, and electrolytic plating is selectively performed only on the opening of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and a via hole is formed in the substrate. Only the portion directly under the hole is processed until the hole for forming a via hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole and the back surface of the substrate are removed. The metal film is formed on.

In the semiconductor device according to the present invention (claim 9), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And then coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, leaving the resist only in the via-hole forming holes, and performing heat treatment. Deform the resist to flatten the step of the via hole forming hole on the substrate surface, form the plating electrode and the plating wiring on the substrate surface, until the via hole forming hole is opened from the back surface on the entire back surface of the substrate. Process to form a via hole, remove the resist filled in the via hole,
A metal film is formed on the inner surface of the via hole and the back surface of the substrate.

In the semiconductor device according to the present invention (claim 10), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And then coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, leaving the resist only in the via-hole forming holes, and performing heat treatment. Deform the resist to flatten the step of the via hole forming hole on the substrate surface, form the plating electrode and the plating wiring on the substrate surface, until the via hole forming hole is opened from the back surface on the entire back surface of the substrate. Form a via hole by processing, remove the resist filled in the via hole, completely fill the inside of the via hole with a metal film,
A metal film is formed on the back surface of the substrate.

Further, in the semiconductor device according to the present invention (claim 11), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And then coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, leaving the resist only in the via-hole forming holes, and performing heat treatment. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, Only the portion directly below the via hole forming hole of the substrate was processed until the via hole forming hole was opened from the back surface to form a via hole, and the via hole was filled. Removing the resist, the inner surface of the via hole, and is obtained as by forming a metal film on the rear surface of the substrate.

In the semiconductor device according to the present invention (claim 12), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via-hole forming hole. And then coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, leaving the resist only in the via-hole forming holes, and performing heat treatment. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, Only the portion directly below the via hole forming hole of the substrate was processed until the via hole forming hole was opened from the back surface to form a via hole, and the via hole was filled. Removing the resist, the inside of the via hole is completely filled with a metal film, in which as formed by forming a metal film on the rear surface of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 13), a recess is formed in the surface of the semiconductor substrate on which the active element is formed, a resist is filled in the recess, and the entire surface of the substrate is covered. Coating so as to cover the surface of the substrate by removing the resist of the unnecessary portion of the substrate surface by the etch back method,
A plating electrode and a plating wiring are formed on the surface of the substrate, and the resist filled in the recess is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 14), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to remove the resist component. The solvent of the same component as the solvent of the above is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and the unnecessary portion of the resist on the surface of the substrate is removed by an etch back method. To flatten the steps of the recess on the substrate surface,
A plating electrode and a plating wiring are formed on the surface of the substrate, and the resist filled in the recess is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 15), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the oxygen plasma treatment is performed on the surface of the semiconductor substrate at 200 W to 300 W for 10 seconds. ~ 30 seconds, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the solvent is dried, the substrate surface of the substrate by the etch-back method. By removing the resist of the unnecessary portion, the step of the concave portion on the substrate surface is made flat, the plating electrode and the plating wiring are formed on the substrate surface, and the resist filled in the concave portion is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 16), a via hole forming hole having a predetermined depth is formed in the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application, and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the surface of the substrate by the etch-back method to flatten the step of the hole for forming via holes on the surface of the substrate, A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and only the opening of the upper layer resist is selectively electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole, and the above The metal film is formed on the back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 17), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application, and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the surface of the substrate by the etch-back method to flatten the step of the hole for forming via holes on the surface of the substrate, A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and only the opening of the upper layer resist is selectively electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole is removed. , And a metal film is formed on the back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 18), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application, and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the surface of the substrate by the etch-back method to flatten the step of the hole for forming via holes on the surface of the substrate, A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and only the opening of the upper layer resist is selectively electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface. A hole is formed, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 19), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and the resist is used to form the via hole. Filling the inside of the hole for application, and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the surface of the substrate by the etch-back method, to flatten the step of the hole for forming via holes on the surface of the substrate, A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and only the opening of the upper layer resist is electrolytically plated, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, and the lower layer is removed. The layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface. A hole is formed, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

In the semiconductor device according to the present invention (claim 20), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And coating so as to cover the entire surface of the substrate, and removing unnecessary portions of the resist on the surface of the substrate by an etch-back method to flatten the steps of the holes for forming via holes on the surface of the substrate. A plating electrode and a plating wiring are formed on the substrate, the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. A metal film is formed on the inner surface of the hole and the back surface of the substrate.

In the semiconductor device according to the present invention (claim 21), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And coating so as to cover the entire surface of the substrate, and removing unnecessary portions of the resist on the surface of the substrate by an etch-back method to flatten the steps of the holes for forming via holes on the surface of the substrate. A plating electrode and a plating wiring are formed on the substrate, the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. The inside of the hole is completely filled with a metal film, and the metal film is formed on the back surface of the substrate.

In the semiconductor device according to the present invention (claim 22), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. And coating so as to cover the entire surface of the substrate, and removing unnecessary portions of the resist on the surface of the substrate by an etch-back method to flatten the steps of the holes for forming via holes on the surface of the substrate. Form a plating electrode and plating wiring on the substrate, process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and open only the portion directly below the via hole forming hole of the substrate until the via hole forming hole opens from the back surface. After processing, a via hole is formed, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. Is obtained in such a manner that form.

Further, in the semiconductor device according to the present invention (claim 23), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via-hole forming hole. And coating so as to cover the entire surface of the substrate, and removing unnecessary portions of the resist on the surface of the substrate by an etch-back method to flatten the steps of the holes for forming via holes on the surface of the substrate. Form a plating electrode and plating wiring on the substrate, process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and open only the portion directly below the via hole forming hole of the substrate until the via hole forming hole opens from the back surface. Forming a via hole by processing, removing the resist filled in the via hole, completely filling the inside of the via hole with a metal film, the substrate It is obtained as by forming a metal film on the rear surface.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 24), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and a resist component is added. The solvent of the same component as the solvent is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the step is flattened on the surface of the substrate by leaving the resist only in the recesses. The plating electrode and the plating wiring are formed on the surface of the substrate, and the resist filled in the recess is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 25), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the oxygen plasma treatment is performed on the surface of the semiconductor substrate at 200 W to 300 W for 10 seconds. ~ 30 seconds, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, leaving the resist only in the recesses The step on the surface of the substrate is made flat, the plating electrode and the plating wiring are formed on the surface of the substrate, and the resist filled in the recess is removed.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 26), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to remove the resist component. Solvent of the same component as the above solvent is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the resist is exposed and developed using a mask having an opening at a required portion. Then, the resist is left only in the recesses, and the heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, form plating electrodes and plating wirings on the substrate surface, and remove the resist filled in the recesses. It is designed to be removed.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 27), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and a resist component is added. A solvent having the same component as that of the above solvent is applied to the surface of the semiconductor substrate, and a resist that does not cause glass transition at the temperature of the subsequent heat treatment before the applied solvent is dried is applied to the surface of the semiconductor substrate, and a mask having an opening in a required portion. Is used to expose and develop the resist to leave the resist only in the recesses, and heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, and form the plating electrodes and the plating wirings on the substrate surface. The resist filled in the recess is removed.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 28), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and a resist component is added. The solvent of the same component as the solvent of the above is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and the unnecessary portion of the resist on the surface of the substrate is removed by an etch back method. The flatness of the steps of the recesses on the surface of the substrate is followed by forming plating electrodes and plating wirings on the surface of the substrate, and removing the resist filling the recesses.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 29), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen is formed on the surface of the semiconductor substrate. Perform plasma treatment, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, only the via hole forming hole The resist is left to flatten the steps on the surface of the substrate, a lower layer resist for plating is formed on the active element formation portion, and a metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating. Forming an upper layer resist that serves as a mask during electrolytic plating for forming plated wiring, and selectively performing electrolytic plating only on the openings of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is formed. The resist filled in is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 30), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen is formed on the surface of the semiconductor substrate. Perform plasma treatment, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, only the via-hole forming hole The resist is left to flatten the steps on the surface of the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power feeding layer for electrolytic plating. Forming an upper layer resist that serves as a mask during electrolytic plating for forming plated wiring, and selectively performing electrolytic plating only on the openings of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, The resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 31), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen is formed on the surface of the semiconductor substrate. Perform plasma treatment, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, only the via-hole forming hole The resist is left to flatten the steps on the surface of the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power feeding layer for electrolytic plating. Forming an upper layer resist that serves as a mask during electrolytic plating for forming plated wiring, and selectively performing electrolytic plating only on the openings of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, directly below the via hole forming hole of the substrate. Only the part is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed.
A metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 32), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and oxygen is formed on the surface of the semiconductor substrate. Perform plasma treatment, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, only the via-hole forming hole The resist is left to flatten the steps on the surface of the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power feeding layer for electrolytic plating. An upper layer resist is formed which serves as a mask during electrolytic plating for forming plated wiring, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist. Then, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is via-formed. Form a via hole by processing until the hole forming hole opens from the back surface, and remove the resist filled in the via hole,
A metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the semiconductor device according to the present invention (claim 33), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment. Do the same, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the holes for forming via holes. Flatten the steps on the surface of the substrate, form plated electrodes and plated wiring on the surface of the substrate, and process the entire back surface of the substrate until the via-hole forming hole opens from the back surface to form a via hole. The resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the semiconductor device according to the present invention (claim 34), a via hole forming hole having a predetermined depth is formed in the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment. Do the same, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the holes for forming via holes. Flatten the steps on the surface of the substrate, form plated electrodes and plated wiring on the surface of the substrate, and process the entire back surface of the substrate until the via-hole forming hole opens from the back surface to form a via hole. By removing the resist filled in the via hole, completely filling the inside of the via hole with a metal film, and forming a metal film on the back surface of the substrate. A.

In the semiconductor device according to the present invention (claim 35), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen plasma treatment is performed on the surface of the semiconductor substrate. Do the same, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the holes for forming via holes. Flatten the steps on the surface of the substrate, form plating electrodes and plating wiring on the surface of the substrate, and machine the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength. The via hole is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Le inner surface, and is obtained as by forming a metal film on the rear surface of the substrate.

In the semiconductor device according to the present invention (claim 36), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment. Do the same, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the holes for forming via holes. Flatten the steps on the surface of the substrate, form plating electrodes and plating wiring on the surface of the substrate, and machine the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength. The via hole is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. The internal Le was completely filled with metal film, in which as formed by forming a metal film on the rear surface of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 37), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a recess forming position is formed on the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the same time, the insulating film is etched using the etching mask, and the recess is etched on the substrate surface using the same etching mask. The resist used as the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the recesses to flatten the substrate surface, and the insulating film used as a mask during selective crystal growth. Are removed, active elements are formed on the surface of the substrate, plated electrodes and wiring are formed on the surface of the substrate, and crystal growth is performed. Ri is obtained so as to remove the filled crystal above the recess.

In the method for manufacturing a semiconductor device according to the present invention (claim 38), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the hole forming position, the insulating film is etched using the etching mask, and the substrate surface is formed using the same etching mask. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Forming, selectively electrolytically plating only the openings of the upper layer resist, removing the upper layer resist, removing unnecessary portions of the power feeding layer, removing the lower layer resist, and forming the substrate for via hole formation. The via hole is formed by processing until the hole opens from the back surface, and the crystal filled in the via hole is removed by crystal growth. And it is obtained so as to form a metal film on the rear surface of the substrate.

In the method for manufacturing a semiconductor device according to the present invention (claim 39), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the hole forming position, the insulating film is etched using the etching mask, and the substrate surface is formed using the same etching mask. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Then, electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is via-formed. Form a via hole by processing until the hole forming hole opens from the back side,
The crystal filled in the via hole is removed by crystal growth, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 40), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the hole forming position, the insulating film is etched using the etching mask, and the substrate surface is formed using the same etching mask. The via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask to grow crystals to fill the via hole forming hole and the substrate. The surface is flattened, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist,
Unnecessary parts of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Only the portion directly below the via hole forming hole of the substrate is used for via hole formation. Form a via hole by processing until the hole opens from the back surface, remove the crystal filled in the via hole by crystal growth, and form a metal film on the inner surface of the via hole and the back surface of the substrate. It was done.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 41), an insulating film is formed on the surface of the GaAs substrate,
The entire surface of the insulating film is coated with a resist, and the resist is exposed and developed using a mask for forming a resist pattern having an opening at a hole forming position for the via hole, and an etching mask is formed. By etching the insulating film, using the same etching mask to form a via hole forming hole of a predetermined depth on the substrate surface, remove the resist used for the etching mask, mask the insulating film By filling the via hole forming hole by making a crystal grow to flatten the substrate surface, remove the insulating film used as a mask during selective crystal growth, form an active element on the substrate surface, A lower layer resist for plating is formed on the active element formation part, and a gold layer is formed on the entire surface of the substrate as a power supply layer for electrolytic plating. A film is formed to form an upper layer resist that serves as a mask during electrolytic plating for forming a plating electrode and a plated wiring, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist, and The unnecessary portion of the power supply layer is removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain the mechanical strength. Only the portion directly below the via hole forming hole of the substrate is formed as the via hole forming hole. Is processed from the back surface to an opening to form a via hole, the crystal filled in the via hole is removed by crystal growth, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. It is a thing.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 42), an insulating film is formed on the surface of the GaAs substrate,
The entire surface of the insulating film is coated with a resist, and the resist is exposed and developed using a mask for forming a resist pattern having an opening at a hole forming position for the via hole to form an etching mask. By etching the insulating film, using the same etching mask to form a via hole forming hole of a predetermined depth on the substrate surface, remove the resist used for the etching mask, mask the insulating film InGaP, which has selectivity for wet etching of a GaAs substrate, is selectively crystal-grown to fill the via-hole forming hole to flatten the substrate surface, and the insulating film used as a mask during selective crystal growth is removed. After removing, an active element is formed on the surface of the substrate, and a lower resist layer for plating is formed on the active element forming portion. Forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring, only the opening of the upper layer resist Electrolytic plating is selectively performed on the upper layer resist, the unnecessary portion of the power supply layer is removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole opens from the back surface. A via hole is formed, and InGaP 2 filled in the via hole by crystal growth is removed with hydrochloric acid to form a metal film on the inner surface of the via hole and the back surface of the substrate.

In a semiconductor device according to the present invention (claim 43), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. A mask for forming a resist pattern having an opening at a position is used for exposure and development to form an etching mask, the above-mentioned etching mask is used to etch the above-mentioned insulating film, and the same etching mask is used to form a predetermined pattern on the substrate surface. A hole for forming a via hole having a depth is formed by etching, the resist used as an etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole to flatten the surface of the substrate. The insulating film used as a mask during crystal growth is removed, an active element is formed on the substrate surface, and a plating electrode is formed on the substrate surface. And plating wiring is formed, and the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the crystal filled in the via hole is removed by crystal growth. A metal film is formed on the inner surface of the hole and the back surface of the substrate.

In the semiconductor device according to the present invention (claim 44), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied over the entire surface of the insulating film, and a via hole forming hole is formed in the resist. A mask for forming a resist pattern having an opening at a position is used for exposure and development to form an etching mask, the above-mentioned etching mask is used to etch the above-mentioned insulating film, and the same etching mask is used to form a predetermined pattern on the substrate surface. A hole for forming a via hole having a depth is formed by etching, the resist used as an etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole to flatten the surface of the substrate. The insulating film used as a mask during crystal growth is removed, an active element is formed on the substrate surface, and a plating electrode is formed on the substrate surface. And forming plated wiring, processing the entire back surface of the substrate until a via hole forming hole is opened from the back surface to form a via hole, and removing the crystal filled in the via hole by crystal growth. The inside of the hole is completely filled with a metal film, and the metal film is formed on the back surface of the substrate.

In the semiconductor device according to the present invention (claim 45), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. A mask for forming a resist pattern having an opening at a position is used for exposure and development to form an etching mask, the above-mentioned etching mask is used to etch the above-mentioned insulating film, and the same etching mask is used to form a predetermined pattern on the substrate surface. Forming a via hole forming hole of a depth by etching, removing the resist used for the etching mask, the insulating film as a mask to grow the crystal by growing the via hole to fill the via hole to flatten the substrate surface, The insulating film used as the mask during the selective crystal growth is removed, an active element is formed on the substrate surface, and the active element is formed on the substrate surface. Form electrodes and plated wiring, and process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and process only the area directly below the via hole forming hole of the board until the via hole forming hole opens from the back surface. To form a via hole, remove the crystal filled in the via hole by crystal growth, the inner surface of the via hole,
Also, a metal film is formed on the back surface of the substrate.

In the semiconductor device according to the present invention (claim 46), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. A mask for forming a resist pattern having an opening at a position is used for exposure and development to form an etching mask, the above-mentioned etching mask is used to etch the above-mentioned insulating film, and the same etching mask is used to form a predetermined pattern on the substrate surface. Forming a via hole forming hole of a depth by etching, removing the resist used for the etching mask, the insulating film as a mask to grow the crystal by growing the via hole to fill the via hole to flatten the substrate surface, The insulating film used as a mask during selective crystal growth is removed, active elements are formed on the surface of the substrate, and a mask is formed on the surface of the substrate. Form electrodes and plated wiring, and process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and process only the area directly below the via hole forming hole of the board until the via hole forming hole opens from the back surface. To form a via hole, remove the crystal filled in the via hole by crystal growth, completely fill the inside of the via hole with a metal film, and form a metal film on the back surface of the substrate. It is a thing.

In the resist coating method according to the present invention (claim 47), the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and a solvent having the same component as the solvent in the resist component is coated on the surface of the semiconductor substrate. The resist is applied to the surface of the semiconductor substrate before the solvent is dried.

In the resist coating method according to the present invention (claim 48), the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W for 10 to 30 seconds, and a solvent having the same composition as the solvent in the resist composition is used as described above. The resist is applied to the surface of the semiconductor substrate, and the resist is applied to the surface of the semiconductor substrate before the applied solvent dries.

[0089]

In the method of manufacturing a semiconductor device according to the present invention (claim 1), a recess is formed in the surface of the semiconductor substrate on which the active element is formed, the resist is filled in the recess, and the whole surface of the substrate is covered. After applying, exposing and developing using a mask having an opening in a required portion, leaving the resist only in the concave portion, and performing heat treatment to deform the resist to flatten the step of the concave portion on the substrate surface, and the state Since the plating electrode and the plating wiring are formed on the substrate surface and the resist filled in the recess is removed thereafter, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. As a result, the coverage of the active elements formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active elements, etc. from being exposed. And resist when forming the plating wiring can be prevented from remaining in the recess,
Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated wiring with high precision simultaneously with the formation of the plated electrode. Furthermore, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described action can be made more reliable.

In the method of manufacturing a semiconductor device according to the present invention (claim 2), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, the resist is filled in the recess, and the entire surface of the substrate is covered. As described above, exposing and developing using a mask having an opening in a required portion, leaving the resist only in the recess, and performing heat treatment to deform the resist to flatten the step of the recess on the substrate surface, In that state, a plating electrode and a plating wiring are formed on the surface of the substrate, and then the resist filled in the recess is removed. Further, as the resist filling the inside of the recess, a resist that does not cause glass transition at the temperature of the subsequent heat treatment is used. Thus, the volume expansion coefficient does not change due to the glass transition of the resist, and the flatness of the substrate can be easily controlled.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 3), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, oxygen plasma treatment is performed on the surface of the semiconductor substrate, and Apply the solvent of the same component as the solvent to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, and expose and develop using a mask that has openings in the required parts, and only the above concave parts The resist is left on, and heat treatment is performed to deform the resist to flatten the step of the recess on the substrate surface, and in that state, a plating electrode and a plating wiring are formed on the substrate surface, and then the resist filled in the recess is removed. Since it is removed, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active element is improved, the underlying pattern of the active element or the like can be prevented from being exposed, and the resist when forming the plating electrode and the plating wiring can be prevented from remaining in the recess. Further, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision simultaneously with the formation of the plated electrode. Furthermore, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described action can be made more reliable. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess of the surface of the semiconductor substrate that is deep and has a small opening diameter. The resist can be filled, and the substrate surface can be flattened more reliably.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 4), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200W to 300W for 10 to 10W. Do it for 30 seconds, apply the same solvent as the solvent in the resist component to the surface of the semiconductor substrate,
A resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and exposure is performed using a mask having an opening at a required portion.
After development, the resist is left only in the recess, and heat treatment is performed to deform the resist to flatten the step of the recess on the substrate surface, and in that state, a plating electrode and a plating wiring are formed on the substrate surface, and then the above Since the resist filled in the concave portion is removed, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the substrate surface, and thus the coverage of the active element formed on the substrate surface can be improved. It is possible to prevent the underlying pattern such as the active element from being exposed, and it is possible to prevent the resist at the time of forming the plating electrode and the plating wiring from remaining in the recess. Since a high-resolution positive type photoresist can be used as a resist for forming plated wiring, the shape of the plated electrode Simultaneously it is possible to form a plated wiring with high accuracy. Furthermore, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described action can be made more reliable. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess of the surface of the semiconductor substrate that is deep and has a small opening diameter. The resist can be filled, and the substrate surface can be flattened more reliably.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 5), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used for forming the via hole. Fill the inside of the hole and apply so as to cover the entire surface of the substrate, expose and develop the resist using a mask having an opening at a required portion,
Leaving the resist only in the via hole forming hole, heat treatment is performed to deform the resist to flatten the step of the via hole forming hole on the substrate surface, and form a plating lower layer resist on the active element forming portion, A metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and an upper layer resist serving as a mask at the time of electrolytic plating for forming a plating electrode and a plating wiring is formed, and only the opening of the upper layer resist is selectively formed. Electrolytic plating is performed to remove the upper layer resist, remove unnecessary portions of the power feeding layer, remove the lower layer resist, and process the substrate until the via hole forming hole opens from the back surface to form a via hole. After the formation, the resist filled in the via hole is removed, and the metal film is formed on the inner surface of the via hole and the back surface of the substrate. It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element and the like. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole, and further, it is possible to prevent the resist from being formed as a resist for forming the plated electrode and the plated wiring. Since a positive photoresist of resolution can be used, highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 6), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used for forming the via hole. Fill the inside of the hole and apply so as to cover the entire surface of the substrate, expose and develop the resist using a mask having an opening at a required portion,
Leaving the resist only in the via hole forming hole, heat treatment is performed to deform the resist to flatten the step of the via hole forming hole on the substrate surface, and form a lower resist layer for plating on the active element forming portion, A metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and an upper layer resist serving as a mask at the time of electrolytic plating for forming a plating electrode and a plating wiring is formed, and only the opening of the upper layer resist is selectively formed. Then, the upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed until the via hole forming holes are opened from the back surface. Forming a via hole, removing the resist filled in the via hole,
Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active elements formed on the substrate is improved, the underlying pattern of the active elements and the like can be prevented from being exposed, and the resist for forming the plated electrodes and the plated wiring remains in the holes for forming via holes. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as forming the plated electrode. Can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 7), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used for forming the via hole. Filling the inside of the hole and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening at a required portion,
Leaving the resist only in the via hole forming hole, heat treatment is performed to deform the resist to flatten the step of the via hole forming hole on the substrate surface, and form a plating lower layer resist on the active element forming portion, A metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plated wiring is formed, and only the opening of the upper layer resist is selectively formed. Electrolytic plating is performed, the upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Only the portion directly under the via hole forming hole is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is filled with the via hole. Since the strike is removed and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface can be uniformly applied. As a result, the coverage of active elements formed on the surface of the substrate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plated electrodes and the plated wiring is the via holes described above. Since it can be prevented from remaining in the formation hole, and furthermore, a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 8), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and a resist is used for forming the via hole. Fill the inside of the hole and apply so as to cover the entire surface of the substrate, expose and develop the resist using a mask having an opening at a required portion, and leave the resist only in the via hole forming hole, and perform heat treatment. Then, the resist is deformed to flatten the level difference of the holes for forming via holes on the surface of the substrate, a lower layer resist for plating is formed on the active element formation portion, and the entire surface of the substrate is used as a power supply layer for electrolytic plating. A metal film is formed, and an upper layer resist that serves as a mask during electrolytic plating for forming a plated electrode and plated wiring is formed. Then, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Only the portion immediately below the hole forming hole is processed until the via hole forming hole opens from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole and the substrate. Since the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface. Therefore, it is possible to prevent the underlying pattern of the active element and the like from being exposed, and the resist used when forming the plating electrode and the plating wiring is the via hole. Since it can be prevented from remaining in the production holes, and a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form a high-potential resist simultaneously with the formation of the plating electrode. Accurate plated wiring can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. You can

Further, in the semiconductor device according to the present invention (claim 9), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is formed inside the via hole forming hole. It is filled and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening in a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. Deform the resist to flatten the step of the via hole forming hole on the substrate surface, form a plating electrode and plating wiring on the substrate surface, and process the entire back surface of the substrate until the via hole forming hole opens from the back surface. To form a via hole, remove the resist filled in the via hole, and form a metal film on the inner surface of the via hole and the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface and improves the coverage of the active elements and the like. It is possible to prevent the pattern from being exposed, and to prevent the resist when forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further to form the plated electrode and the plated wiring. Since a high-resolution positive type photoresist can be used as a resist for this purpose, highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the semiconductor device according to the present invention (claim 10), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via hole forming hole. It is filled and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening in a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed to Deform the resist to flatten the step of the via hole forming hole on the substrate surface, form a plating electrode and plating wiring on the substrate surface, and process the entire back surface of the substrate until the via hole forming hole opens from the back surface. To form a via hole, remove the resist filled in the via hole, and completely fill the inside of the via hole with a metal film. Since the metal film is formed, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the substrate surface, which improves the coverage of the active elements formed on the substrate surface. It is possible to prevent the underlying pattern of the active element, etc. from being exposed, and to prevent the resist when forming the plating electrode and the plating wiring from remaining in the via hole forming hole. Since a high-resolution positive type photoresist can be used as the resist for forming the electrodes and the plated wiring, it is possible to form the plated wiring with high precision simultaneously with the formation of the plated electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the semiconductor device according to the present invention (claim 11), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via hole forming hole. It is filled and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening in a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, Only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is filled. Since the resist was removed and a metal film was formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface is uniformly applied. As a result, coverage of the active element formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active element or the like from being exposed, and the resist for forming the plating electrode and the plating wiring is It is possible to prevent the via holes from remaining in the via hole forming holes, and further, since a high resolution positive type photoresist can be used as a resist for forming the plated electrodes and the plated wirings, it is possible to form the plated electrodes. At the same time, highly accurate plated wiring can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Furthermore, the entire semiconductor substrate is thick enough to maintain its mechanical strength (for example, 10
0 μm), and the mechanical strength during handling of the semiconductor substrate can be improved.

Further, in the semiconductor device according to the present invention (claim 12), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via hole forming hole. It is filled and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening in a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, Only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is filled. The resist was removed, the inside of the via hole was completely filled with a metal film, and the metal film was formed on the back surface of the substrate. The resist can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface, prevents the underlying pattern of the active elements and the like from being exposed, and prevents the plating electrodes and plating wiring from being exposed. It is possible to prevent the resist at the time of forming from remaining in the via hole forming hole, and further, a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring. Therefore, highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

In the method for manufacturing a semiconductor device according to the present invention (claim 13), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, the resist is filled in the recess, and the entire surface of the substrate is covered. It is applied so as to cover it, and the step of the concave portion of the substrate surface is flattened by removing the resist on the unnecessary portion of the substrate surface by the etch-back method, and in that state, the plated electrode and the plated wiring are formed, and then the above Since the resist filled in the concave portion is removed, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the substrate surface, and thus the coverage of the active element formed on the substrate surface can be improved. It is possible to prevent the exposure of the underlying pattern such as the active element, and also to prevent the formation of the plating electrode and the plating wiring. It is possible to prevent the resist from remaining in the concave portion, and further, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to simultaneously form the plated electrode. Highly accurate plated wiring can be formed. Further, since the unnecessary portion of the resist filled in the concave portion is removed by the etch back, the step on the substrate surface can be made more flat and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. .

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 14), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to obtain a resist component. By applying a solvent of the same component as the solvent to the surface of the semiconductor substrate, applying a resist to the surface of the semiconductor substrate before the applied solvent dries, and removing the resist on the unnecessary portion of the substrate surface by the etch back method. By flattening the steps of the recesses on the substrate surface, forming the plating electrodes and plating wiring on the substrate surface in that state, and then removing the resist filling the recesses, the plating electrodes and plating wiring were formed on the substrate surface. When forming the resist, it is possible to apply the resist uniformly, which improves the coverage of the active elements formed on the substrate surface, It is possible to prevent the underlying pattern of the moving element and the like from being exposed, and it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the recesses. Since a high-resolution positive type photoresist can be used as a resist for forming, a highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Further, since the unnecessary portion of the resist filled in the concave portion is removed by the etch back, the step on the substrate surface can be made more flat and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. . Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled with resist,
The surface of the substrate can be flattened more reliably.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 15), a recess is formed in the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200W to 300W for 10 to 10W. Perform for 30 seconds, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, and remove the substrate surface by the etch back method. By removing the resist of the part, the step of the concave portion of the substrate surface is made flat, and in that state the plating electrode and the plating wiring are formed, and then the resist filled in the concave portion is removed. It is possible to evenly apply the resist when forming the plating electrode and the plating wiring on the surface, and thus the cover of the active element formed on the substrate surface. Tsu di is improved, it is possible to prevent the underlying pattern, such as active elements are exposed, also,
It is possible to prevent the resist at the time of forming the plating electrode and the plating wiring from remaining in the recesses, and further, to use a high-resolution positive type photoresist as the resist for forming the plating electrode and the plating wiring. Therefore, it is possible to form a highly accurate plated wiring simultaneously with the formation of the plated electrode. Further, since the unnecessary portion of the resist filled in the concave portion is removed by the etch back, the step on the substrate surface can be made more flat and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. . Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and a high-viscosity resist can easily flow into the recess deep in the semiconductor substrate surface and having a small opening diameter,
As a result, the concave portion of the semiconductor substrate can be completely filled with the resist, and the substrate surface can be more surely flattened.

In the method of manufacturing a semiconductor device according to the present invention (claim 16), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
A via hole is formed on the substrate surface by filling the inside of the via hole forming hole with a resist and applying it so as to cover the entire surface of the substrate, and removing the unnecessary portion of the resist on the substrate surface by an etchback method. , The lower layer for plating is formed on the active element formation portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and electrolytic plating is performed to form a plating electrode and plating wiring. An upper layer resist to be a mask at the time is formed, and only the openings of the upper layer resist are selectively electroplated, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, and the lower layer resist is removed. The substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. And the inner surface of the via hole, and it is so arranged to form a metal film on the rear surface of the substrate,
It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element and the like. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole. Furthermore, as a resist for forming the plated electrode and the plated wiring, Since a positive photoresist of resolution can be used, highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The tolerance can be increased.

In the method of manufacturing a semiconductor device according to the present invention (claim 17), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
A via hole is formed on the substrate surface by filling the inside of the via hole forming hole with a resist and applying it so as to cover the entire surface of the substrate, and removing the resist on the unnecessary portion of the substrate surface by an etch back method. , The lower layer resist for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and the plating electrode and the plating wiring are formed. An upper layer resist to be a mask at the time is formed, and only the openings of the upper layer resist are electrolytically plated, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, and the lower layer resist is removed. The entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is filled. Since the strike is removed and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface can be uniformly applied. As a result, the coverage of active elements formed on the surface of the substrate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plated electrodes and the plated wiring is the via holes described above. Since it can be prevented from remaining in the formation hole, and furthermore, a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming hole are allowed. You can increase the degree. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

In the method of manufacturing a semiconductor device according to the present invention (claim 18), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
A via hole is formed on the substrate surface by filling the inside of the via hole forming hole with a resist and applying it so as to cover the entire surface of the substrate, and removing the resist on the unnecessary portion of the substrate surface by an etch back method. , The lower layer for plating is formed on the active element formation portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and electrolytic plating is performed to form a plating electrode and plating wiring. An upper layer resist to be a mask at the time is formed, and only the openings of the upper layer resist are electrolytically plated, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, and the lower layer resist is removed. , The entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is formed as a via hole forming hole. Since the via hole is formed by processing from the back surface to the opening, the resist filled in the via hole is removed, and the metal film is formed on the inner surface of the via hole and the back surface of the substrate. Resist can be applied uniformly when forming plating electrodes and plating wiring on the surface, which improves coverage of active elements formed on the substrate surface and prevents exposure of underlying patterns such as active elements. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring. Since a positive image type photoresist can be used, high-precision plated wiring can be formed simultaneously with the formation of plated electrodes. It is possible.
Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming hole are allowed. You can increase the degree. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 19), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and the resist is used for forming the via hole. Filling the inside of the hole and coating so as to cover the entire surface of the substrate, and removing the resist on the unnecessary portion of the surface of the substrate by an etch-back method to flatten the step of the via-hole forming hole on the substrate surface, A lower resist for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper resist serving as a mask during electrolytic plating for forming plating electrodes and wiring. And selectively electrolytically plating only the openings of the upper layer resist to remove the upper layer resist and remove unnecessary portions of the power feeding layer. The lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength,
Only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole is formed. Also, since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied to the surface of the substrate, and the active element formed on the surface of the substrate is thereby formed. Coverage is improved, and it is possible to prevent the underlying pattern of active elements and the like from being exposed.
It is possible to prevent the resist at the time of forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type photoresist. Therefore, it is possible to form high-precision plated wiring simultaneously with the formation of the plated electrode. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming hole are allowed. You can increase the degree. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. You can

Further, in the semiconductor device according to the present invention (claim 20), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via-hole forming hole. Filling and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the substrate surface by the etch-back method, to flatten the steps of the via-hole forming holes on the substrate surface,
A plating electrode and a plating wiring are formed on the surface of the substrate, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active elements formed on the surface of the substrate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring is used as the via hole forming holes. It is possible to prevent it from remaining, and furthermore, as a resist for forming plated electrodes and plated wiring, a high-resolution positive type photo resist. It is possible to use a resist, it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The tolerance can be increased. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the semiconductor device according to the present invention (claim 21), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via hole forming hole. Filling and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the substrate surface by the etch-back method to flatten the step of the via hole forming hole on the substrate surface,
A plating electrode and a plating wiring are formed on the surface of the substrate, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Since the inside of the via hole is completely filled with the metal film and the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the surface of the substrate is uniformly applied. As a result, the coverage of active elements formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring is improved. It can be prevented from remaining in the via hole forming hole, and has a high resolution as a resist for forming a plated electrode and a plated wiring. It is possible to use a positive type photoresist, it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The tolerance can be increased. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the semiconductor device according to the present invention (claim 22), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via-hole forming hole. Filling and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the substrate surface by the etch-back method, to flatten the steps of the via-hole forming holes on the substrate surface,
Form the plated electrode and the plated wiring on the surface of the substrate, process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and only the portion directly below the via hole forming hole of the substrate from the back surface Since the via hole is formed by processing until it is opened, the resist filled in the via hole is removed, and the metal film is formed on the inner surface of the via hole and the back surface of the substrate. It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate, which improves the coverage of the active elements formed on the substrate surface and prevents the underlying pattern of the active elements from being exposed. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via hole forming hole. A, it is possible to use a positive type photoresist of high resolution as a resist for forming a plating electrode and plating wiring, it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The tolerance can be increased. Furthermore, the entire semiconductor substrate has a thickness (for example, 100
μm), and the mechanical strength during handling of the semiconductor substrate can be improved.

Further, in the semiconductor device according to the present invention (claim 23), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is provided inside the via-hole forming hole. Filling and coating so as to cover the entire surface of the substrate, by removing the resist of the unnecessary portion of the substrate surface by the etch-back method, to flatten the steps of the via-hole forming holes on the substrate surface,
Form the plated electrode and the plated wiring on the surface of the substrate, process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and only the portion directly below the via hole forming hole of the substrate from the back surface to the via hole forming hole. Form a via hole by processing until it is opened, remove the resist filled in the via hole, completely fill the inside of the via hole with a metal film, and form a metal film on the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface,
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plated electrodes and the plated wiring can form the via holes. Since it can be prevented from remaining in the holes for use, and a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, high precision can be achieved at the same time when the plating electrode is formed. The plated wiring can be formed. Further, since unnecessary portions of the resist filled in the via hole forming holes are removed by etch back, the steps on the substrate surface can be made more flat, and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The tolerance can be increased. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.
Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 24), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and the resist component A solvent of the same component as the solvent is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and the steps on the surface of the substrate are flattened by leaving the resist only in the recesses, In that state, the plating electrode and the plating wiring were formed on the surface of the substrate, and then the resist filled in the recess was removed, so that the resist for forming the plating electrode and the wiring on the surface of the substrate was uniformly applied. This improves the coverage of the active elements formed on the substrate surface and prevents the underlying pattern of the active elements from being exposed. In addition, it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the recesses, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type resist can be used. Since photoresist can be used,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled, and the substrate surface can be flattened more reliably.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 25), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W for 10 to 10. Perform for 30 seconds, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, leaving the resist only in the recessed portion Since the steps on the substrate surface are made flat and plating electrodes and plating wirings are formed on the substrate surface in that state, and then the resist filling the recesses is removed, the plating electrodes and plating wirings are formed on the substrate surface. It is possible to apply the resist evenly, which improves the coverage of the active elements formed on the surface of the substrate. Exposing can be prevented, also resist when forming a plating electrode and plating wiring can be prevented from remaining in the recess,
Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated wiring with high precision simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled with
The surface of the substrate can be flattened more reliably.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 26), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and the resist component A solvent having the same components as the solvent is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the resist is exposed and developed using a mask having openings at required portions. And leave the resist only in the recesses, and heat-treat it to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state form the plating electrodes and plating wirings, and then fill the recesses. Since the resist is removed, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active elements formed on the surface of the substrate is improved, the underlying pattern of the active elements and the like can be prevented from being exposed, and the resist for forming the plated electrodes and the plated wiring remains in the recesses. It is possible to prevent this, and since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Furthermore, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described action can be made more reliable. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and a high-viscosity resist can easily flow into the recess deep in the semiconductor substrate surface and having a small opening diameter,
As a result, the concave portion of the semiconductor substrate can be completely filled with the resist, and the substrate surface can be more surely flattened.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 27), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and the resist component A solvent having the same components as the solvent is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the resist is exposed and developed using a mask having an opening at a required portion. And leave the resist only in the recesses, and heat-treat it to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state form the plating electrodes and plating wirings, and then fill the recesses. The resist which has not been glass-transposed at the temperature of the subsequent heat treatment is used as the resist to be filled in the concave portion. Because it was Unishi generates no change in volume expansion rate due to the glass transition of the resist, the control of the flatness of the substrate can be facilitated.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 28), a concave portion is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment so that the resist component in the resist component is removed. By applying a solvent of the same component as the solvent to the surface of the semiconductor substrate, applying a resist to the surface of the semiconductor substrate before the applied solvent dries, and removing the resist on the unnecessary portion of the substrate surface by the etch back method. , The step of the recess on the surface of the substrate is made flat, the plating electrode and the plating wiring are formed on the surface of the substrate in that state, and then the resist filled in the recess is removed. Resist can be applied evenly when forming wiring, which improves coverage of active devices formed on the substrate surface. Therefore, it is possible to prevent the underlying pattern of the active element and the like from being exposed, and it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the recesses. Since a high-resolution positive type photoresist can be used as the resist for forming the wiring, it is possible to form the plated wiring with high precision at the same time when the plated electrode is formed. Further, since the unnecessary portion of the resist filled in the concave portion is removed by the etch back, the step on the substrate surface can be made more flat and the above-mentioned action can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. . further,
The affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter, thereby completely filling the recess in the semiconductor substrate with the resist. Therefore, the surface of the substrate can be flattened more reliably.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 29), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
The semiconductor substrate surface is subjected to oxygen plasma treatment, a solvent having the same component as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and the via Leave the resist only in the hole forming holes to flatten the steps on the substrate surface,
A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. Form a resist,
Electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the substrate is formed with a via hole forming back surface. To form a via hole by processing until it is opened, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring, which improves the coverage of the active element formed on the substrate surface and prevents the underlying pattern of the active element or the like from being exposed. Yes, again
It is possible to prevent the resist at the time of forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type photoresist. Therefore, it is possible to form high-precision plated wiring simultaneously with the formation of the plated electrode. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 30), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
The semiconductor substrate surface is subjected to oxygen plasma treatment, a solvent having the same component as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and the via Leave the resist only in the hole forming holes to flatten the steps on the substrate surface,
A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. Form a resist,
Electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is used for forming via holes. Forming a via hole by processing until the hole is opened from the back surface, removing the resist filled in the via hole, to form a metal film on the inner surface of the via hole, and the back surface of the substrate,
It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element and the like. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole. Furthermore, as a resist for forming the plated electrode and the plated wiring, Since a positive photoresist of resolution can be used, highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 31), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed,
The semiconductor substrate surface is subjected to oxygen plasma treatment, a solvent having the same component as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and the via Leave the resist only in the hole forming holes to flatten the steps on the substrate surface,
A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. Form a resist,
Electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate has mechanical strength. Process to a thickness that can be sufficiently maintained, and process only the portion directly below the via hole forming hole of the substrate until the via hole forming hole opens from the back surface to form a via hole, and remove the resist filled in the via hole. Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist for forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active elements formed on the substrate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the plated electrodes and the plated wirings can be prevented. It is possible to prevent the resist at the time of forming from remaining in the via hole forming hole, and further, a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring. Therefore, highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. In addition, the entire semiconductor substrate must be thick enough to maintain its mechanical strength (for example, 100 μm).
m) can be provided, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 32), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and oxygen plasma is formed on the surface of the semiconductor substrate. After the treatment, a solvent having the same composition as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and the resist is applied only to the via hole forming holes. To flatten the step on the surface of the substrate, and form a lower layer resist for plating on the active element forming portion,
A metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plated wiring is formed, and only the opening of the upper layer resist is selectively formed. Electrolytic plating, removing the upper layer resist, removing unnecessary portions of the power supply layer, removing the lower layer resist, and processing the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength, Only the portion directly below the via hole forming hole is processed until the via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, the via hole inner surface, and the substrate. Since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface can be uniformly applied. As a result, the coverage of the active elements formed on the surface of the substrate is improved, the underlying pattern of the active elements and the like can be prevented from being exposed, and the resist used for forming the plated electrodes and the plated wirings is used for forming the via holes. Since it can be prevented from remaining in the holes, and a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high accuracy at the same time. Plated wiring can be formed. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. In addition, the entire semiconductor substrate must be thick enough to maintain its mechanical strength (for example, 100 μm).
m) can be provided, and the mechanical strength at the time of handling a semiconductor substrate, which is particularly problematic for a GaAs substrate which is fragile in material, can be improved.

Further, in the semiconductor device according to the present invention (claim 33), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen plasma treatment is performed on the surface of the semiconductor substrate. , Applying a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate,
Before the applied solvent dries, a resist is applied to the surface of the semiconductor substrate, the resist is left only in the via-hole forming holes to flatten the steps on the surface of the substrate, and a plating electrode and plating wiring are formed on the surface of the substrate. Then, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed, the via hole inner surface,
Also, since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied to the surface of the substrate. The coverage of the device is improved, the underlying pattern of the active device, etc. can be prevented from being exposed, and the resist at the time of forming the plating electrode and the plating wiring is prevented from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. . Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the semiconductor device according to the present invention (claim 34), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen plasma treatment is performed on the surface of the semiconductor substrate. , Applying a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate,
Before the applied solvent dries, a resist is applied to the surface of the semiconductor substrate, the resist is left only in the via-hole forming holes to flatten the level difference on the surface of the substrate, and a plating electrode and plating wiring are formed on the surface of the substrate Then, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inside of the via hole is completely covered with a metal film. Since the metal film is filled and the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the plating electrode and the plating wiring are formed. Resist can be prevented from remaining in the via hole forming hole, further, since it is possible to use a high-resolution positive type photoresist as a resist for forming a plating electrode and plating wiring, High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the semiconductor device according to the present invention (claim 35), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen plasma treatment is performed on the surface of the semiconductor substrate. , Applying a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate,
Before the applied solvent dries, a resist is applied to the surface of the semiconductor substrate, the resist is left only in the via-hole forming holes to flatten the level difference on the surface of the substrate, and a plating electrode and plating wiring are formed on the surface of the substrate Then, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole. Since the resist filled in the via hole is removed and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, when the plating electrode and the plating wiring are formed on the substrate surface, The resist can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface and exposes the underlying pattern of the active elements, etc. It is possible to prevent the resist from remaining in the via hole forming hole when forming the plated electrode and the plated wiring, and to further form the plated electrode and the plated wiring. Since a high-resolution positive type photoresist can be used as the resist, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the semiconductor device according to the present invention (claim 36), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and oxygen plasma treatment is performed on the surface of the semiconductor substrate. , Applying a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate,
Before the applied solvent dries, a resist is applied to the surface of the semiconductor substrate, the resist is left only in the via-hole forming holes to flatten the steps on the surface of the substrate, and a plating electrode and plating wiring are formed on the surface of the substrate. Then, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole. The resist filled in the via hole is removed, the inside of the via hole is completely filled with a metal film, and the metal film is formed on the back surface of the substrate. The resist used for forming the wiring can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface and improves the coverage under the active elements. It is possible to prevent the pattern from being exposed, and to prevent the resist when forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further to form the plated electrode and the plated wiring. Since a high-resolution positive type photoresist can be used as a resist for this purpose, it is possible to form a highly accurate plated wiring simultaneously with the formation of the plated electrode. Furthermore, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. The holes for forming via holes of the substrate can be completely filled with the resist, and the surface of the substrate can be more surely flattened. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 37), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a recess is formed in the resist. Exposure and development are performed using a mask that forms a resist pattern having an opening, an etching mask is created, the insulating film is etched using the etching mask, and a recess is formed on the substrate surface using the same etching mask. Then, the resist used for the etching mask is removed, and the recess is filled by growing a crystal using the insulating film as a mask to flatten the substrate surface, and the insulating film used as the mask during selective crystal growth is removed. Then, the active element is formed on the surface of the substrate, the plating electrode and the plating wiring are formed on the surface of the substrate, and the crystallization is performed. Since the crystal filled in the concave portion is removed by the method described above, the resist for forming the plating electrode and the plating wiring can be uniformly applied to the surface of the substrate, and the active element formed on the surface of the substrate can be coated with the resist. The coverage is improved, it is possible to prevent the underlying pattern of the active element or the like from being exposed, and it is possible to prevent the resist at the time of forming the plating electrode and the plating wiring from remaining in the recesses. Since a high-resolution positive type photoresist can be used as the resist for forming the electrodes and the plated wiring, it is possible to form the plated wiring with high precision simultaneously with the formation of the plated electrode. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 38), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a hole forming position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Forming, selectively electrolytically plating only the openings of the upper layer resist, removing the upper layer resist, removing unnecessary portions of the power feeding layer, removing the lower layer resist, and forming the substrate for via hole formation. The via hole is formed by processing until the hole opens from the back surface, and the crystal filled in the via hole is removed by crystal growth. Also, since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the surface of the substrate, and the active element formed on the surface of the substrate can be coated with the resist. The coverage is improved, and it is possible to prevent the underlying pattern of the active element or the like from being exposed. Also, it is possible to prevent the resist when forming the plating electrode and the plating wiring from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated wiring with high precision simultaneously with the formation of the plated electrode. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved.

In the method of manufacturing a semiconductor device according to the present invention (claim 39), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a hole forming position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Then, electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is via-formed. Form a via hole by processing until the hole forming hole opens from the back side,
Since the crystal filled in the via hole is removed by crystal growth and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, when the plating electrode and the plating wiring are formed on the substrate surface, The resist can be applied uniformly, which improves the coverage of the active elements formed on the surface of the substrate, prevents the underlying pattern of the active elements and the like from being exposed, and also prevents the plating electrodes and plating wiring from being exposed. It is possible to prevent the resist at the time of forming from remaining in the via hole forming hole, and it is possible to use a high-resolution positive type photoresist as the resist for forming the plated electrode and the plated wiring. Therefore, highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Furthermore, there is no problem of flatness control due to alteration of the material of the filling resist or modification of the filling resist due to heating process,
The reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

Further, in the method of manufacturing a semiconductor device according to the present invention (claim 40), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a hole forming position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. The via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole forming hole and the substrate surface. Is flattened, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. Forming a lower layer resist for plating on the active element forming portion, forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming a plating electrode and a plating wiring, which serves as a mask during electrolytic plating An upper layer resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist,
Unnecessary parts of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Form a via hole by processing until the hole opens from the back surface, remove the crystal filled in the via hole by crystal growth, and form a metal film on the inner surface of the via hole and the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface and exposes the underlying pattern of the active elements and the like. Of the via hole and the resist used for forming the plated electrode and the plated wiring is prevented from remaining in the via hole forming hole. Can be further it is possible to use a positive type photoresist of high resolution as a resist for forming a plating electrode and plating wires,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 41), an insulating film is formed on the surface of the GaAs substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a hole forming position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. The via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole forming hole and the substrate surface. Is flattened, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist,
Unnecessary parts of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Form a via hole by processing until the hole opens from the back surface, remove the crystal filled in the via hole by crystal growth, and form a metal film on the inner surface of the via hole and the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface and exposes the underlying pattern of the active elements and the like. Of the via hole and the resist used for forming the plated electrode and the plated wiring is prevented from remaining in the via hole forming hole. Can be further it is possible to use a positive type photoresist of high resolution as a resist for forming a plating electrode and plating wires,
High-precision plating wiring can be formed simultaneously with the formation of the plating electrode. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. You can

Further, in the method for manufacturing a semiconductor device according to the present invention (claim 42), an insulating film is formed on the surface of the GaAs substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a hole forming position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the insulating film is used as a mask for Ga
In Selective for wet etching of substrates
GaP is selectively grown to fill the via hole forming hole to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the substrate is a via hole. A via hole is formed by processing until the formation hole opens from the back surface, and InGaP filled in the via hole is removed by crystal growth with hydrochloric acid. Since the metal film is formed on the inner surface of the hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the resist for forming the plating electrode and the plating wiring can be prevented from remaining in the via hole forming hole. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. You can Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Furthermore, since InGaP has wet etching selectivity with respect to the GaAs substrate, it can be easily removed from the via hole with hydrochloric acid.

Further, in the semiconductor device according to the present invention (claim 43), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole forming position is formed with respect to the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening in the substrate, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface to a predetermined depth. A hole for forming a via hole is removed by etching, the resist used as the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole to flatten the surface of the substrate. The insulating film used as a mask during growth is removed, active elements are formed on the surface of the substrate, and the active film is formed on the surface of the substrate. An electrode and plated wiring are formed, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the crystal filled in the via hole is removed by crystal growth. Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the substrate surface, which allows the substrate surface to be formed. The coverage of the active element formed on the substrate is improved, and the underlying pattern of the active element can be prevented from being exposed, and the resist for forming the plated electrode and the plated wiring remains in the via hole forming hole. In addition, a positive-type photoresist with high resolution can be used as a resist for forming the plated electrode and the plated wiring. It is possible to use the door, it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified.

In the semiconductor device according to the present invention (claim 44), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole forming position is formed on the resist. An etching mask is created by exposing and developing using a mask for forming a resist pattern having an opening in the substrate, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface to a predetermined depth. A hole for forming a via hole is removed by etching, the resist used for the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole to flatten the surface of the substrate and select crystals. The insulating film used as a mask during growth is removed, active elements are formed on the surface of the substrate, and the active film is formed on the surface of the substrate. An electrode and a plated wiring are formed, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the crystal filled in the via hole is removed by crystal growth. Since the inside of the via hole is completely filled with the metal film and the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. This makes it possible to improve the coverage of the active elements formed on the surface of the substrate and prevent the underlying pattern of the active elements from being exposed.
It is possible to prevent the resist at the time of forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type photoresist. Therefore, it is possible to form high-precision plated wiring simultaneously with the formation of the plated electrode. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when forming the via hole from the via hole forming hole, the processing of the back surface of the substrate can be simplified. Further, compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, in the semiconductor device according to the present invention (claim 45), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole forming position is formed with respect to the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening in the substrate, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface to a predetermined depth. A hole for forming a via hole is removed by etching, the resist used for the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole to flatten the substrate surface, The insulating film used as a mask during crystal growth is removed, active elements are formed on the substrate surface, and Kick electrodes and plated wiring are formed, and the entire back surface of the board is processed to a thickness that can maintain sufficient mechanical strength. The via surface is processed to form a via hole, the crystal filled in the via hole is removed by crystal growth, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. Resist can be applied evenly when forming plating electrodes and plating wiring on
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plated electrodes and the plated wiring can form the via holes. Since it can be prevented from remaining in the holes for use, and a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, high precision can be achieved at the same time when the plating electrode is formed. The plated wiring can be formed. Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

Further, in the semiconductor device according to the present invention (claim 46), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied over the entire surface of the insulating film, and a via hole forming hole forming position is formed with respect to the resist. An etching mask is created by exposing and developing using a mask for forming a resist pattern having an opening in the substrate, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface to a predetermined depth. A hole for forming a via hole is removed by etching, the resist used for the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole and flatten the surface of the substrate. The insulating film used as a mask during crystal growth is removed, an active element is formed on the substrate surface, and Kick electrodes and plated wiring are formed, and the entire back surface of the board is processed to a thickness that can maintain sufficient mechanical strength, and only the portion directly below the via hole formation hole of the board is opened until the via hole formation hole opens from the back surface. Forming a via hole by processing, removing the crystal filled in the via hole by crystal growth, completely filling the inside of the via hole with a metal film, and forming a metal film on the back surface of the substrate Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface and the underlying pattern of the active elements and the like. It is possible to prevent the resist from being exposed, and to prevent the resist used when forming the plated electrode and the plated wiring from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time when the plated electrode is formed. . Further, there is no problem of flatness control due to alteration of the material of the filling resist and no problem of denaturation of the filling resist due to the heating step, and the reliability of the manufacturing process can be improved. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved. further,
As compared with the case where the inside of the via hole is not completely filled with the metal film, heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

In the resist coating method according to the present invention (claim 47), the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and the solvent having the same component as the solvent in the resist component is coated on the surface of the semiconductor substrate. Since the resist is applied to the surface of the semiconductor substrate before the solvent is dried, the affinity of the resist with the semiconductor substrate is improved so that a highly viscous resist can be easily formed in a deep recess of the semiconductor substrate surface with a small opening diameter. It is possible to inflow, so that the above-mentioned concave portion of the semiconductor substrate can be completely filled with the resist.

According to the resist coating method of the present invention (claim 48), the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W for 10 to 30 seconds, and the same solvent as the solvent in the resist component is added to the above semiconductor. Apply on the substrate surface,
Since the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, the affinity of the resist with the semiconductor substrate is improved so that a high-viscosity resist is formed in a deep recess of the semiconductor substrate surface with a small opening diameter. It can easily flow in, so that the recesses of the semiconductor substrate can be completely filled with resist.

[0137]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a device sectional view of a semiconductor device having a via hole according to an embodiment of the present invention.
101 is a GaAs substrate, 102 is a source electrode of FET formed on the surface of the GaAs substrate 101, 103 is a drain electrode, 104 is a gate electrode, and 105 is penetrating from the front surface to the back surface of the GaAs substrate 101 and is adjacent to the source electrode 102. Dry-etch type via hole, 106 covers the surface opening of the via hole 105, and the power supply layer for plating of the via hole in contact with the source electrode 102, 107 overlaps and covers the upper part of the power supply layer 106 for plating, and for plating A plating electrode of a dry-etch type via hole portion connected to the source electrode 102 through the power feeding layer 106,
Reference numeral 108 denotes a PHS which is formed on the back surface of the substrate 101 and inside the via hole 105 by an electrolytic plating method and is in contact with the plating power supply layer 106 at the via hole 105 surface opening.

2 to 5 show a method of manufacturing a semiconductor device having a via hole according to the first embodiment of the present invention. In the figures, the same reference numerals as those in FIG. A resist used as a mask for forming a hole for forming a via hole from the substrate surface, 110 is a hole for forming a via hole, 111 is a filling resist for temporarily filling a resist in the hole for forming a via hole 110 and planarizing it. ,
112 is the resist that remains after exposure and development using a mask that leaves the resist only in the holes for forming via holes, 113 is the resist whose shape has been changed by heat treatment, 11
4 is a lower layer resist for connecting to the source electrode 102 to form the plated electrode 107 and plated wiring in the via hole portion, 115 is an upper layer resist for forming the plated electrode 107 and plated wiring in the via hole portion, and 121 is a filling The solvent has the same composition as the solvent of the resist 111 for use.

FIGS. 6 and 7 are detailed diagrams of the step of forming the plated wiring in the method of manufacturing a semiconductor device having a via hole according to the first embodiment of the present invention. The wiring is shown as an example together with the plated electrode 107 in the via hole.
The same reference numerals as those in FIGS. 2 to 5 denote the same or corresponding portions, and 120 is a plated wiring connected to the drain electrode 103.

A manufacturing method will be described with reference to FIGS. 2 to 5 and, if necessary, FIGS. 6 to 7 in the plating wiring step. First, as shown in Fig. 2 (a), GaAs
FET source electrode 102 and drain electrode 10 on the surface of substrate 101
3, the gate electrode 104 is formed. Next, the source electrode 102
A resist 109 for forming holes for forming via holes is formed with high accuracy (FIG. 2 (b)). Then, using the resist 109 as a mask, the GaAs substrate 101 is etched by anisotropic dry etching to a depth of, for example, 30 μm.
A via hole forming hole 110 having an opening diameter of 8 to 10 μm is formed (FIG. 2 (c)).

Next, the resist 109 is removed (see FIG. 2D).
), The surface of the GaAs substrate 101 is treated with oxygen plasma at a low output for a short time (for example, 10 seconds at 200 W) in order to fill the via hole forming hole 110 with the resist without gaps (see FIG. 2).
(e)) and then the via hole filling resist 111
A solvent 121 having the same composition as the solvent in the composition is applied to the surface of the GaAs substrate 101 (FIG. 3 (a)), and before the applied solvent dries,
Apply resist 111 to the surface of GaAs substrate 101 (Fig. 3 (b))
).

As the resist 111 used here, a resist which does not undergo glass transition at the temperature of the subsequent heat treatment is used. This is the resist 111 filled in the via hole forming hole 110.
This is because the volume expansion coefficient is changed due to the glass transition of, so that the volume of the filled resist 111 cannot be controlled and the controllability of the flatness of the substrate is deteriorated.
The resist used varies depending on the temperature required for the subsequent heat treatment. For example, a novolac-based resist has a glass transition temperature of about 160 ° C,
The temperature is 200 to 230 ° C for PMMA for EB, and 220 to 230 ° C for polyimide resist. By using a resist having a high glass transition temperature, the degree of freedom in the temperature of heat treatment in the subsequent manufacturing steps becomes high. Further, since this filling resist 111 fills a hole for forming a via hole having a depth of 30 μm, for example, the solid component needs to have a high viscosity of, for example, 50% or more.

Then, the mask is aligned again so that the resist is selectively left only in the via hole forming holes 110.
111 is exposed and developed, and the resist 111 filled only in the via hole forming hole 110 is used as the resist 112 (FIG. 3).
(c)). However, at this time, a gap of about 1 to 2 μm is formed between the via hole forming hole 110 and the filling resist 112, which is an alignment margin for mask alignment. Therefore, if the filling resist 112 is, for example, a novolac-based resist, then 10
By baking the resist 112 for 60 to 90 minutes at 0 to 120 ° C., the resist 112 is heated to form the resist 113, and the gap is filled (FIGS. 3D and 6A).

Next, a plating lower layer resist 114 for forming the plating electrode 107 and the plating wiring 120 in the via hole portion is formed (FIGS. 3 (e) and 6 (b)). The resist used here is the via hole forming hole 110.
Since the step is flattened by being filled with 113, it is possible to use a positive type resist capable of realizing high resolution instead of the negative type resist as in the conventional method.

Next, a power supply layer 106 for plating is formed on the entire surface of the substrate for use in electrolytic plating in the next step (FIG. 4).
(A) and FIG.6 (c)). Since the power supply layer 106 uses gold-based plating for electrolytic plating, a gold-based metal thin film such as TiAu that can be stably formed in the process is used.
Further, as the forming method, a sputtering method is adopted so that the step difference of the plating lower layer resist 114 can be surely covered. Next, an upper layer resist 115 that serves as a mask for electrolytic plating when forming the plating electrode 107 and the plating wiring 120 in the via hole is formed on the plating power supply layer 106 (FIGS. 4B and 6D). )). As the resist used at this time, a high-resolution positive type resist can be used like the lower layer resist for plating, and therefore a highly accurate wiring pattern can be formed.

Next, using the upper layer resist 115 prepared above, the source electrode 102 of the FET is connected to the plating electrode 107 and the drain electrode 103 of the dry-etch type via hole portion connected via the power feeding layer 106 for plating. Plated wiring 12
0 (FIG. 4 (c) and FIG. 6 (e)). The wiring thickness to be formed needs to be at least 2 μm or more to prevent electromigration.

Next, the upper layer resist 115 is removed (see FIG.
(d) and FIG. 7 (a), the unnecessary power feeding layer 106 is removed by ion milling or the like, and the lower layer resist 114 is removed (FIG. 4).
(e) and FIG. 7B), the process of the surface process of the substrate 101 is completed.

Next, regarding the processing on the back surface side of the substrate 101,
Similar to the conventional manufacturing method, after applying an adhesive (for example, wax) to the front surface side of the substrate 101 and sticking it to a reinforcing plate such as a glass plate (not shown), a via hole with a depth of 30 μm from the rear surface side of the substrate 101. The GaAs substrate 101 is processed by grinding or etching until the thickness of the heat-drained resist 113 filled in the formation holes 110 appears, for example, 30 μm, and the via holes 105 are formed (FIG. 5A). Then, the resist filled in the via hole 105
113 is removed from the back surface side of the substrate 101 with a resist stripping solution (FIG. 5 (b)). Finally, backside of substrate 101 and via holes
PHS 108 is formed inside 105 by electrolytic plating to complete the semiconductor device (FIG. 5 (c)).

As described above, according to this embodiment, since the via hole forming hole 110 is temporarily filled with the resist 113, the step on the substrate surface is flattened, and the plating electrode is formed on the substrate surface.
The resist for forming 107 and the plated wiring 120 can be applied uniformly, which improves the coverage of the active elements formed on the surface of the substrate 101 and prevents the underlying pattern of the active elements or the like from being exposed. In addition, the resist for forming the plated electrode 107 and the plated wiring 120 can be prevented from remaining in the via hole forming hole 110, and the resist for forming the plated electrode 107 and the plated wiring 120 can be further prevented. As a high resolution positive type photoresist can be used as
Since the plated wiring 120 can be formed simultaneously with the formation of the plated electrode 107, the manufacturing process can be shortened.

Further, since the resist 113 filled in the via-hole forming hole 110 is deformed by heat treatment, the step on the surface of the substrate 101 can be made more flat and the above-mentioned effect can be more surely achieved.

Further, as the resist 111 to be filled in the via hole forming hole 110, a resist which does not undergo glass transition at the temperature of the subsequent heat treatment is used. It is possible to easily control the flatness of the substrate 101.

Further, when the via hole forming hole 110 is temporarily filled with the resist 111, the GaAs substrate 101 is subjected to oxygen plasma treatment for a short time with a low output, and thereafter, the same component as the solvent in the component of the filling resist 111 is used. The solvent 121 is applied to the GaAs substrate 101, and the resist 111 is applied to the GaAs substrate 101 before the applied solvent 121 dries.
By improving the affinity between the GaAs substrate 101 and the resist 111, the highly viscous resist 111 can easily flow into the via-hole forming hole 110 of the GaAs substrate 101, which allows the via-hole forming hole 110 of the GaAs substrate 101 to have no gap. Resist
111 can be filled with via hole forming holes 110
No cavity is formed in the substrate 101, the surface of the substrate 101 can be made flat more reliably, and the reliability of the semiconductor device manufacturing process is improved.

8 to 11 show a method of manufacturing a semiconductor device having a via hole according to a second embodiment of the present invention. In the drawings, the same symbols as those in FIGS. 2 to 5 show the same or corresponding parts. ing. Further, in the following embodiments, the detailed description of the plated wiring in FIGS. 6 to 7 is omitted because it is the same as in the first embodiment.

Next, the manufacturing method will be described with reference to FIGS. First, the source electrode 102, the drain electrode 103, and the gate electrode 104 are formed in the same process as in the first embodiment, the via hole forming hole 110 is formed, and the GaAs substrate 101 is formed.
Oxygen plasma treatment is applied to the surface and solvent 121 is applied to the GaAs substrate 10.
1 Apply to the surface and apply the resist before the applied solvent dries.
111 is applied to the surface of the GaAs substrate 101 (FIGS. 8 (a) to 9 (b)).

Next, the resist 111 on the unnecessary portion of the GaAs substrate 101 is removed by using the etch back method by oxygen plasma treatment to which sulfur hexafluoride or carbon tetrafluoride is added (FIG. 9 (c)). Therefore, the resist 111 needs to have a high viscosity in order to fill the holes for forming via holes as in Example 1, but does not need to be a resist that does not undergo glass transition at the temperature of the subsequent heat treatment. In addition, there is almost no influence on the already formed active element.

Thereafter, in the same process as in Example 1, a lower layer resist 114, a plating power supply layer 106, and an upper layer resist 115 are sequentially formed (FIGS. 9 (d) to 10 (a)), and a via hole plating electrode is formed. 107 and plated wiring 120 were formed (Fig. 1
After 0 (b), unnecessary parts are removed (Figs. 10 (c) and (d)).
), The GaAs substrate 101 is processed to form a via hole 105 (FIG. 10 (e)), and the filling resist 111 filled in the via hole 105 is removed (FIG. 11 (a)). A PHS 108 is formed on the inner surface of the hole 105 to complete the semiconductor device (FIG. 11 (b)).

In this embodiment, the via hole forming hole 11 is formed.
Since 0 is temporarily filled with the resist 111, the steps on the substrate surface are flattened, and the resist for forming the plating electrodes 107 and the plating wirings 120 can be uniformly applied to the substrate surface. The coverage of the active elements formed on the substrate is improved, the underlying pattern of the active elements and the like can be prevented from being exposed, and the plating electrode 10
7 and the resist for forming the plated wiring 120 can be prevented from remaining in the via hole forming hole 110. Furthermore, as a resist for forming the plated electrode 107 and the plated wiring 120, a high-resolution positive type resist can be used. Since a photoresist can be used, the plated electrode 107
It is possible to form the plated wiring 120 at the same time as the formation of, and to shorten the manufacturing process.

Furthermore, since unnecessary portions of the resist 111 filled in the via hole forming holes 110 are removed by etching back, the steps on the surface of the substrate 101 can be made more flat, and the above-mentioned effects can be more reliably achieved. Further, since the via hole filling resist 111 can be selected regardless of the glass transition temperature, the degree of freedom in the manufacturing process can be improved, and the temperature control during heat treatment and the volume of the via hole filling resist 111 can be controlled. The tolerance of accuracy can be increased.

Furthermore, when the via hole forming hole 110 is temporarily filled with the resist 111, the GaAs substrate 101 is subjected to oxygen plasma treatment at a low output for a short time, and then the same component as the solvent in the component of the filling resist 111 is used. The solvent 121 is applied to the GaAs substrate 101, and the resist 111 is applied to the GaAs substrate 101 before the applied solvent 121 dries.
By improving the affinity between the GaAs substrate 101 and the resist 111, the highly viscous resist 111 can easily flow into the via-hole forming hole 110 of the GaAs substrate 101, which allows the via-hole forming hole 110 of the GaAs substrate 101 to have no gap. Resist
111 can be filled with via hole forming holes 110
No cavities are generated in the substrate 101, the surface of the substrate 101 can be flattened more reliably, and the reliability of the semiconductor device manufacturing process is improved.

12 to 14 show a method of manufacturing a semiconductor device having a via hole according to a third embodiment of the present invention. In the drawings, the same symbols as those in FIGS. 2 to 5 show the same or corresponding portions. , 116 is an insulating film formed on the surface of the semiconductor substrate 101, 117 is an insulating film 116,
A resist serving as a mask for forming the via hole forming hole 110, and 118 are InGaPs selectively grown to temporarily flatten the via hole forming hole 110.

Next, the manufacturing method will be described with reference to FIGS. First, as shown in Fig. 12 (a), GaAs
An insulating film 116 is formed on the surface of the substrate 101. This insulating film 116
Is a very important because it serves as a mask for selective growth of InGaP 118.

Next, a resist 117, which is a resist for forming the via hole forming hole 110 and is also used as a mask when the insulating film 116 is etched, is formed (FIG. 12B). Next, the insulating film 116 is etched using the resist 117 as a mask (FIG. 12 (c)). further,
The GaAs substrate 101 is etched using the resist 117 as a mask to form a via hole forming hole 110 having a depth of 30 μm and an opening diameter of 8 to 10 μm (FIG. 12 (d)), and then the resist 117 is removed (FIG. 12). (e)).

Next, in order to flatten the surface of the substrate 101 on which the via-hole forming holes 110 are formed, InGaP 118 is selectively grown by MOCVD at 650 ° C. using this insulating film 116 as a mask (FIG. 13 (a)). )). Selectively grow here In
GaP 118 does not matter in particular regarding the electrical characteristics of the crystal, but the uniformity of the film thickness is very important.

Next, after removing the insulating film 116 used as the mask during the selective growth (FIG. 13B), active elements such as FETs are formed (FIG. 13C). Next, the lower layer resist 114, the plating power supply layer 106, and the upper layer resist 115 are sequentially formed by the same process as in the first embodiment to form the via hole plating electrode 107 and the plating wiring 120, and then the unnecessary portion is removed. Then, the processing of the substrate 101 surface process is completed (FIG. 13).
(d), (e)).

Next, regarding the processing on the back surface side of the substrate 101,
Similar to Example 1, after applying an adhesive (for example, wax) to the front surface side of the substrate 101 and sticking it to a reinforcing plate such as a glass plate (not shown), a via hole having a depth of 30 μm is formed from the rear surface side of the substrate 101. The GaAs substrate 101 is processed by grinding or etching until the thickness of the InGaP 118 filled in the use hole 110 appears, for example, 30 μm, and the via hole 105 is formed (FIG. 14A). Next, since InGaP has a wet etching selectivity with respect to the GaAs substrate, InGaP 118 grown on the via hole forming hole 110 is grown on the substrate 10.
1 Remove from the back side with hydrochloric acid etc. (Fig. 14 (b)). Finally, the PHS 108 is formed on the back surface of the substrate 101 and inside the via hole 105 by electrolytic plating to complete the semiconductor device (FIG. 14 (c)).

As described above, according to this embodiment, the via hole forming hole 110 is temporarily made of InGa by the selective crystal growth method.
Since it is filled with P 118, the steps on the substrate surface are flattened, and the resist for forming the plating electrode 107 and the plating wiring 120 can be uniformly applied to the substrate surface. The element coverage is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the plating electrode 107 and the plating wiring 12 can be prevented.
The resist for forming 0 is the via hole forming hole 11
It is possible to prevent the residue from remaining at 0, and since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode 107 and the plated wiring 120, it is possible to simultaneously form the plated electrode 107. The plated wiring 120 can be formed, and the manufacturing process can be shortened.

Furthermore, since no resist is used to fill the via-hole forming hole 110, there are problems such as flatness control problems due to alteration of the material of the filled resist and modification of the filled resist due to the heating process. Therefore, the reliability of the manufacturing process can be improved.

Furthermore, the InGaP 118 grown on the crystal is GaAs.
Since the substrate 101 has wet etching selectivity, it can be easily removed from the via hole 105 with hydrochloric acid.

Further, FIGS. 15 (a) to 15 (c) show a fourth embodiment of the present invention. In each of the above-mentioned embodiments, the depth of the via hole forming hole 110 is increased in the step of forming the via hole. Is about 30 μm, the entire GaAs substrate 101 is processed to a thickness of about 30 μm. However, as shown in FIG. 15 (a), the entire GaAs substrate 101 has sufficient mechanical strength, for example, 10
Processed to a thickness of 0 μm, then via hole forming hole 11
0 After masking so that the area directly underneath is selectively etched, only the opening is formed with a via hole forming hole 110.
The resist or crystal filled in the via hole 105 is then formed by selectively etching to a thickness of, for example, 30 μm in which the resist or crystal grown InGaP appears. Grown InGa
By removing P, it is possible to solve mechanical strength problems such as cracks when handling a semiconductor substrate made of a fragile material such as a GaAs substrate, which has been a potential problem until now.

In each of the above embodiments, the PHS108
In the forming process, the PHS 108 is not thickened until the via hole 105 is completely filled, but as the fifth embodiment, for example, as shown in FIG. The heat conductivity may be improved by increasing the thickness of the film.

Further, FIG. 16 (b) shows the PHS 108 of the semiconductor device manufactured in the fourth embodiment thickened until the via hole 105 is completely filled. This has the effect of further improving the mechanical strength of the substrate.

In each of the above embodiments, the via hole forming hole 110 has a depth of 30 μm and an opening diameter of 8 to 10 μm.
Although the GaAs substrate is processed up to 30 μm, the present invention is not limited to this value.

[0173]

As described above, according to the method for manufacturing a semiconductor device of the present invention (claim 1), a recess is formed on the surface of a semiconductor substrate on which an active element is formed, and a resist is filled inside the recess, Further, it is applied so as to cover the entire surface of the substrate, exposed and developed using a mask having an opening in a required portion, and the resist is left only in the recess, and heat treatment is performed to deform the resist to form the recess in the substrate surface. Since the step is made flat and the plating electrode and the plating wiring are formed on the substrate surface in that state, and the resist filled in the recess is removed thereafter, when the plating electrode and the plating wiring are formed on the substrate surface, The resist can be applied uniformly,
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring remains in the recesses. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. There is an effect that it can be formed. Further, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured.

According to the method for manufacturing a semiconductor device of the present invention (claim 2), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and a resist is filled in the recess,
Further, it is applied so as to cover the entire surface of the substrate, exposed and developed using a mask having an opening in a required portion, and the resist is left only in the recess, and heat treatment is performed to deform the resist to form the recess in the substrate surface. The step is made flat, and in that state, the plating electrode and the plating wiring are formed on the substrate surface, and then the resist filled in the recess is removed, and further, as the resist filling the inside of the recess at the temperature of the subsequent heat treatment. Since the resist that does not undergo glass transition is used, the volume expansion coefficient does not change due to the glass transition of the resist, and the flatness of the substrate can be easily controlled.

According to the method for manufacturing a semiconductor device of the present invention (claim 3), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. The solvent of the same component as the solvent in the above is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the resist is exposed and developed using a mask having an opening in a required portion, The resist is left only in the recesses, and heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state, the plating electrodes and plating wirings are formed on the substrate surface, and then the recesses are filled. Since the resist is removed, it is possible to apply the resist evenly when forming the plating electrode and the plating wiring on the substrate surface, and thus the resist is formed on the substrate surface. The coverage of the active element is improved, the underlying pattern of the active element or the like can be prevented from being exposed, and the resist when forming the plating electrode and the plating wiring can be prevented from remaining in the recess, Further, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. is there. Further, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the resist can be filled and the surface of the substrate can be flattened more reliably.

According to the method for manufacturing a semiconductor device of the present invention (claim 4), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W. Perform for 10 to 30 seconds, apply the same solvent as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, and use a mask with an opening in the required area. By exposing and developing, leaving the resist only in the recesses, and performing heat treatment to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state, form the plating electrodes and plating wirings on the substrate surface. Since the resist filled in the concave portion is removed thereafter, the resist can be uniformly applied when forming the plating electrode and the plating wiring on the substrate surface. Coverage of active elements formed on the surface of the plate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and resist for forming the plating electrodes and plating wiring remains in the recesses. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. The effect is that you can. Further, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the resist can be filled and the surface of the substrate can be flattened more reliably.

According to the method of manufacturing a semiconductor device of the present invention (claim 5), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. Filling the inside of the forming hole, and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening in a required portion, leaving the resist only in the via hole forming hole, The resist is deformed by heat treatment to flatten the steps of the holes for forming via holes on the substrate surface, the lower layer resist for plating is formed on the active element forming portion, and the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the entire surface, an upper layer resist serving as a mask for electrolytic plating for forming a plating electrode and a plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole. Since the resist filled in the via hole is removed and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the resist when forming the plating electrode and the plating wiring on the substrate surface Can be applied evenly,
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist for forming the plated electrodes and the plated wiring can be formed by the via hole formation described above. Since it can be prevented from remaining in the holes for use, and a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, high precision can be achieved at the same time when the plating electrode is formed. There is an effect that the plated wiring can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured.

According to the method of manufacturing a semiconductor device of the present invention (claim 6), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. Filling the inside of the forming hole, and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening in a required portion, leaving the resist only in the via hole forming hole, The resist is deformed by heat treatment to flatten the step of the via hole forming hole on the substrate surface, the lower layer resist for plating is formed on the active element forming portion, and the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the entire surface, an upper layer resist serving as a mask for electrolytic plating for forming a plating electrode and a plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface. To form
Since the resist filled in the via hole was removed and the metal film was formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface was used. It can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and forms the plating electrodes and plating wirings. When resist can be prevented from remaining in the via hole forming hole, further, since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, There is an effect that high-precision plated wiring can be formed simultaneously with the formation of the plated electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the method of manufacturing a semiconductor device of the present invention (claim 7), a via hole forming hole having a predetermined depth is formed in the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. Filling the inside of the forming hole, and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening in a required portion, leaving the resist only in the via hole forming hole, The resist is deformed by heat treatment to flatten the steps of the holes for forming via holes on the substrate surface, the lower layer resist for plating is formed on the active element forming portion, and the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the entire surface, an upper layer resist serving as a mask for electrolytic plating for forming a plating electrode and a plated wiring is formed, and an electrolytic film is selectively formed only in the opening of the upper layer resist. The upper layer resist is removed, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and a via hole is formed in the substrate. Only the portion directly below the forming hole is processed until the via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole, and the substrate Since the metal film is formed on the back surface, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface. , It is possible to prevent the underlying pattern of the active element and the like from being exposed, and the resist used when forming the plated electrode and the plated wiring is the via hole. Since it can be prevented from remaining in the production holes, and a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form a high-potential resist simultaneously with the formation of the plating electrode. There is an effect that it is possible to form an accurate plated wiring. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the method of manufacturing a semiconductor device of the present invention (claim 8), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and the resist is used as the via hole. Filling the inside of the forming hole, and coating so as to cover the entire surface of the substrate, exposing and developing the resist using a mask having an opening in a required portion, leaving the resist only in the via hole forming hole, The resist is deformed by heat treatment to flatten the steps of the holes for forming via holes on the substrate surface, the lower layer resist for plating is formed on the active element forming portion, and the substrate is used as a power supply layer for electrolytic plating. A metal film is formed on the entire surface, an upper layer resist that serves as a mask during electrolytic plating for forming a plating electrode and a plated wiring is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist. Then, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and a via hole is formed in the substrate. Only the portion directly below the hole is processed until the hole for forming a via hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole and the back surface of the substrate are removed. Since the metal film is formed on the substrate, it is possible to uniformly apply the resist when forming the plated electrode and the plated wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface. It is possible to prevent the underlying pattern of active elements and the like from being exposed, and the resist used when forming the plating electrode and the plating wiring forms the above via hole. It is possible to prevent the residual metal from remaining in the holes. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high accuracy. There is an effect that plated wiring can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. There is an effect that can be.

According to the semiconductor device of the present invention (claim 9), a via-hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via-hole forming hole. It is filled inside and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the via hole forming hole is opened from the back surface to the entire back surface of the substrate. Process to form a via hole, remove the resist filled in the via hole,
Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the active elements formed on the surface of the substrate is improved, the underlying pattern of the active elements and the like can be prevented from being exposed, and the resist used when forming the plated electrodes and the plated wiring is the above holes for forming via holes. It is possible to prevent the residue from being left on the plate, and since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to perform high-precision plating simultaneously with the formation of the plating electrode. The effect is that wiring can be formed. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device of the present invention (claim 10), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. It is filled inside and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening in a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. The resist is deformed to flatten the step of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the via hole forming hole is opened from the back surface to the entire back surface of the substrate. To form a via hole, remove the resist filled in the via hole, completely fill the inside of the via hole with a metal film,
Since the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, and thereby the active element formed on the substrate surface. Of the active element and the like can be prevented from being exposed, and the resist when forming the plating electrode and the plating wiring can be prevented from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time when the plated electrode is formed. effective. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the semiconductor device of the present invention (claim 11), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. It is filled inside and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. , Only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole, and the via hole is filled. Since the cyst was removed and a metal film was formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface should be applied uniformly. As a result, the coverage of active elements formed on the surface of the substrate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring is Since it can be prevented from remaining in the holes for forming via holes, and a positive type photoresist with high resolution can be used as a resist for forming the plated electrodes and the plated wiring, the formation of the plated electrodes can be prevented. At the same time, it is possible to form highly accurate plated wiring. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the semiconductor device of the present invention (claim 12), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. It is filled inside and coated so as to cover the entire surface of the substrate, and the resist is exposed and developed using a mask having an opening at a required portion, and the resist is left only in the holes for forming via holes, and heat treatment is performed. Then, the resist is deformed to flatten the level difference of the via hole forming hole on the substrate surface, the plating electrode and the plating wiring are formed on the substrate surface, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. , Only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole, and the via hole is filled. The resist is used when the plating electrode and the plating wiring are formed on the front surface of the substrate because the resist is removed and the inside of the via hole is completely filled with the metal film and the metal film is formed on the back surface of the substrate. Can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface, prevents the underlying pattern of the active elements, etc. from being exposed, and also forms the plating electrodes and plating wiring. It is possible to prevent the resist at the time of remaining from remaining in the via hole forming hole, and further, since a high-resolution positive type photoresist can be used as the resist for forming the plating electrode and the plating wiring. There is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, heat treatment is applied to deform the resist filled in the via-hole forming holes, so that the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. In addition, the entire semiconductor substrate must be thick enough to maintain its mechanical strength (for example, 100 μm).
m) can be provided and the mechanical strength at the time of handling the semiconductor substrate can be improved.
Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the method of manufacturing a semiconductor device of the present invention (claim 13), a recess is formed in the surface of the semiconductor substrate on which the active element is formed, a resist is filled in the recess, and the surface of the substrate is filled. It is applied so as to cover the entire surface, and by removing the resist on the unnecessary portion of the substrate surface by the etch-back method, the steps of the concave portion of the substrate surface are flattened,
In that state, the plating electrode and the plating wiring are formed on the substrate surface, and then the resist filled in the recess is removed. Therefore, the resist for forming the plating electrode and the plating wiring on the substrate surface is uniformly applied. It is possible,
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring remains in the recesses. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. There is an effect that it can be formed. Furthermore, since unnecessary portions of the resist filled in the recesses are removed by etching back, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. There is an effect.

According to the method for manufacturing a semiconductor device of the present invention (claim 14), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. A solvent having the same components as the solvent in the above is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and an unnecessary portion of the resist on the substrate surface is removed by an etch-back method. To flatten the step of the recess on the substrate surface,
In that state, the plating electrode and the plating wiring are formed on the substrate surface, and then the resist filled in the recess is removed. Therefore, the resist for forming the plating electrode and the plating wiring on the substrate surface is uniformly applied. It is possible,
This improves the coverage of the active elements formed on the substrate surface, can prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring remains in the recesses. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. There is an effect that it can be formed. Furthermore, since unnecessary portions of the resist filled in the recesses are removed by etching back, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. There is an effect. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the resist can be filled and the surface of the substrate can be flattened more reliably.

Further, according to the method for manufacturing a semiconductor device of the present invention (claim 15), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W. Perform for 10 to 30 seconds, apply a solvent of the same component as the solvent in the resist component to the semiconductor substrate surface, apply the resist to the semiconductor substrate surface before the applied solvent dries, and etch the substrate surface of the substrate By removing the resist of the unnecessary portion of, the step of the recess on the substrate surface is made flat, and in that state the plating electrode and the plating wiring are formed, and then the resist filled in the recess is removed. It is possible to uniformly apply the resist for forming the plating electrode and the plating wiring on the surface of the substrate, thereby covering the active elements formed on the surface of the substrate. It is possible to prevent the underlying pattern of the active element or the like from being exposed, and it is possible to prevent the resist at the time of forming the plating electrode and the plating wiring from remaining in the recessed portion. Also, since a high-resolution positive type photoresist can be used as a resist for forming the plated wiring, it is possible to form the plated electrode with high precision at the same time when the plated electrode is formed. Furthermore, since unnecessary portions of the resist filled in the recesses are removed by etching back, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recesses, and the temperature control during the heat treatment and the tolerance of the accuracy of the volume of the resist to be filled in the recesses can be increased. There is an effect. Furthermore, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the resist can be filled and the surface of the substrate can be flattened more reliably.

According to the semiconductor device manufacturing method of the present invention (claim 16), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. It fills the inside of the formation hole and is applied so as to cover the entire surface of the substrate, and the resist of the unnecessary portion of the substrate surface is removed by the etch back method to flatten the step of the via hole formation hole on the substrate surface. Forming a lower layer resist for plating on the active element forming portion, forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming a plating electrode and a plating wiring, which serves as a mask during electrolytic plating An upper layer resist is formed, and only the openings of the upper layer resist are electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole, and the above Since the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the surface of the substrate, and thus the coverage of the active elements formed on the surface of the substrate can be improved. It improves and can prevent the underlying pattern such as active elements from being exposed,
Further, it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type resist is used. Since a photoresist can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable.
Further, it is not necessary to consider the glass transition temperature in selecting the resist to be filled in the via hole forming hole, and,
There is an effect that the temperature control during the heat treatment and the tolerance of the volume accuracy of the resist filled in the via hole forming hole can be increased.

According to the semiconductor device manufacturing method of the present invention (claim 17), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. It fills the inside of the formation hole and is applied so as to cover the entire surface of the substrate, and the resist of the unnecessary portion of the substrate surface is removed by the etch back method to flatten the step of the via hole formation hole on the substrate surface. Forming a lower layer resist for plating on the active element forming portion, forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming a plating electrode and a plating wiring, which serves as a mask during electrolytic plating An upper layer resist is formed, and only the openings of the upper layer resist are electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and the inner surface of the via hole is removed. Since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied to the surface of the substrate, and the active element formed on the surface of the substrate is thereby formed. Of the active element and the like can be prevented from being exposed, and the resist when forming the plating electrode and the plating wiring can be prevented from remaining in the via hole forming hole. In addition, it is possible to use high-resolution positive type photoresist as a resist for forming plated electrodes and plated wiring. Because it has an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in selecting the resist to be filled in the via hole forming holes, and the temperature control during heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming holes are allowed. The effect is that the degree can be increased. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device manufacturing method of the present invention (claim 18), a via hole forming hole having a predetermined depth is formed in the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole. It fills the inside of the formation hole and is applied so as to cover the entire surface of the substrate, and the resist of the unnecessary portion of the substrate surface is removed by the etch back method to flatten the step of the via hole formation hole on the substrate surface. Forming a lower layer resist for plating on the active element forming portion, forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming a plating electrode and a plating wiring, which serves as a mask during electrolytic plating An upper layer resist is formed, and only the openings of the upper layer resist are electrolytically plated, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The lower layer resist is removed, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface. A hole is formed, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate, so that a plating electrode and a plating wiring are formed on the substrate surface. It is possible to apply the resist evenly, the coverage of the active element formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active element or the like is exposed, and the plating electrode and It is possible to prevent the resist at the time of forming the plated wiring from remaining in the via hole forming hole. It is possible to use a positive type photoresist of high resolution as a resist for forming a line, there is an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in selecting the resist to be filled in the via hole forming holes, and the temperature control during heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming holes are allowed. The effect is that the degree can be increased. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the semiconductor device manufacturing method of the present invention (claim 19), a via hole forming hole having a predetermined depth is formed on the surface of the GaAs substrate on which the active element is formed, and the resist is used as the via hole. It fills the inside of the formation hole and is applied so as to cover the entire surface of the substrate, and the resist of the unnecessary portion of the substrate surface is removed by the etch back method to flatten the step of the via hole formation hole on the substrate surface. Forming a lower layer resist for plating on the active element forming portion, forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming a plating electrode and a plating wiring, which serves as a mask during electrolytic plating An upper layer resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed. The layer resist is removed, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface. A hole is formed, the resist filled in the via hole is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate, so that a plating electrode and a plating wiring are formed on the substrate surface. It is possible to apply the resist evenly, the coverage of the active element formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active element or the like is exposed, and the plating electrode and It is possible to prevent the resist at the time of forming the plated wiring from remaining in the via hole forming hole, and further, to further improve the plating electrode and the plated wiring. Since as a resist for forming can be used positive type photoresist of high resolution, there is an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in selecting the resist to be filled in the via hole forming holes, and the temperature control during heat treatment and the tolerance of the volume accuracy of the resist filling the via hole forming holes are allowed. The effect is that the degree can be increased. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. There is an effect that can be.

According to the semiconductor device of the present invention (claim 20), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. The inside of the substrate is coated so as to cover the entire surface of the substrate, and the resist of unnecessary portions on the surface of the substrate is removed by an etch-back method to flatten the step of the via-hole forming hole on the substrate surface. A plating electrode and a plating wiring are formed on the front surface, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the registration for forming the plating electrode and the plating wiring on the substrate surface is performed. Can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface and prevents the underlying pattern of the active elements from being exposed. It is possible to prevent the resist at the time of forming from remaining in the via hole forming hole, and further, since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring. There is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The effect is that the tolerance can be increased. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device of the present invention (claim 21), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. The inside of the substrate is coated so as to cover the entire surface of the substrate, and the resist on unnecessary portions of the substrate surface is removed by an etch-back method to flatten the steps of the via-hole forming holes on the substrate surface. A plating electrode and a plating wiring are formed on the surface, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Since the inside of the via hole is completely filled with the metal film and the metal film is formed on the back surface of the substrate, the plating electrode and the plating wiring are formed on the substrate surface. It is possible to apply the resist evenly, the coverage of the active element formed on the substrate surface is improved by this, it is possible to prevent the underlying pattern of the active element or the like is exposed, and the plating electrode and It is possible to prevent the resist at the time of forming the plated wiring from remaining in the via hole forming hole, and use a high-resolution positive type photoresist as the resist for forming the plated electrode and the plated wiring. Therefore, it is possible to form a highly accurate plated wiring at the same time when the plated electrode is formed. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The effect is that the tolerance can be increased. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the semiconductor device of the present invention (claim 22), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. The inside of the substrate is coated so as to cover the entire surface of the substrate, and the resist of unnecessary portions on the surface of the substrate is removed by an etch-back method to flatten the step of the via-hole forming hole on the substrate surface. A plating electrode and a plating wiring are formed on the surface, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and the via hole forming hole is opened from the back surface only under the via hole forming hole of the substrate. To form a via hole, remove the resist filled in the via hole, and form a metal film on the inner surface of the via hole and the back surface of the substrate. Since the resist is used for forming the plating electrode and the plating wiring on the substrate surface evenly, the coverage of the active element formed on the substrate surface is improved and the active element is formed. It is possible to prevent the underlying pattern such as
Further, it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type resist is used. Since a photoresist can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable.
Further, it is not necessary to consider the glass transition temperature in selecting the resist to be filled in the via hole forming hole, and,
There is an effect that the temperature control during the heat treatment and the tolerance of the volume accuracy of the resist filled in the via hole forming hole can be increased. Furthermore, the entire semiconductor substrate is thick enough to maintain its mechanical strength (for example, 100 μm).
Therefore, there is an effect that the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the semiconductor device of the present invention (claim 23), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the resist is used as the via hole forming hole. The inside of the substrate is coated so as to cover the entire surface of the substrate, and the resist of unnecessary portions on the surface of the substrate is removed by an etch-back method to flatten the step of the via-hole forming hole on the substrate surface. A plating electrode and a plating wiring are formed on the surface, the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and the via hole forming hole is opened from the back surface only under the via hole forming hole of the substrate. To form a via hole, remove the resist filled in the via hole, completely fill the inside of the via hole with a metal film, and Since the metal film is formed on the back surface, it is possible to uniformly apply the resist when forming the plating electrodes and the plating wirings on the substrate surface, and thus the coverage of the active elements formed on the substrate surface can be improved. It is possible to prevent the underlying pattern such as the active element from being exposed, and to prevent the resist when forming the plating electrode and the plating wiring from remaining in the via hole forming hole. Since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form the plating electrode with high precision simultaneously with the formation of the plating electrode. . Further, since the unnecessary portion of the resist filled in the via hole forming hole is removed by the etch back, the steps on the substrate surface can be made more flat, and the above-mentioned effect can be made more reliable. Further, it is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the via hole forming hole, and the temperature control during the heat treatment, and the accuracy of the volume of the resist filling the via hole forming hole The effect is that the tolerance can be increased. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

Further, according to the method of manufacturing a semiconductor device of the present invention (claim 24), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. A solvent having the same composition as the solvent in the above is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and the step is flattened on the surface of the substrate by leaving the resist only in the recesses. In that state, the plating electrode and the plating wiring are formed on the substrate surface, and then the resist filled in the recess is removed. Can improve the coverage of the active elements formed on the surface of the substrate and prevent the underlying pattern of the active elements from being exposed. In addition, it is possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the recesses. Since the resist can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled, and there is an effect that the surface of the substrate can be flattened more reliably.

According to the method for manufacturing a semiconductor device of the present invention (claim 25), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W. Do for 10 to 30 seconds, apply a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, apply the resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the recesses. Since the steps on the surface of the substrate are flattened, the plating electrodes and the wiring are formed on the surface of the substrate in that state, and then the resist filling the recesses is removed. It is possible to apply the resist evenly when forming the film, which improves the coverage of the active elements formed on the substrate surface and exposes the underlying pattern of the active elements and the like. It is possible to prevent that,
Further, it is possible to prevent the resist at the time of forming the plated electrode and the plated wiring from remaining in the recesses, and further, a high resolution positive type photoresist is used as the resist for forming the plated electrode and the plated wiring. Therefore, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled, and there is an effect that the surface of the substrate can be flattened more reliably.

According to the method of manufacturing a semiconductor device of the present invention (claim 26), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. A solvent having the same components as the solvent in the above is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and the resist is exposed using a mask having an opening in a required portion, After development, the resist is left only in the recesses, and heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state, the plating electrodes and plating wirings are formed, and then the recesses are formed in the recesses. Since the filled resist is removed, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. Coverage of active elements formed on the surface of the plate is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and resist for forming the plating electrodes and plating wiring remains in the recesses. In addition, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. The effect is that you can. Further, since the heat treatment is applied to deform the resist filled in the recesses, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled, and there is an effect that the surface of the substrate can be flattened more reliably.

According to the method of manufacturing a semiconductor device of the present invention (claim 27), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. A solvent having the same components as the solvent in the above is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and the resist is exposed using a mask having an opening in a required portion, After development, the resist is left only in the recesses, and heat treatment is performed to deform the resist to flatten the steps of the recesses on the substrate surface, and in that state, the plating electrodes and the plating wirings are formed on the substrate surface, and then the recesses are formed. Be sure to remove the filled resist, and use a resist that does not undergo glass transition at the temperature of the subsequent heat treatment as the resist to be filled inside the recess. Since the, not generated change of volume expansion rate due to the glass transition of the resist, there is an effect that the control of the flatness of the substrate can be facilitated.

According to the method of manufacturing a semiconductor device of the present invention (claim 28), a recess is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is subjected to oxygen plasma treatment to form a resist component. A solvent having the same components as the solvent in the above is applied to the surface of the semiconductor substrate, a resist is applied to the surface of the semiconductor substrate before the applied solvent is dried, and an unnecessary portion of the resist on the substrate surface is removed by an etch-back method. As a result, the steps of the concave portion on the substrate surface are made flat, and in that state, the plating electrode and the plating wiring are formed, and then the resist filling the concave portion is removed. Also, the resist for forming the plated wiring can be uniformly applied, which improves the coverage of the active elements formed on the substrate surface. It is possible to prevent the underlying pattern of the active element or the like from being exposed, and to prevent the resist when forming the plated electrode and the plated wiring from remaining in the recesses. Since a high-resolution positive type photoresist can be used as a resist for forming, there is an effect that a highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Furthermore, since unnecessary portions of the resist filled in the recesses are removed by etching back, the steps on the substrate surface can be made more flat, and the above-described effect can be further ensured. Also,
It is not necessary to consider the glass transition temperature in the selection of the resist to be filled in the recess, and it is possible to increase the tolerance of temperature control during heat treatment and the accuracy of the volume of the resist to be filled in the recess. There is. Further, the affinity between the semiconductor substrate and the resist filling the recess is improved, and the high-viscosity resist can easily flow into the recess deep in the surface of the semiconductor substrate and having a small opening diameter. Can be filled, and there is an effect that the surface of the substrate can be flattened more reliably.

According to the method of manufacturing a semiconductor device of the present invention (claim 29), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is formed. Oxygen plasma treatment is performed, a solvent having the same component as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and only the holes for forming via holes are formed. The surface of the substrate is made flat by leaving a resist on the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating. And forming an upper layer resist that serves as a mask at the time of electrolytic plating for forming plated wiring, and selectively electrolytically plating only the opening of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the via hole is formed. Since the resist filled in was removed and the metal film was formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface is uniformly applied. As a result, the coverage of active elements formed on the substrate surface is improved, it is possible to prevent the underlying pattern of the active elements and the like from being exposed, and the resist used when forming the plating electrodes and plating wiring is improved. It can be prevented from remaining in the via hole forming hole,
Further, since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form the plating electrode with high precision at the same time when the plating electrode is formed. is there. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened.

According to the method of manufacturing a semiconductor device of the present invention (claim 30), a via hole forming hole having a predetermined depth is formed in the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is formed. Oxygen plasma treatment is performed, a solvent of the same component as the solvent in the resist component is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and only the holes for forming via holes are formed. A level difference on the surface of the substrate is flattened by leaving a resist on the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and a plating electrode is formed. And forming an upper layer resist that serves as a mask at the time of electrolytic plating for forming plated wiring, and selectively electrolytically plating only the opening of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, Since the resist filled in the via hole is removed and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, the resist for forming the plating electrode and the plating wiring on the substrate surface is uniform. Can improve the coverage of the active elements formed on the substrate surface and prevent the underlying pattern of the active elements from being exposed. Also, when forming plated electrodes and plated wiring, Resist can be prevented from remaining in the via hole forming hole, and further, a resist for forming a plating electrode and a plating wiring. Since the positive type photoresist of high resolution can be used with, there is an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device manufacturing method of the present invention (claim 31), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is formed. Oxygen plasma treatment is performed, a solvent of the same component as the solvent in the resist component is applied to the surface of the semiconductor substrate, the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, and only the holes for forming via holes are formed. A level difference on the surface of the substrate is flattened by leaving a resist on the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and a plating electrode is formed. And forming an upper layer resist that serves as a mask at the time of electrolytic plating for forming plated wiring, and selectively electrolytically plating only the opening of the upper layer resist,
The upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, directly below the via hole forming hole of the substrate. Only the part is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed.
Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the formed active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the resist for forming the plating electrode and the plating wiring remains in the via hole forming hole. You can prevent
Since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high accuracy simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the method for manufacturing a semiconductor device of the present invention (claim 32), a via hole forming hole having a predetermined depth is formed in the surface of the GaAs substrate on which the active element is formed, and the surface of the semiconductor substrate is formed. Oxygen plasma treatment is performed, a solvent having the same component as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent dries, and only the holes for forming via holes are formed. The surface of the substrate is made flat by leaving a resist on the substrate, a lower layer resist for plating is formed on the active element forming portion, and a metal film is formed on the entire surface of the substrate as a power supply layer for electrolytic plating. And forming an upper layer resist that serves as a mask during electrolytic plating for forming plated wiring, and selectively performing electrolytic plating only on the openings of the upper layer resist to remove the upper layer resist. Then, unnecessary portions of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is via-formed. Form a via hole by processing until the hole forming hole opens from the back surface, and remove the resist filled in the via hole,
Since the metal film is formed on the inner surface of the via hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the formed active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the resist for forming the plating electrode and the plating wiring remains in the via hole forming hole. You can prevent
Since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high accuracy simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Further, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate, which is a problem particularly in the fragile GaAs substrate, can be improved. There is an effect that can be.

According to the semiconductor device of the present invention (claim 33), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is treated with oxygen plasma. The same component solvent as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent is dried, and the resist is applied only to the via-hole forming holes. Flatten the steps on the surface of the substrate leaving, form plating electrodes and plating wiring on the surface of the substrate, and process the entire rear surface of the substrate until a via hole forming hole opens from the rear surface to form a via hole, Since the resist filled in the via hole is removed and a metal film is formed on the inner surface of the via hole and the back surface of the substrate, the metal film is formed on the substrate surface. It is possible to uniformly apply the resist when forming the electrodes and the plated wiring, which improves the coverage of the active elements formed on the substrate surface and prevents the underlying pattern of the active elements and the like from being exposed. Further, it is possible to prevent the resist used when forming the plated electrode and the plated wiring from remaining in the via hole forming hole, and further, as a resist for forming the plated electrode and the plated wiring, a high-resolution positive type Since this photoresist can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device of the present invention (claim 34), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is treated with oxygen plasma. The same component solvent as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent is dried, and the resist is applied only to the via-hole forming holes. Flatten the steps on the surface of the substrate leaving, form plating electrodes and plating wiring on the surface of the substrate, and process the entire rear surface of the substrate until a via hole forming hole opens from the rear surface to form a via hole, The resist filled in the via hole is removed, the inside of the via hole is completely filled with a metal film, and the metal film is formed on the back surface of the substrate. It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element and the like. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole. Furthermore, as a resist for forming the plated electrode and the plated wiring, Since a positive photoresist of resolution can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the semiconductor device of the present invention (claim 35), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is treated with oxygen plasma. The same component solvent as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent is dried, and the resist is applied only to the via-hole forming holes. Flatten the steps on the surface of the substrate, form plated electrodes and plated wiring on the surface of the substrate, and machine the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength. Only the portion is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. Since the metal film is formed on the inner surface of the substrate and the back surface of the substrate, the resist can be uniformly applied when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the formed active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the resist for forming the plating electrode and the plating wiring remains in the via hole forming hole. Can prevent that
Further, since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form the plating electrode with high precision at the same time when the plating electrode is formed. is there. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the semiconductor device of the present invention (claim 36), a via hole forming hole having a predetermined depth is formed on the surface of the semiconductor substrate on which the active element is formed, and the surface of the semiconductor substrate is treated with oxygen plasma. The same component solvent as the solvent in the resist component is applied to the semiconductor substrate surface, the resist is applied to the semiconductor substrate surface before the applied solvent is dried, and the resist is applied only to the via-hole forming holes. Flatten the steps on the surface of the substrate, form plated electrodes and plated wiring on the surface of the substrate, and machine the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength, directly below the holes for forming via holes in the substrate. Only the portion is processed until the via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. The internal Le was completely filled with metal film. Thus by forming a metal film on the rear surface of the substrate,
It is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element and the like. In addition, it is possible to prevent the resist used for forming the plated electrode and the plated wiring from remaining in the via-hole forming hole. Furthermore, as a resist for forming the plated electrode and the plated wiring, Since a positive photoresist of resolution can be used, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, the affinity between the semiconductor substrate and the resist filled in the via-hole forming hole is improved, and the high-viscosity resist can easily flow into the via-hole forming hole deep in the surface of the semiconductor substrate and having a small opening diameter. There is an effect that the via hole forming hole of the substrate can be completely filled with the resist and the surface of the substrate can be more surely flattened. In addition, the entire semiconductor substrate must be thick enough to maintain its mechanical strength (for example, 100 μm).
m) can be provided and the mechanical strength at the time of handling the semiconductor substrate can be improved.
Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the method of manufacturing a semiconductor device of the present invention (claim 37), an insulating film is formed on the surface of a semiconductor substrate, a resist is applied on the entire surface of the insulating film, and recesses are formed in the resist. A mask for forming a resist pattern having an opening at a position is used for exposure and development to create an etching mask, the insulating film is etched using the etching mask, and a recess is formed on the substrate surface using the same etching mask. The resist used for the etching mask is removed by etching, and the insulating film is used as a mask to grow crystals to fill the recesses and flatten the substrate surface. The film is removed, active elements are formed on the surface of the substrate, plating electrodes and wiring are formed on the surface of the substrate, and crystal growth is performed. Since the crystal filled in the recess is removed, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, and thereby the active element formed on the substrate surface The coverage is improved, it is possible to prevent the underlying pattern of the active element or the like from being exposed, and it is possible to prevent the resist when forming the plating electrode and the plating wiring from remaining in the recesses. Since a high-resolution positive type photoresist can be used as a resist for forming the electrodes and the plated wirings, it is possible to form the plated electrodes with high precision at the same time when the plated electrodes are formed. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved.

According to the method for manufacturing a semiconductor device of the present invention (claim 38), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a formation hole forming position, the insulating film is etched using the etching mask, and the substrate is formed using the same etching mask. A hole for forming a via hole having a predetermined depth is formed by etching on the surface, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Forming, selectively electrolytically plating only the openings of the upper layer resist, removing the upper layer resist, removing unnecessary portions of the power feeding layer, removing the lower layer resist, and forming the substrate for via hole formation. The via hole is formed by processing until the hole opens from the back surface, and the crystal filled in the via hole is removed by crystal growth. Further, since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied to the surface of the substrate, and the active element formed on the surface of the substrate can be coated with the resist. The coverage is improved, and it is possible to prevent the underlying pattern of the active element or the like from being exposed. Also, it is possible to prevent the resist when forming the plating electrode and the plating wiring from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision simultaneously with the formation of the plated electrode. There is. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved.

According to the method for manufacturing a semiconductor device of the present invention (claim 39), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a formation hole forming position, the insulating film is etched using the etching mask, and the substrate is formed using the same etching mask. A hole for forming a via hole having a predetermined depth is formed by etching on the surface, the resist used for the etching mask is removed, and the insulating film is used as a mask.
By growing a crystal, the via-hole forming hole is filled to flatten the substrate surface, the insulating film used as a mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer resist for plating is formed on the element forming portion, a metal film is formed on the entire surface of the substrate as a power feeding layer for performing electrolytic plating, and an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring is formed. Then, electrolytic plating is selectively performed only on the openings of the upper layer resist, the upper layer resist is removed, unnecessary portions of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is via-formed. Form a via hole by processing until the hole forming hole opens from the back side,
Since the crystal filled in the via hole is removed by crystal growth and the metal film is formed on the inner surface of the via hole and the back surface of the substrate, when the plating electrode and the plating wiring are formed on the substrate surface, The resist can be applied uniformly, which improves the coverage of the active elements formed on the substrate surface, prevents the underlying pattern of the active elements and the like from being exposed, and prevents the plating electrodes and plating wiring from being exposed. It is possible to prevent the resist at the time of forming from remaining in the via hole forming hole, and further, a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring. Therefore, there is an effect that a highly accurate plated wiring can be formed simultaneously with the formation of the plated electrode. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the method for manufacturing a semiconductor device of the present invention (claim 40), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole is formed in the resist. An etching mask is formed by exposing and developing using a mask that forms a resist pattern having an opening at a formation hole forming position, the insulating film is etched using the etching mask, and the substrate is formed using the same etching mask. The via hole forming hole having a predetermined depth is formed by etching on the surface, the resist used for the etching mask is removed, and the via hole forming hole is filled by growing a crystal using the insulating film as a mask. The substrate surface is flattened, the insulating film used as the mask during selective crystal growth is removed, and an active element is formed on the substrate surface. A lower layer for plating is formed on the active element forming portion, a metal film is formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and an upper layer serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring. A resist is formed, and electrolytic plating is selectively performed only on the openings of the upper layer resist to remove the upper layer resist,
Unnecessary parts of the power feeding layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Form a via hole by processing until the hole opens from the back surface, remove the crystal filled in the via hole by crystal growth, and form a metal film on the inner surface of the via hole and the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active elements formed on the substrate surface and exposes the underlying pattern of the active elements and the like. Of the via hole and the resist used when forming the plated electrode and the plated wiring are prevented from remaining in the via hole forming hole. Can be further it is possible to use a positive type photoresist of high resolution as a resist for forming a plating electrode and plating wires,
There is an effect that high-precision plated wiring can be formed simultaneously with the formation of the plated electrode. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved.
Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the method of manufacturing a semiconductor device of the present invention (claim 41), an insulating film is formed on the surface of the GaAs substrate,
The entire surface of the insulating film is coated with a resist, and the resist is exposed and developed using a mask for forming a resist pattern having an opening at a hole forming position for the via hole, and an etching mask is formed. By etching the insulating film, using the same etching mask to form a via hole forming hole of a predetermined depth on the substrate surface, remove the resist used for the etching mask, mask the insulating film By filling the via hole forming hole by making a crystal grow to flatten the substrate surface, remove the insulating film used as a mask during selective crystal growth, form an active element on the substrate surface, A lower layer resist for plating is formed on the active element formation part, and a gold layer is formed on the entire surface of the substrate as a power supply layer for electrolytic plating. Forming a film, forming an upper layer resist that serves as a mask during electrolytic plating for forming a plating electrode and plated wiring, and selectively electrolytically plating only the openings of the upper layer resist to remove the upper layer resist, and Unnecessary parts of the power supply layer are removed, the lower layer resist is removed, and the entire back surface of the substrate is processed to a thickness that can maintain sufficient mechanical strength. Is processed from the back surface to an opening to form a via hole, the crystal filled in the via hole is removed by crystal growth, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. Therefore, the resist for forming the plated electrode and the plated wiring on the substrate surface can be uniformly applied, which allows the active element formed on the substrate surface to be covered with the resist. It is possible to improve the ledge, prevent the underlying pattern of the active element and the like from being exposed, and prevent the resist when forming the plating electrode and the plating wiring from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plating electrode and the plating wiring, it is possible to form the plating electrode with high precision at the same time when the plating electrode is formed. There is. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) sufficient to maintain its mechanical strength, which makes the material fragile.
There is an effect that the mechanical strength at the time of handling a semiconductor substrate, which is a particular problem in a GaAs substrate, can be improved.

According to the method of manufacturing a semiconductor device of the present invention (claim 42), an insulating film is formed on the surface of the GaAs substrate,
The entire surface of the insulating film is coated with a resist, and the resist is exposed and developed using a mask for forming a resist pattern having an opening at a hole forming position for the via hole to form an etching mask. By etching the insulating film, using the same etching mask to form a via hole forming hole of a predetermined depth on the substrate surface, remove the resist used for the etching mask, mask the insulating film InGaP, which has selectivity for wet etching of a GaAs substrate, is selectively crystal-grown to fill the via-hole forming hole to flatten the substrate surface, and the insulating film used as a mask during selective crystal growth is removed. After removing, an active element is formed on the surface of the substrate, and a lower resist layer for plating is formed on the active element forming portion. Forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating, and forming an upper layer resist serving as a mask during electrolytic plating for forming a plating electrode and a plating wiring, only the opening of the upper layer resist Electrolytic plating is selectively performed on the upper layer resist, the unnecessary portion of the power supply layer is removed, the lower layer resist is removed, and the substrate is processed until the via hole forming hole opens from the back surface. Since a via hole is formed and InGaP filled in the via hole by crystal growth is removed with hydrochloric acid, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate, a plating electrode is formed on the substrate surface. Also, the resist for forming the plated wiring can be applied uniformly, which improves the coverage of the active element formed on the substrate surface, and thus the active element, etc. It is possible to prevent the underlying pattern from being exposed, and it is possible to prevent the resist at the time of forming the plated electrode and the plated wiring from remaining in the via hole forming hole. Since a high-resolution positive type photoresist can be used as a resist for forming, there is an effect that a highly accurate plated wiring can be formed at the same time when the plated electrode is formed. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, since InGaP has wet etching selectivity with respect to the GaAs substrate, it has an effect that it can be easily removed from the via hole with hydrochloric acid.

According to the semiconductor device of the present invention (claim 43), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the created position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used as the etching mask is removed, and the substrate surface is flattened by filling the via hole by growing a crystal using the insulating film as a mask, The insulating film used as a mask during selective crystal growth is removed, active elements are formed on the substrate surface, and plating electrodes are formed on the substrate surface. And plating wiring is formed, and the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the crystal filled in the via hole is removed by crystal growth. Since the metal film is formed on the inner surface of the hole and the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. The coverage of the formed active element is improved, the underlying pattern of the active element and the like can be prevented from being exposed, and the resist for forming the plating electrode and the plating wiring remains in the via hole forming hole. And a high-resolution positive-type photoresist as a resist for forming plated electrodes and plated wiring. It is possible to use, there is an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. further,
Since there is no problem of flatness control due to alteration of the material of the filling resist and denaturation of the filling resist due to the heating step, there is an effect that the reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified.

According to the semiconductor device of the present invention (claim 44), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the created position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used for the etching mask is removed, and the substrate surface is flattened by filling the via hole by growing a crystal using the insulating film as a mask, The insulating film used as a mask during selective crystal growth is removed, active elements are formed on the substrate surface, and plating electrodes are formed on the substrate surface. And forming a plated wiring, processing the entire back surface of the substrate until the via hole forming hole is opened from the back surface to form a via hole, and removing the crystal filled in the via hole by crystal growth. Since the inside of the hole is completely filled with the metal film and the metal film is formed on the back surface of the substrate, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface. As a result, the coverage of the active element formed on the substrate surface is improved, the underlying pattern of the active element or the like can be prevented from being exposed, and the resist used when forming the plated electrode and the plated wiring is the via hole. A positive type resist that can be prevented from remaining in the formation holes and has high resolution as a resist for forming plated electrodes and plated wiring. It is possible to use a photoresist, there is an effect that it is possible to form a high-precision plating wiring simultaneously with the formation of plated electrodes. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, since the entire back surface of the substrate is processed when the via hole is formed from the via hole forming hole, there is an effect that the processing of the back surface of the substrate can be simplified. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the semiconductor device of the present invention (claim 45), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the created position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used as the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole and flatten the substrate surface. The insulating film used as a mask during the selective crystal growth is removed, active elements are formed on the substrate surface, and a mask is formed on the substrate surface. Form electrodes and plated wiring, and process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and process only the area directly below the via hole forming hole of the board until the via hole forming hole opens from the back surface. To form a via hole, remove the crystal filled in the via hole by crystal growth, the inner surface of the via hole,
Further, since the metal film is formed on the back surface of the substrate, the resist for forming the plating electrode and the plating wiring can be uniformly applied on the surface of the substrate. The coverage of the device is improved, the underlying pattern of the active device, etc. can be prevented from being exposed, and the resist at the time of forming the plating electrode and the plating wiring is prevented from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. There is an effect. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved.

According to the semiconductor device of the present invention (claim 46), an insulating film is formed on the surface of the semiconductor substrate, a resist is applied on the entire surface of the insulating film, and a via hole forming hole is formed in the resist. An etching mask is created by exposing and developing using a mask that forms a resist pattern having an opening at the created position, the insulating film is etched using the etching mask, and the same etching mask is used to etch the substrate surface. A via hole forming hole having a predetermined depth is formed by etching, the resist used as the etching mask is removed, and a crystal is grown using the insulating film as a mask to fill the via hole and flatten the substrate surface. The insulating film used as a mask during the selective crystal growth is removed, active elements are formed on the substrate surface, and a mask is formed on the substrate surface. Form the electrodes and plated wiring, and process the entire back surface of the substrate to a thickness that can maintain sufficient mechanical strength, and process only the portion directly below the via hole formation hole of the substrate until the via hole formation hole opens from the back surface. To form a via hole, remove the crystal filled in the via hole by crystal growth, completely fill the inside of the via hole with a metal film, and form a metal film on the back surface of the substrate. Therefore, it is possible to uniformly apply the resist when forming the plating electrode and the plating wiring on the substrate surface, which improves the coverage of the active element formed on the substrate surface and exposes the underlying pattern of the active element or the like. It is also possible to prevent the resist when forming the plated electrode and the plated wiring from remaining in the via hole forming hole. Furthermore, since a high-resolution positive type photoresist can be used as a resist for forming the plated electrode and the plated wiring, it is possible to form the plated electrode with high precision at the same time as the formation of the plated electrode. effective. Further, there is no problem of flatness control due to alteration of the material of the filled resist and no problem of denaturation of the filled resist due to the heating step, and there is an effect that the reliability of the manufacturing process can be improved. Furthermore, the entire semiconductor substrate can have a thickness (for example, 100 μm) that can sufficiently maintain the mechanical strength, and the mechanical strength at the time of handling the semiconductor substrate can be improved. Further, as compared with the case where the inside of the via hole is not completely filled with the metal film, there is an effect that heat generated from the active element portion on the front surface of the semiconductor substrate can be more efficiently released to the back surface side of the substrate.

According to the resist coating method of the present invention (claim 47), the surface of the semiconductor substrate is subjected to oxygen plasma treatment, and a solvent having the same component as the solvent in the resist component is coated on the surface of the semiconductor substrate. Since the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, the affinity of the semiconductor substrate and the resist is improved, so that a high-viscosity resist can be formed in a deep recess of the semiconductor substrate surface with a small opening diameter. There is an effect that it can be easily flowed in, and thus the resist can be completely filled in the concave portion of the semiconductor substrate.

According to the resist coating method of the present invention (claim 48), the surface of the semiconductor substrate is subjected to oxygen plasma treatment at 200 W to 300 W for 10 to 30 seconds, and the same solvent as the solvent in the resist component is used. It is applied to the surface of the semiconductor substrate, and the resist is applied to the surface of the semiconductor substrate before the applied solvent dries, so that the affinity between the semiconductor substrate and the resist is improved so that the semiconductor substrate surface has a deep opening diameter. A resist having a high viscosity can easily flow into the small concave portion, and thus the concave portion of the semiconductor substrate can be completely filled with the resist.

[Brief description of drawings]

FIG. 1 is a device sectional view showing a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a manufacturing process diagram showing a first portion of the method for manufacturing a semiconductor device according to the first embodiment of the present invention (FIGS. 2 (a) to 2).
(e)).

FIG. 3 is a manufacturing process diagram showing a second part of the method for manufacturing a semiconductor device according to the first embodiment of the present invention (FIGS. 3A to 3).
(e)).

FIG. 4 is a manufacturing process diagram (FIGS. 4A to 4) showing a third part of the method for manufacturing a semiconductor device according to the first embodiment of the invention.
(e)).

FIG. 5 is a manufacturing process diagram showing a fourth portion of the method of manufacturing a semiconductor device according to the first embodiment of the present invention (FIGS. 5 (a) to 5).
(c)).

FIG. 6 is a manufacturing process diagram showing the first portion of the details of the method for manufacturing a plated wiring according to the first embodiment of the present invention (FIG. 6 (a)).
~ 6 (e)).

FIG. 7 is a manufacturing process diagram showing a second portion of the details of the method for manufacturing a plated wiring according to the first embodiment of the present invention (FIG. 7 (a)).
, 7 (b)).

FIG. 8 is a manufacturing step diagram (FIGS. 8A to 8) showing a first portion of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.
(e)).

FIG. 9 is a manufacturing process diagram showing a second part of the method for manufacturing a semiconductor device according to the second embodiment of the present invention (FIGS.
(e)).

FIG. 10 is a manufacturing step diagram (FIG. 10 (a) -FIG.
10 (e)).

FIG. 11 is a manufacturing process drawing (FIG. 11 (a), showing a fourth portion of the method for manufacturing a semiconductor device according to the second embodiment of the present invention;
11 (b)).

FIG. 12 is a manufacturing process diagram (FIG. 12 (a) -FIG.
12 (e)).

FIG. 13 is a manufacturing process diagram showing a second part of the method for manufacturing a semiconductor device according to the third embodiment of the present invention (FIG.
13 (e)).

FIG. 14 is a manufacturing process diagram showing a third portion of the method for manufacturing a semiconductor device according to the third embodiment of the present invention (FIG. 14 (a) -FIG.
14 (c)).

FIG. 15 is a manufacturing process diagram (FIGS. 15A to 15C) showing a method of manufacturing a semiconductor device according to a fourth embodiment of the invention.

FIG. 16 is a device sectional view showing a semiconductor device according to a fifth embodiment of the present invention (FIGS. 16 (a) and 16 (b)).

FIG. 17 is a device sectional view of a semiconductor device having a via hole according to a first conventional example.

FIG. 18 is a manufacturing process diagram showing a first portion of the method for manufacturing a semiconductor device according to the first conventional example (FIGS. 18A to 18E).
).

FIG. 19 is a manufacturing process diagram showing a second part of the method for manufacturing a semiconductor device according to the first conventional example (FIGS. 19 (a) to 19 (e)).
).

FIG. 20 is a manufacturing process diagram showing a third portion of the method for manufacturing a semiconductor device according to the first conventional example (FIGS. 20 (a) and 20 (b)).
).

FIG. 21 is a manufacturing process diagram showing the first part of the details of the method for manufacturing plated wiring according to the first conventional example (FIGS.
1 (e)).

FIG. 22 is a manufacturing process diagram showing a second portion of the details of the method for manufacturing plated wiring according to the first conventional example (FIGS. 22 (a) and 2).
2 (b)).

FIG. 23 is a device sectional view of a semiconductor device having a via hole according to a second conventional example.

FIG. 24 is a manufacturing process diagram showing a first portion of a method for manufacturing a semiconductor device according to a second conventional example (FIGS. 24 (a) to 24 (e)).
).

FIG. 25 is a manufacturing process diagram showing a second portion of the method for manufacturing a semiconductor device according to the second conventional example (FIGS. 25 (a) to 25 (e)).
).

FIG. 26 is a manufacturing process diagram showing a third portion of the method for manufacturing a semiconductor device according to the second conventional example (FIGS. 26 (a) to 26 (d)).
).

FIG. 27 is a cross-sectional view showing insufficient resist coverage that occurs in a conventional manufacturing method.

FIG. 28 is a cross-sectional view showing a cavity generated in a hole for forming a via hole generated by a conventional manufacturing method.

[Explanation of symbols]

101 GaAs substrate, 102 source electrode, 103 drain electrode, 104 gate electrode, 105 dry etch type via hole, 106 power supply layer for plating, 107 plated electrode in via hole portion, 108 heat dissipation electrode (PH
S), 109 via hole forming hole forming resist, 1
10 via hole forming holes, 111 filling resist,
112 filled resist, 113 filled resist whose shape is changed by heat treatment, 114 lower layer resist, 115 upper layer resist, 116 insulating film, 117
Insulation film and resist for etching holes for forming via holes, 118 InGaP selectively grown, 119 tab holes,
120 plated wiring, 121 solvent, 501 GaAs substrate, 502 source electrode, 503 drain electrode, 50
4 gate electrode, 505 dry etch type via hole, 506 power supply layer for plating of via hole portion, 507
Plating electrode for via hole, 508 heat dissipation electrode (P
HS), 509 via hole forming hole forming resist, 510 via hole forming hole, 511 via hole portion lower layer resist for plating, 512 via hole portion plating upper layer resist, 513 plated wiring, 514
Lower layer resist for plated wiring, 515 Power supply layer for plating of plated wiring, 516 Upper layer resist for plated wiring, 5
17 Filling resist, 518 Insufficient coverage, 519 Exposed underlying pattern, 520 Cavity.

Claims (48)

[Claims] 1. A step of forming a recess on the surface of a semiconductor substrate on which an active element is formed, a step of filling the inside of the recess with a resist and applying the resist so as to cover the entire surface of the substrate, and an opening at a required portion. A step of exposing and developing the resist with a mask having the resist to leave the resist only in the concave portion; a step of performing a heat treatment to deform the resist to flatten the step of the concave portion on the substrate surface; A method of manufacturing a semiconductor device, comprising: a step of forming a plating electrode and a plating wiring; and a step of removing the resist filled in the recess. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a resist that does not undergo glass transition at a temperature of a subsequent heat treatment is used as the resist left only in the recess. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of applying a resist so as to fill the inside of the recess and cover the entire surface of the substrate is an oxygen plasma treatment. A step of performing, a step of applying a solvent having the same component as the solvent in the resist component to the semiconductor substrate surface, and a step of applying a resist to the semiconductor substrate surface before the applied solvent dries. A method for manufacturing a characteristic semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the oxygen plasma treatment performed on the surface of the semiconductor substrate is 200 W to 300 W.
A method for manufacturing a semiconductor device, which is performed for 10 to 30 seconds. 5. A step of forming a via-hole forming hole having a predetermined depth on a surface of a semiconductor substrate on which an active element is formed, and a resist is filled in the via-hole forming hole and the entire surface of the substrate is covered. As described above, a step of exposing and developing the resist using a mask having an opening in a required portion to leave the resist only in the holes for forming via holes, and a heat treatment to deform the resist to transform the substrate. A step of flattening the step of the via hole forming hole on the surface, a step of forming a lower resist for plating on the active element forming portion, and a metal film being formed on the entire surface of the substrate as a power supply layer for performing electrolytic plating After that, a step of forming an upper layer resist serving as a mask at the time of electrolytic plating for forming a plating electrode and a plating wiring, and an electrolytic plating is selectively performed only in the opening of the upper layer resist. A step of removing the upper layer resist, removing unnecessary portions of the power feeding layer, and further removing the lower layer resist, and processing the substrate until the via hole forming hole opens from the back surface. Forming a via hole by removing the resist filled in the via hole,
And a step of forming a metal film on the inner surface of the via hole and the back surface of the substrate. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of processing the substrate until a via hole forming hole is opened from the back surface to form a via hole, the entire back surface of the substrate is processed. A method of manufacturing a semiconductor device, wherein a via hole is formed. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the via hole by processing the substrate until the via hole forming hole is opened from the back surface is performed by mechanically treating the entire back surface of the substrate. And a step of forming a via hole by processing only a portion directly below the via hole forming hole of the substrate, the method of manufacturing a semiconductor device. 8. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor substrate is a GaAs substrate. 9. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which an active element is formed, a resist is filled in the via hole forming hole, and the entire surface of the substrate is covered. After coating, the resist is exposed and developed using a mask that has openings in the required parts, leaving the resist only in the holes for forming via holes, and performing heat treatment to deform the resist to form via holes on the substrate surface. The level difference of the hole is made flat, the plated electrode and the plated wiring are formed on the surface of the substrate, and the entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole. A semiconductor device, characterized in that the filled resist is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. 10. The semiconductor device according to claim 9, wherein the inside of the via hole is completely filled with a metal film. 11. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which an active element is formed, a resist is filled in the via hole forming hole, and the whole surface of the substrate is covered. After coating, the resist is exposed and developed using a mask that has openings in the required parts, leaving the resist only in the holes for forming via holes, and performing heat treatment to deform the resist to form via holes on the substrate surface. Flatten the step of the hole, form a plating electrode and plating wiring on the surface of the substrate, and process the entire back surface of the substrate to a thickness sufficient to maintain mechanical strength. The via hole is formed by processing until the hole forming hole is opened from the back surface, and the resist filled in the via hole is removed. , And a semiconductor device which is characterized in that by forming a metal film on the rear surface of the substrate. 12. The semiconductor device according to claim 11, wherein the inside of the via hole is completely filled with a metal film. 13. A step of forming a recess on the surface of a semiconductor substrate on which an active element is formed, a step of filling the inside of the recess with a resist and applying the resist so as to cover the entire surface of the substrate, and a step of etching back. The step of flattening the step of the concave portion on the substrate surface by removing the resist on the unnecessary portion of the substrate surface, the step of forming the plating electrode and the plated wiring on the substrate surface, and the resist filling the concave portion are removed. A method of manufacturing a semiconductor device, comprising: 14. The method for manufacturing a semiconductor device according to claim 13, wherein the step of applying a resist so as to fill the inside of the recess and cover the entire surface of the substrate is an oxygen plasma treatment. A step of performing, a step of thereafter applying a solvent of the same component as the solvent in the resist component to the surface of the semiconductor substrate, and a step of applying a resist to the surface of the semiconductor substrate before the applied solvent dries. A method of manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 14, wherein the oxygen plasma treatment performed on the surface of the semiconductor substrate is 200 W to 300 W.
A method for manufacturing a semiconductor device, which is performed for 10 to 30 seconds. 16. A step of forming a via-hole forming hole having a predetermined depth on a surface of a semiconductor substrate on which active elements are formed, and a resist is filled in the via-hole forming hole and covers the entire surface of the substrate. As described above, a step of flattening the step of the via hole forming hole on the substrate surface by removing the resist on the unnecessary portion of the substrate surface by the etch back method, and a plating process on the active element forming portion. Step of forming a lower resist for use, and a step of forming a metal film on the entire surface of the substrate as a power supply layer for performing electroplating, and then forming an upper layer resist serving as a mask during electroplating for forming a plating electrode and a plating wiring. And a step of selectively electrolytically plating only the openings of the upper layer resist, removing the upper layer resist, and removing unnecessary portions of the power feeding layer, In addition, a step of removing the lower layer resist, a step of forming the via hole by processing the substrate until the via hole forming hole is opened from the back surface, and after removing the resist filled in the via hole,
And a step of forming a metal film on the inner surface of the via hole and the back surface of the substrate. 17. The method of manufacturing a semiconductor device according to claim 16, wherein the step of processing the substrate until a via-hole forming hole is opened from the back surface to form a via hole, the entire back surface of the substrate is processed. A method of manufacturing a semiconductor device, wherein a via hole is formed. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the step of forming the via hole by processing the substrate until the via hole forming hole is opened from the back surface is performed by mechanically treating the entire back surface of the substrate. And a step of forming a via hole by processing only a portion directly below the via hole forming hole of the substrate, the method of manufacturing a semiconductor device. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the semiconductor substrate is a GaAs substrate. 20. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which an active element is formed, a resist is filled in the via hole forming hole, and the whole surface of the substrate is covered. By coating and removing the resist on the unnecessary portion of the substrate surface by the etch-back method, the steps of the holes for forming via holes on the substrate surface are flattened, and the plated electrodes and the plated wiring are formed on the substrate surface. The entire back surface of the via hole is processed until the via hole forming hole is opened from the back surface to form a via hole, the resist filled in the via hole is removed, and a metal film is formed on the inside surface of the via hole and the back surface of the substrate. A semiconductor device comprising: 21. The semiconductor device according to claim 20, wherein the inside of the via hole is completely filled with a metal film. 22. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which an active element is formed, a resist is filled in the via hole forming hole, and the whole surface of the substrate is covered. By coating and removing the resist on the unnecessary portion of the substrate surface by the etch-back method, the steps of the holes for forming via holes on the substrate surface are flattened, and the plated electrodes and the plated wiring are formed on the substrate surface. The entire back surface of the substrate to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole. The semiconductor device, characterized in that the resist filled in is removed, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. 23. The semiconductor device according to claim 22, wherein the inside of the via hole is completely filled with a metal film. 24. A step of forming a recess on the surface of a semiconductor substrate on which an active element is formed, a step of performing oxygen plasma treatment on the surface of the semiconductor substrate, and a solvent having the same component as the solvent in the resist component. A step of applying to the surface, a step of applying a resist to the surface of the semiconductor substrate before the applied solvent dries, a step of leaving the resist only in the recesses to flatten the step on the substrate surface, A method of manufacturing a semiconductor device, comprising: a step of forming a plating electrode and a plating wiring on a surface of a substrate; and a step of removing the resist filled in the recess. 25. The method of manufacturing a semiconductor device according to claim 24, wherein the oxygen plasma treatment performed on the surface of the semiconductor substrate is 200 W to 300 W.
A method for manufacturing a semiconductor device, which is performed for 10 to 30 seconds. 26. The method of manufacturing a semiconductor device according to claim 24, wherein the step of flattening the step on the surface of the substrate by leaving the resist only in the recess uses the mask having an opening in a required portion. Manufacturing of a semiconductor device, which comprises a step of exposing and developing the resist to leave the resist only in the concave portion, and a step of performing heat treatment to deform the resist to flatten the step of the concave portion on the substrate surface. Method. 27. The method of manufacturing a semiconductor device according to claim 26, wherein a resist that does not undergo glass transition at a temperature of a subsequent heat treatment is used as the resist left only in the recess. 28. The method of manufacturing a semiconductor device according to claim 24, wherein the step of flattening the step on the substrate surface by leaving the resist only in the recessed portion removes unnecessary portions of the substrate surface by an etchback method. A method of manufacturing a semiconductor device, wherein the step of the recess on the surface of the substrate is flattened by removing the resist. 29. A step of forming a via-hole forming hole having a predetermined depth on the surface of a semiconductor substrate on which an active element is formed, a step of performing oxygen plasma treatment on the surface of the semiconductor substrate, and a solvent in the resist component. A step of applying a solvent of the same component to the surface of the semiconductor substrate, a step of applying a resist to the surface of the semiconductor substrate before the applied solvent dries, leaving the resist only in the via hole forming holes, A step of flattening the steps on the surface of the substrate, a step of forming a lower layer resist for plating on the active element forming portion, and a metal film formed on the entire surface of the substrate as a power supply layer for electrolytic plating, and then a plating electrode And a step of forming an upper layer resist that serves as a mask during electrolytic plating for forming plated wiring, and a step of selectively electrolytically plating only the openings of the upper layer resist. And a step of removing the upper layer resist, removing an unnecessary portion of the power feeding layer, and further removing the lower layer resist, and processing the substrate until the via hole forming hole is opened from the back surface to form a via hole. After the step of forming and removing the resist filled in the via hole,
And a step of forming a metal film on the inner surface of the via hole and the back surface of the substrate. 30. The method of manufacturing a semiconductor device according to claim 29, wherein the step of processing the substrate until a via hole forming hole is opened from the back surface to form a via hole, the entire back surface of the substrate is processed. A method of manufacturing a semiconductor device, wherein a via hole is formed. 31. The method of manufacturing a semiconductor device according to claim 29, wherein the step of forming the via hole by processing the substrate until the via hole forming hole is opened from the rear surface is performed by mechanically treating the entire rear surface of the substrate. And a step of forming a via hole by processing only a portion directly below the via hole forming hole of the substrate, the method of manufacturing a semiconductor device. 32. The method of manufacturing a semiconductor device according to claim 31, wherein the semiconductor substrate is a GaAs substrate. 33. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which active elements are formed, oxygen plasma treatment is performed on the surface of the semiconductor substrate, and a solvent having the same composition as the solvent in the resist composition is formed. Is applied to the surface of the semiconductor substrate, before the applied solvent is dried, a resist is applied to the surface of the semiconductor substrate, leaving the resist only in the via-hole forming holes to flatten the step on the surface of the substrate, A plating electrode and a plating wiring are formed on the surface of the substrate, the entire back surface of the substrate is processed until a via hole forming hole is opened from the back surface to form a via hole, and the resist filled in the via hole is removed. A semiconductor device, wherein a metal film is formed on the inner surface of the via hole and the back surface of the substrate. 34. The semiconductor device according to claim 33, wherein the inside of the via hole is completely filled with a metal film. 35. A via hole forming hole having a predetermined depth is formed on a surface of a semiconductor substrate on which an active element is formed, oxygen plasma treatment is performed on the surface of the semiconductor substrate, and a solvent having the same composition as the solvent in the resist composition is formed. Is applied to the surface of the semiconductor substrate, before the applied solvent is dried, a resist is applied to the surface of the semiconductor substrate, leaving the resist only in the via-hole forming holes to flatten the step on the surface of the substrate, A plating electrode and a plating wiring are formed on the surface of the substrate, and the entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength. Only the portion directly below the via hole forming hole of the substrate has a via hole forming hole from the back surface. Process to form an opening to form a via hole, remove the resist filled in the via hole, and remove the resist on the inner surface of the via hole and the back surface of the substrate. A semiconductor device comprising a metal film. 36. The semiconductor device according to claim 35, wherein the inside of the via hole is completely filled with a metal film. 37. A step of forming an insulating film on the surface of a semiconductor substrate, a step of applying a resist on the entire surface of the insulating film, and a mask for forming a resist pattern having an opening at a recess forming position with respect to the resist. To expose and develop to form an etching mask, to etch the insulating film using the etching mask, and to form a recess on the substrate surface using the same etching mask, and to form the etching mask. The step of removing the used resist, the step of flattening the substrate surface by filling the recesses by growing crystals using the insulating film as a mask, and the insulating film used as the mask during selective crystal growth Removing step, forming an active element on the substrate surface, and forming a plating electrode and a plating wiring on the substrate surface. Process and method of manufacturing a semiconductor device which comprises a step of removing the crystals filled in the recesses by crystal growth to. 38. A step of forming an insulating film on the surface of a semiconductor substrate, and a resist pattern having an opening at a position where holes for forming via holes are formed in the resist after applying a resist on the entire surface of the insulating film. A step of exposing and developing using a mask for forming an etching mask to form an etching mask, and etching the insulating film using the etching mask, and using the same etching mask for forming a via hole of a predetermined depth on the substrate surface A step of forming a hole by etching, a step of removing the resist used as the etching mask, and a step of filling the via hole forming hole by growing a crystal using the insulating film as a mask to flatten the substrate surface. Step, and after removing the insulating film used as a mask during selective crystal growth, an active element is formed on the substrate surface And a step of forming a lower resist for plating on the active element forming portion, and an electrolytic plating for forming a plating electrode and a plating wiring after forming a metal film on the entire surface of the substrate as a power supply layer for performing electrolytic plating. A step of forming an upper layer resist serving as a mask at the time, a step of selectively electrolytically plating only the opening of the upper layer resist, the upper layer resist is removed, and unnecessary portions of the power feeding layer are removed, and further A step of removing the lower layer resist, a step of forming the via hole by processing the substrate until the via hole forming hole is opened from the back surface, and a step of removing the crystal filled in the via hole by crystal growth, And a step of forming a metal film on the inside of the via hole and on the back surface of the substrate. 39. The method of manufacturing a semiconductor device according to claim 38, wherein the step of processing the substrate until a via hole forming hole is opened from the back surface to form a via hole, the entire back surface of the substrate is processed. A method of manufacturing a semiconductor device, wherein a via hole is formed. 40. The method of manufacturing a semiconductor device according to claim 38, wherein the step of forming the via hole by processing the substrate until the via hole forming hole is opened from the back surface is performed by mechanically treating the entire back surface of the substrate. And a step of forming a via hole by processing only a portion directly below the via hole forming hole of the substrate, the method of manufacturing a semiconductor device. 41. The method of manufacturing a semiconductor device according to claim 40, wherein the semiconductor substrate is a GaAs substrate. 42. The method of manufacturing a semiconductor device according to claim 38, wherein the semiconductor substrate is a GaAs substrate, and the step of flattening the substrate surface by growing a crystal is selected for wet etching of the GaAs substrate. Have sex
InGaP is for selective crystal growth, and the step of removing the crystal filled in the via hole by crystal growth is characterized in that the InGaP filled in the via hole by crystal growth is removed with hydrochloric acid. Of manufacturing a semiconductor device. 43. A mask for forming an insulating film on a surface of a semiconductor substrate, applying a resist on the entire surface of the insulating film, and forming a resist pattern having an opening at a position where holes for forming via holes are formed on the resist. To form an etching mask by exposing and developing, etching the insulating film using the etching mask, and then forming a via hole forming hole of a predetermined depth on the substrate surface using the same etching mask. Then, the resist used for the etching mask is removed, the crystal is grown using the insulating film as a mask to fill the via holes to flatten the substrate surface, and the insulation used as a mask during selective crystal growth is used. After removing the film, an active element is formed on the substrate surface, and a plating electrode and a plating wiring are formed on the substrate surface. The entire back surface of the substrate is processed until the via hole forming hole is opened from the back surface to form a via hole, and the crystal filled in the via hole is removed by crystal growth, and the inner surface of the via hole and the substrate A semiconductor device having a metal film formed on the back surface of the semiconductor device. 44. The semiconductor device according to claim 43, wherein the inside of the via hole is completely filled with a metal film. 45. A mask for forming an insulating film on a surface of a semiconductor substrate, applying a resist on the entire surface of the insulating film, and forming a resist pattern having an opening at a position for forming a via hole forming hole on the resist. To form an etching mask by exposing and developing, etching the insulating film using the etching mask, and then forming a via hole forming hole of a predetermined depth on the substrate surface using the same etching mask. Then, the resist used for the etching mask is removed, the crystal is grown using the insulating film as a mask to fill the via holes to flatten the substrate surface, and the insulation used as a mask during selective crystal growth is used. After removing the film, an active element is formed on the substrate surface, and a plating electrode and a plating wiring are formed on the substrate surface. The entire back surface of the substrate is processed to a thickness sufficient to maintain mechanical strength, and only the portion directly below the via hole forming hole of the substrate is processed until the via hole forming hole opens from the back surface to form a via hole. A semiconductor device, wherein crystals filled in the via hole are removed by growth, and a metal film is formed on the inner surface of the via hole and the back surface of the substrate. 46. The semiconductor device according to claim 45, wherein the inside of the via hole is completely filled with a metal film. 47. A step of performing oxygen plasma treatment on the surface of a semiconductor substrate, a step of applying a solvent having the same component as the solvent in the resist component to the surface of the semiconductor substrate, And a step of applying the resist to the surface of the semiconductor substrate. 48. The method of manufacturing a semiconductor device according to claim 47, wherein the oxygen plasma treatment performed on the surface of the semiconductor substrate is 200 W to 300 W.
A method for manufacturing a semiconductor device, which is performed for 10 to 30 seconds.