JPH04124822A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04124822A
JPH04124822A JP24392390A JP24392390A JPH04124822A JP H04124822 A JPH04124822 A JP H04124822A JP 24392390 A JP24392390 A JP 24392390A JP 24392390 A JP24392390 A JP 24392390A JP H04124822 A JPH04124822 A JP H04124822A
Authority
JP
Japan
Prior art keywords
hole
etching
opening
resist mask
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24392390A
Other languages
Japanese (ja)
Inventor
Soichiro Otani
聡一郎 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Nikko Kyodo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd, Nikko Kyodo Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP24392390A priority Critical patent/JPH04124822A/en
Publication of JPH04124822A publication Critical patent/JPH04124822A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce damage at the time of etching, to set the conditions of etching properly and to form a through-hole with a stepped section positively by leaving a resist on the bottom of the through-hole when a second resist mask with a second opening larger than a first opening is formed. CONSTITUTION:A process, in which a metallic electrode 2 is formed onto one main surface of a semiconductor substrate 1, a process, in which a first resist mask 3 with a first opening 3a is shaped onto the other main surface of said substrate 1, a process, in which the substrate 1 in the first opening 3a section is removed through etching by using said resist mask 3 and a through-hole 4, from which the underside of the metallic electrode 2 is exposed, is shaped, a process, in which said resist mask 3 is removed, a process, in which a second resist mask 5 with a second opening 5a larger than the first opening 3a is formed to the forming section of the through-hole 4 in the other main surface of said substrate 1 while leaving a resist 5b on the bottom of the through-hole 4, and a process, in which the substrate 1 in the second opening 5a section is removed through etching up to required depth by employing said second resist mask 5 and a stepped section 6 is formed around the through-hole 4, are provided.

Description

【発明の詳細な説明】 [産業上の利用分野] この発明は、半導体装置の製造方法に関し、特にエツチ
ング法により半導体基板に段部を有する貫通孔を形成す
る方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a through hole having a step in a semiconductor substrate by an etching method.

[従来の技術] 一般に、マイクロ波システムにおいて使用されるモノリ
シックマイクロ波集積回路装置等の分野では、基板裏面
の金属層を利用して放熱性を高める等の目的のため、半
導体基板をエツチングして基板主面の電極につながる貫
通孔を形成し、これに湿式メツキ法等により金属を充填
して基板主面の電極と基板裏面の金属層とをその充填金
属により接続することが行われる。このとき、貫通孔に
金属を良好に堆積するための一つの方法として、貫通孔
周辺に段部を形成して貫通孔の開口部を広くする方法が
ある。
[Prior Art] Generally, in the field of monolithic microwave integrated circuit devices used in microwave systems, semiconductor substrates are etched to improve heat dissipation using a metal layer on the back side of the substrate. A through hole connected to an electrode on the main surface of the substrate is formed, and the through hole is filled with metal by wet plating or the like, and the electrode on the main surface of the substrate and the metal layer on the back surface of the substrate are connected by the filled metal. At this time, one method for satisfactorily depositing metal in the through hole is to form a stepped portion around the through hole to widen the opening of the through hole.

このような貫通孔周辺に段部を形成する従来の方法とし
ては、例えば第2図に示すような方法がある。半導体基
板1の一生面上には、例えばFET素子のソース電極等
となる金属電極2が形成されている。半導体基板1の他
の主面にフォトリソグラフィ技術によりポジレジストを
用いて第1の開ロアaを有するレジストマスク7を形成
する(第2図(a))。このとき、後述する段部形成の
ための第2の開口部についても露光処理のみを予め行う
。7bは、その露光処理済みのレジスト部分を示してい
る(第2図(b))。レジストマスク7を用いて第1の
開ロアa部分の半導体基板1を異方性ドライエツチング
によりエツチング除去し、貫通孔8を形成して半導体基
板1主面の金属電極2の下面を露出させる(第2図(c
))。続けて露光処理済みレジストアbの現像処理を行
いレジストマスク7に第2の開ロアCを開口する(第2
図(d))。
As a conventional method for forming a stepped portion around such a through hole, there is a method as shown in FIG. 2, for example. A metal electrode 2 is formed on the entire surface of the semiconductor substrate 1 to serve as, for example, a source electrode of an FET element. A resist mask 7 having a first open lower a is formed on the other main surface of the semiconductor substrate 1 by photolithography using a positive resist (FIG. 2(a)). At this time, only exposure processing is performed in advance for a second opening for forming a step portion, which will be described later. 7b indicates the exposed resist portion (FIG. 2(b)). Using a resist mask 7, the semiconductor substrate 1 at the first open lower portion a is etched away by anisotropic dry etching to form a through hole 8 and expose the lower surface of the metal electrode 2 on the main surface of the semiconductor substrate 1 ( Figure 2 (c
)). Subsequently, the exposed resist b is developed and a second opening lower C is opened in the resist mask 7 (second
Figure (d)).

再度異方性ドライエツチングにより第2の開ロアc部分
の半導体基板1を所要の深さまでエツチング除去し、貫
通孔8の周辺に段部9を形成する(第2図(e))。
The semiconductor substrate 1 at the second open lower portion C is etched away to a required depth by anisotropic dry etching again to form a stepped portion 9 around the through hole 8 (FIG. 2(e)).

[発明か解決しようとする課題] 貫通孔周辺に段部を形成する従来のエツチング方法では
、金属電極の下面が露出したままで2度目の異方性ドラ
イエツチングを行って貫通孔の周辺に段部を形成するよ
うにしていたため、FET素子等が形成される半導体基
板の一生面側に幻する異方性ドライエツチング時のダメ
ージが大きくなり、ときにはFET素子等の特性に影響
を与えてしまう。これを避けるためには異方性ドライエ
ツチング時のRFパワーを低めにするなとの方法でダメ
ージが少なくなるようにしなければならない。また、1
度目の異方性ドライエツチング後に露光処理済みレジス
トの現像処理を行うために1度目の異方性トライエッチ
ンクによるレジストへのダメージかないようにエツチン
グ条件を定めなければならない。したかって従来の方法
では、エツチングダメージを減少させるためにエツチン
グ条件に制約が加えられ、エツチング装置によっては十
分なエツチング速度が得られない場合があるという問題
かあった。
[Problems to be Solved by the Invention] In the conventional etching method of forming a step around the through hole, a second anisotropic dry etching is performed with the lower surface of the metal electrode exposed to form a step around the through hole. As a result, the damage during anisotropic dry etching that appears on the surface of the semiconductor substrate on which the FET elements and the like are formed becomes large, sometimes affecting the characteristics of the FET elements and the like. In order to avoid this, it is necessary to reduce the damage by lowering the RF power during anisotropic dry etching. Also, 1
In order to develop the exposed resist after the first anisotropic dry etching, etching conditions must be determined so that the resist is not damaged by the first anisotropic try etching. Therefore, in the conventional method, restrictions are imposed on the etching conditions in order to reduce etching damage, and a sufficient etching rate may not be obtained depending on the etching apparatus.

そこで、この発明は、半導体素子が形成される半導体基
板の一生面側に対しエツチング時のダメジが少なく、ま
た、エツチング条件を適切に設定することができて段部
を有する貫通孔を確実に形成することのできる半導体装
置の製造方法を提供することを目的とする。
Therefore, the present invention reduces damage during etching to the whole surface side of a semiconductor substrate on which a semiconductor element is formed, and also enables the etching conditions to be appropriately set to reliably form a through hole having a stepped portion. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform the following steps.

[課題を解決するための手段] この発明は上記課題を解決するために、(a)半導体基
板の一生面上に所要の半導体素子を構成する金属電極を
形成する工程、(b)前記半導体基板の他の主面に第1
の開口を有する第1のレジストマスクを形成する工程、
(c)前記第1のレジストマスクを用いて前記第1の開
口部の前記半導体基板をエツチング除去し、前記金属電
極の下面か露出する貫通孔を形成する工程、(d)前記
第1のレジストマスクを除去する工程、(e)前記半導
体基板の他の主面における前記貫通孔の形成部に前記第
1の開口よりも大なる第2の開口を有する第2のレジス
トマスクを前記貫通孔の底部にレジストを残して形成す
る工程、(f)前記第2のレジストマスクを用いて前記
第2の開口部の前記半導体基板を所要の深さまでエツチ
ング除去し前記貫通孔周辺に段部を形成する工程を有す
ることを要旨とする。
[Means for Solving the Problems] In order to solve the above problems, the present invention provides a step of (a) forming a metal electrode constituting a required semiconductor element on the entire surface of a semiconductor substrate; (b) a step of forming a metal electrode constituting a required semiconductor element; on the other main surface of
forming a first resist mask having an opening of
(c) etching away the semiconductor substrate in the first opening using the first resist mask to form a through hole through which the lower surface of the metal electrode is exposed; (d) the first resist (e) removing a mask, (e) applying a second resist mask having a second opening larger than the first opening in the formation portion of the through hole on the other main surface of the semiconductor substrate; (f) etching away the semiconductor substrate in the second opening to a required depth using the second resist mask to form a stepped portion around the through hole; The gist is that there is a process.

[作用] 1度目のエツチングによる貫通孔の形成後、第1のレジ
ストマスクか除去され、この第1のレジストマスクにお
ける第1の開口よりも大なる第2の開口を有する第2の
レジストマスクが形成され、この時貫通孔の底部にレジ
ストが残される。これにより、貫通孔の底部に残された
レジストがドライエツチング法等による2度目のエツチ
ング時の保護材となって、半導体素子が形成される半導
体基板の一生面側に対するエツチング時のダメージが効
果的に減少する。また、第1のレジストマスクは再度の
現像処理により第2の開口を開口して2度目のエツチン
グ時のマスクとして使用するということはないので、1
度目のエツチング時にレジストへのダメージを考慮する
必要がない。したかって、1度目及び2度目の両エツチ
ング時のエツチング条件を適切に設定することができて
段部を有する貫通孔か確実に形成される。
[Operation] After the through-hole is formed by the first etching, the first resist mask is removed, and a second resist mask having a second opening larger than the first opening in the first resist mask is formed. At this time, resist is left at the bottom of the through hole. As a result, the resist left at the bottom of the through-hole serves as a protective material during the second etching process using dry etching, etc., effectively preventing damage during etching to the entire surface of the semiconductor substrate on which semiconductor elements are formed. decreases to In addition, the first resist mask is not used as a mask for the second etching by opening the second opening through another development process.
There is no need to consider damage to the resist during the second etching. Therefore, the etching conditions for both the first and second etching can be appropriately set, and a through hole having a stepped portion can be reliably formed.

[実施例] 以下、この発明の実施例を第1図を参照して説明する。[Example] Hereinafter, an embodiment of the present invention will be described with reference to FIG.

なお、第1図において前記第2図における部材及び部位
等と同一ないし均等のものは、前記と同一符号を以って
示す。
In FIG. 1, parts that are the same as or equivalent to those in FIG. 2 are designated by the same reference numerals.

この実施例は半導体基板としてGaAs基板か適用され
ている。
In this embodiment, a GaAs substrate is used as the semiconductor substrate.

GaAs基板1の一生面上に、ソース電極等となる金属
電極2等を構成要素とするFET素子等の所要の半導体
素子を形成する。GaAs基板1の厚みは100μm程
度である。GaAs基板1の他の主面に、通常のフォト
リソグラフィにより、ポジレジストを用いて第1の開口
3aを有する第1のレジストマスク3を形成する。第1
のレジストマスク3の膜厚は3μm程度である(第1図
(a))第1のレジストマスク3を用いて第1の開口3
aの部分のGaAs基板]を選択的にエツチング除去し
、金属電極2の下面か露出する貫通孔4を形成する。エ
ツチング時置はS i C14及びC10をエツチング
時スに用いた平行平板型反応性イオンエツチング装置を
用いた。ガス比は、5iC14/C12−1〜3、圧力
は10〜50mTorr−,パワーは400〜800W
にそれぞれ設定した。このような条件に設定した反応性
イオンエツチングにより貫通孔4が確実に形成された(
第1図(b))。第1のレジストマスク3を除去した後
、GaAs基板1の他の主面における貫通孔4の形成部
に、フォトリソグラフィにより第1の開口3aよりも大
なる第2の開口5aを有する第2のレジストマスク5を
形成する。この時、貫通孔4の底部にレジスト5bを残
す。レジスト塗布時に、貫通孔4の底部にはレジストが
他の領域よりも厚く堆積されるので、露光量の制御等に
より貫通孔4の底部に容易にレジスト5bを残すことが
できる(第1図(c))。第2のレジストマスク5を用
いて第2の開口5aの部分のGaAs基板1を選択的に
所要の深さまでエツチング除去し、貫通孔4の周辺に段
部6を形成する。エツチング法は、前記とほぼ同様の条
件に設定した反応性イオンエツチングを用いた。この反
応性イオンエツチングにより貫通孔4の周辺に段部6か
確実に形成され、また、このエツチング時に、貫通孔4
の底部に残されたレジスト5bが保護材となって、FE
T素子等が形成されるGaAs基板1の一生面側に対す
るエツチング時のダメージが効果的に減少した(第1図
(d))。
On the whole surface of the GaAs substrate 1, a required semiconductor element such as an FET element whose constituent elements include a metal electrode 2 serving as a source electrode or the like is formed. The thickness of the GaAs substrate 1 is approximately 100 μm. A first resist mask 3 having a first opening 3a is formed using a positive resist on the other main surface of the GaAs substrate 1 by ordinary photolithography. 1st
The film thickness of the resist mask 3 is about 3 μm (FIG. 1(a)).
The portion a of the GaAs substrate] is selectively etched away to form a through hole 4 through which the lower surface of the metal electrode 2 is exposed. A parallel plate type reactive ion etching apparatus using S i C14 and C10 was used for etching. Gas ratio is 5iC14/C12-1~3, pressure is 10~50mTorr-, power is 400~800W
were set respectively. The through holes 4 were reliably formed by reactive ion etching under these conditions (
Figure 1(b)). After removing the first resist mask 3, a second opening 5a, which is larger than the first opening 3a, is formed by photolithography in the area where the through hole 4 is formed on the other main surface of the GaAs substrate 1. A resist mask 5 is formed. At this time, the resist 5b is left at the bottom of the through hole 4. During resist application, the resist is deposited thicker at the bottom of the through-hole 4 than in other areas, so the resist 5b can be easily left at the bottom of the through-hole 4 by controlling the exposure amount (see Fig. 1). c)). Using the second resist mask 5, the portion of the GaAs substrate 1 in the second opening 5a is selectively etched away to a required depth to form a stepped portion 6 around the through hole 4. As the etching method, reactive ion etching was used under almost the same conditions as above. Through this reactive ion etching, the stepped portion 6 is reliably formed around the through hole 4, and during this etching, the through hole 4 is
The resist 5b left at the bottom of the FE acts as a protective material.
Damage during etching to the full surface side of the GaAs substrate 1 on which T elements and the like are formed is effectively reduced (FIG. 1(d)).

上述したように、この実施例によれば、FET素子等が
形成されるGaAs基板1の一生面側へのダメージが少
なく、且つ1度目、2度目の両エツチング時のエツチン
グ条件の自由度が大きくなって段部6を有する貫通孔4
を確実に形成することが可能となる。
As described above, according to this embodiment, there is less damage to the lifetime side of the GaAs substrate 1 on which FET elements and the like are formed, and there is a greater degree of freedom in the etching conditions during both the first and second etching. A through hole 4 having a stepped portion 6
It becomes possible to form reliably.

なお、上述の実施例において、半導体基板にはGaAs
を適用したが、Si、InP等を適用することもできる
。また、エツチング法として反応性イオンエツチングか
らなる異方性ドライエツチングを適用したか、反応性ス
パッタエツチング、スパッタエツチング等の他の異方性
ドライエツチングを適用することもてきる。さらに、半
導体基板をエツチングするガスは半導体基板材料に依存
しており、例えばGaAsては5iC14/C12の他
+:cc 12 F2102 、CC12F2/不活性
ガス等が用いられる。
Note that in the above embodiment, the semiconductor substrate is made of GaAs.
was applied, but Si, InP, etc. can also be applied. Further, as the etching method, anisotropic dry etching consisting of reactive ion etching is applied, or other anisotropic dry etching such as reactive sputter etching or sputter etching can also be applied. Furthermore, the gas for etching the semiconductor substrate depends on the semiconductor substrate material; for example, for GaAs, 5iC14/C12, +:cc 12 F2102, CC12F2/inert gas, etc. are used.

[発明の効果] 以上説明したように、この発明によれば1、第1のレジ
ストマスクを用いた1度目のエツチングによる貫通孔の
形成後、その第1のレジストマスクを除去し、この第1
のレジストマスクにおける第1の開口よりも大なる第2
の開口を有する第2のレジストマスクを形成し、この時
、貫通孔の底部にレジストを残すようにしたため、貫通
孔の底部に残されたレジストがドライエツチング法等に
よる2度目のエツチング時の保護材となって半導体素子
が形成される半導体基板の一生面側に対するエツチング
時のダメージが効果的に減少する。
[Effects of the Invention] As explained above, according to the present invention, after forming a through hole by the first etching using the first resist mask, the first resist mask is removed and the first resist mask is etched.
The second opening is larger than the first opening in the resist mask.
A second resist mask having an opening was formed, and at this time, the resist was left at the bottom of the through hole, so that the resist left at the bottom of the through hole was protected during the second etching by dry etching etc. Damage during etching to the entire surface of the semiconductor substrate on which semiconductor elements are formed is effectively reduced.

また、第1のレジストマスクは再度の現像処理等を施す
ことにより2度目のエツチング時のマスクとして使用す
るということはないので、1度目のエツチング時にレジ
ストへのダメージを考慮する必要かない。したがって、
1度目、2度目の両エツチング時のエツチング条件を適
切に設定することができて段部を有する貫通孔を確実に
形成することができる。
Further, since the first resist mask is not used as a mask for the second etching by subjecting it to another development process, there is no need to consider damage to the resist during the first etching. therefore,
Etching conditions for both the first and second etching can be appropriately set, and a through hole having a stepped portion can be reliably formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係る半導体装置の製造方法の実施例
を説明するための工程図、第2図は従来の半導体装置の
製造方法を説明するための工程図である。 1:GaAs基板(半導体基板)、 2:金属電極、  3:第1のレジストマスク、3a:
第1の開口、  41貫通孔、 5、第2のレジストマスク、 5a:第2の開口、 5b=貫通孔の底部に残したレジスト、6:段部。
FIG. 1 is a process diagram for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a process diagram for explaining a conventional method for manufacturing a semiconductor device. 1: GaAs substrate (semiconductor substrate), 2: Metal electrode, 3: First resist mask, 3a:
1st opening, 41 through hole, 5, second resist mask, 5a: second opening, 5b = resist left at the bottom of through hole, 6: step portion.

Claims (1)

【特許請求の範囲】 (a)半導体基板の一主面上に所要の半導体素子を構成
する金属電極を形成する工程、 (b)前記半導体基板の他の主面に第1の開口を有する
第1のレジストマスクを形成する工程、(c)前記第1
のレジストマスクを用いて前記第1の開口部の前記半導
体基板をエッチング除去し、前記金属電極の下面が露出
する貫通孔を形成する工程、 (d)前記第1のレジストマスクを除去する工程、(e
)前記半導体基板の他の主面における前記貫通孔の形成
部に前記第1の開口よりも大なる第2の開口を有する第
2のレジストマスクを前記貫通孔の底部にレジストを残
して形成する工程、 (f)前記第2のレジストマスクを用いて前記第2の開
口部の前記半導体基板を所要の深さまでエッチング除去
し前記貫通孔周辺に段部を形成する工程 を有することを特徴とする半導体装置の製造方法。
Scope of Claims: (a) a step of forming a metal electrode constituting a required semiconductor element on one main surface of the semiconductor substrate; (b) a step of forming a metal electrode constituting a required semiconductor element on one main surface of the semiconductor substrate; (c) forming the first resist mask; (c) forming the first resist mask;
etching away the semiconductor substrate in the first opening using a resist mask to form a through hole through which a lower surface of the metal electrode is exposed; (d) removing the first resist mask; (e
) A second resist mask having a second opening larger than the first opening is formed in the other main surface of the semiconductor substrate at a portion where the through hole is formed, leaving resist at the bottom of the through hole. (f) etching away the semiconductor substrate in the second opening to a required depth using the second resist mask to form a stepped portion around the through hole; A method for manufacturing a semiconductor device.
JP24392390A 1990-09-17 1990-09-17 Manufacture of semiconductor device Pending JPH04124822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24392390A JPH04124822A (en) 1990-09-17 1990-09-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24392390A JPH04124822A (en) 1990-09-17 1990-09-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04124822A true JPH04124822A (en) 1992-04-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP24392390A Pending JPH04124822A (en) 1990-09-17 1990-09-17 Manufacture of semiconductor device

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Country Link
JP (1) JPH04124822A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078080A (en) * 2001-08-30 2003-03-14 Fujitsu Ltd Thin film circuit board, manufacturing method therefor, via formed substrate and manufacturing method therefor
JP2014038322A (en) * 2012-07-19 2014-02-27 Sumitomo Electric Ind Ltd Manufacturing method of optical semiconductor element
US20150056743A1 (en) * 2012-03-12 2015-02-26 Mitsubishi Electric Corporation Manufacturing method of solar cell

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003078080A (en) * 2001-08-30 2003-03-14 Fujitsu Ltd Thin film circuit board, manufacturing method therefor, via formed substrate and manufacturing method therefor
JP4703061B2 (en) * 2001-08-30 2011-06-15 富士通株式会社 Thin film circuit board manufacturing method and via forming board forming method
US20150056743A1 (en) * 2012-03-12 2015-02-26 Mitsubishi Electric Corporation Manufacturing method of solar cell
JP2014038322A (en) * 2012-07-19 2014-02-27 Sumitomo Electric Ind Ltd Manufacturing method of optical semiconductor element

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