JPH0497532A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0497532A
JPH0497532A JP21555990A JP21555990A JPH0497532A JP H0497532 A JPH0497532 A JP H0497532A JP 21555990 A JP21555990 A JP 21555990A JP 21555990 A JP21555990 A JP 21555990A JP H0497532 A JPH0497532 A JP H0497532A
Authority
JP
Japan
Prior art keywords
film
plating
opening
photoresist
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21555990A
Other languages
Japanese (ja)
Inventor
Takaaki Kobayashi
孝彰 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21555990A priority Critical patent/JPH0497532A/en
Publication of JPH0497532A publication Critical patent/JPH0497532A/en
Pending legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent electrical short-circuit due to the mutual contact of adjacent metallic plated films or unetched metallic conductive films which are current passage during plating by using first and second photoresist films as masks during plating. CONSTITUTION:In a case where a semiconductor substrate 1 is dipped in a gold plating solution and plating is performed by causing electric current to flow between the anode electrode plate of a plating apparatus with a titanium film 2 as a current passage, a gold plated wiring 7 does not grow in a direction perpendicular to the direction of the growth and adjacent gold plated wirings do not contact with each other as a result of using a first photoresist film 4A and a second photoresist film 4B as masks. Since there is no decrease in the plated region because of misalignment of patternings and fixed as a result of making a second opening portion 6B of the film 4B smaller than a first opening portion 6A of the film 4A, stable gold plating can be performed and electrical short-circuit can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にメッキによ
って配線用の金属メッキ膜を形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a metal plating film for wiring by plating.

〔従来の技術〕[Conventional technology]

従来、この種の金属メッキ膜を有する半導体装置の製造
方法では、下地配線形成終了後に、メッキの際に電流路
となる金属導電膜を形成し、下地配線と金属メッキ膜と
の密着力を強化するための密着用金属膜及びその上層に
下地金属膜と金属メッキ膜が反応することを防止するた
めのバリア用金属膜を形成し、その後フォトレジスト膜
をマスクとしてメッキを行うことによりバリア用金属膜
上に金属メッキ膜を形成し、次でフォトレジスト膜を剥
離した後、金属メッキ膜をマスクとして不要となった金
属導電膜の一部をエツチング除去し、各々の金属メッキ
膜を絶縁分離していた。
Conventionally, in the manufacturing method of semiconductor devices having this type of metal plating film, after the formation of the base wiring is completed, a metal conductive film is formed to serve as a current path during plating to strengthen the adhesion between the base wiring and the metal plating film. A barrier metal film is formed on the adhesion metal film to prevent the base metal film from reacting with the metal plating film, and then plating is performed using the photoresist film as a mask to form the barrier metal film. A metal plating film is formed on the film, and then the photoresist film is peeled off. Then, using the metal plating film as a mask, a part of the unnecessary metal conductive film is removed by etching, and each metal plating film is insulated and separated. was.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の金属メッキ膜の製造方法は、メッキの際
のマスクとして金属メッキ膜の膜厚と同程度の膜厚であ
る単一のフォトレジスト膜を用いているため、基板面内
でのメッキ成長速度にばらつきが生じた場合などは、金
属メッキ膜はフォトレジスト膜より厚くなった部分で容
易に成長方向に対して垂直方向へも肥大してしまい、隣
接した金属メッキ膜が接触したり、あるいは、金属導電
膜を異方性ドライエツチングでエツチング除去する際に
その肥大部がマスクとなりエツチング残りが生じ、電気
的に短絡してしまうという問題点があった。
The conventional metal plating film manufacturing method described above uses a single photoresist film with a thickness similar to that of the metal plating film as a mask during plating. If there are variations in the growth rate, the metal plating film will easily enlarge in the direction perpendicular to the growth direction at the part where it is thicker than the photoresist film, causing adjacent metal plating films to come into contact with each other, or Another problem is that when a metal conductive film is removed by anisotropic dry etching, the enlarged portion acts as a mask and leaves etching residue, resulting in an electrical short circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、素子および下層配線
が形成された半導体基板に、メッキ用電流路となる導電
膜と密着用金属膜とバリア用金属膜からなる下地膜を形
成する工程と、下地膜を含む全面に第1のフォトレジス
ト膜を形成したのちパターニングし金属メッキ層形成領
域に第1の開口部を形成する工程と、全面にポリイミド
系樹脂膜を形成し前記第1の開口部を埋め込んだのちエ
ツチングし、前記第1のフォトレジスト膜の表面を露出
させると共に前記第1の開口部内のみにポリイミド系樹
脂膜を残す工程と、露出した前記第1のフォトレジスト
膜を含む全面に第2のフォトレジスト膜を形成したのち
パターニングし前記第1の開口部の上部に第1の開口部
より小さい第2の開口部を形成する工程と、前記第2の
開口部を有する第2のフォトレジスト膜をマスクとし前
記第1の開口部内のポリイミド系樹脂膜を除去し前記下
地膜を露出させる工程と、前記第1および第2のフォト
レジスト膜をマスクとしメッキ法により露出した前記下
地膜上に金属メッキ層を形成する工程とを含んで構成さ
れる。
The method for manufacturing a semiconductor device of the present invention includes a step of forming a base film consisting of a conductive film serving as a current path for plating, an adhesion metal film, and a barrier metal film on a semiconductor substrate on which elements and lower wiring are formed; A step of forming a first photoresist film on the entire surface including the base film and then patterning it to form a first opening in the metal plating layer forming area, and forming a polyimide resin film on the entire surface and forming the first opening. embedding and etching to expose the surface of the first photoresist film and leaving a polyimide resin film only in the first opening; forming a second photoresist film and then patterning it to form a second opening smaller than the first opening above the first opening; using a photoresist film as a mask to remove the polyimide resin film in the first opening to expose the base film; and using the first and second photoresist films as masks and exposing the base film by plating. and forming a metal plating layer thereon.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(、a)〜(e)は本発明の第1の実施例を説明
するための工程順に示した半導体チップの断面図であり
、本発明をテープキャリア式集積回路の金メッキ配線に
適用した場合である。
FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, in which the present invention is applied to gold-plated wiring of a tape carrier type integrated circuit. This is the case.

先ず第1図(a>のように、素子及び下層配線(図示せ
ず)を完成した後の半導体基板1の表面全体にメッキを
行う際の電流路となる金属導電膜として、膜厚的0.3
1μmのチタン膜2を被着する0次でこのチタン膜2上
に、選択エツチング法又はリフトオフ法等でメッキの際
の下地バリア膜となる膜厚0,2μmのチタン・白金p
IA3を形成する。これは下地との密着強度を高めるた
めのチタン膜く膜厚O11μm)と金の拡散を防止する
ための白金膜(膜厚0.1μm)の2層構造になってい
る。
First, as shown in FIG. 1 (a), a metal conductive film with a film thickness of 0 is used as a metal conductive film that will serve as a current path when plating the entire surface of the semiconductor substrate 1 after completing the elements and lower layer wiring (not shown). .3
A titanium film 2 with a thickness of 0.2 μm is deposited on this titanium film 2 using a selective etching method or a lift-off method to form a base barrier film during plating.
Form IA3. This has a two-layer structure: a titanium film (thickness: 11 μm) to increase adhesion strength to the base, and a platinum film (thickness: 0.1 μm) to prevent gold diffusion.

次に第1図(b)のように、常法のパターニングにより
第1の開口部6A内にこのチタン・白金膜3を露呈させ
た第1のフォトレジストM4Aを形成する。ここに第1
のフォトレジスト膜4Aは、チタン・白金膜3を容易に
しかも安定性よく露呈できる様に比較的薄い膜厚(約3
.0μm)で塗布・形成する。次で、膜厚的8μmのポ
リイミド樹脂を全面に塗布し第1の開口部6A内を埋め
て基板表面を平坦化した後、エッチバック法により第1
のフォトレジストM4Aの膜厚までポリイミド樹脂を均
一にエツチングし、第1のフォトレジスト膜4Aの第1
の開口部6A内のみにポリイミド樹脂膜5を残す。
Next, as shown in FIG. 1(b), a first photoresist M4A exposing the titanium/platinum film 3 is formed in the first opening 6A by patterning using a conventional method. here the first
The photoresist film 4A has a relatively thin film thickness (approximately 3
.. 0 μm). Next, a polyimide resin with a film thickness of 8 μm is applied to the entire surface to fill the inside of the first opening 6A and flatten the substrate surface, and then the first
The polyimide resin is uniformly etched to the film thickness of the photoresist M4A of the first photoresist film M4A.
The polyimide resin film 5 is left only in the opening 6A.

次に第1図(c)のように、常法によりパターニングし
て第2の開口部6Bを形成した膜厚3.0μmの第2の
フォトレジスト膜4Bをマスクとしてポリイミド樹脂膜
5をヒドラジン系溶液で全てエツチング除去し、チタン
・白金膜3を露呈させる。ここで第2のフォトレジスト
膜4Bの第2の開口部6Bは、第1のフォトレジスト膜
4Aの第1の開口部6Aより小さくする。このためその
断面形状はオーバーハング状となってぃる。
Next, as shown in FIG. 1(c), using as a mask the second photoresist film 4B with a thickness of 3.0 μm, which has been patterned by a conventional method to form a second opening 6B, the polyimide resin film 5 is coated with a hydrazine-based film. All etching is removed with a solution to expose the titanium/platinum film 3. Here, the second opening 6B of the second photoresist film 4B is made smaller than the first opening 6A of the first photoresist film 4A. Therefore, its cross-sectional shape is overhanging.

次に第1図(d)のように、半導体基板1を金メッキ液
中に浸漬し、チタン膜2を電流路としてメッキ装置側の
陽極電極板との間に電流を流してメッキを行うことによ
り、チタン・白金M3上に金メッキ層、即ち膜厚的5.
0μmの金メッキ配817を形成する。この際、半導体
基板1内での金メッキ成長速度は均一ではないため局所
的に金メッキ膜厚が厚くなる領域が発生しやすい。しか
し、第1のフォトレジスト膜4A及び第2のフォトレジ
スト膜4Bをメッキ時のマスクとしているため、金メッ
キ配線7は成長方向に対して垂直方向へ成長することは
なく、隣接した金メッキ配線が接触することはない。例
えば、従来の方法て本実施例と同様に3.0μm厚のフ
ォトレジストマスクで5.0μmの金メッキ配線を形成
する場合、金メッキ配線の間隔は最低4.0μm以上必
要であるが、本実施例によれば1.0μmの間隔があれ
ば充分である。また、第2のフォトレジスト膜4Bの第
2の開口部6Bは、第1のフォトレジスト膜4Aの第1
の開口部6Aより小さいため、パターニング時の位置ず
れによるメッキ領域の減少はなく一定であるため安定し
た金メッキが行える。
Next, as shown in FIG. 1(d), plating is performed by immersing the semiconductor substrate 1 in a gold plating solution and passing a current through the titanium film 2 as a current path between it and the anode electrode plate on the plating apparatus side. , a gold plating layer on titanium/platinum M3, that is, a film thickness of 5.
A gold plating pattern 817 with a thickness of 0 μm is formed. At this time, since the growth rate of the gold plating within the semiconductor substrate 1 is not uniform, regions where the gold plating film is locally thick tend to occur. However, since the first photoresist film 4A and the second photoresist film 4B are used as masks during plating, the gold-plated wiring 7 does not grow perpendicular to the growth direction, and adjacent gold-plated wirings come into contact with each other. There's nothing to do. For example, when forming 5.0 μm gold-plated wiring using a 3.0 μm thick photoresist mask using the conventional method as in this embodiment, the interval between the gold-plated wires must be at least 4.0 μm; According to the above, a spacing of 1.0 μm is sufficient. Further, the second opening 6B of the second photoresist film 4B is connected to the first opening 6B of the first photoresist film 4A.
Since the opening 6A is smaller than the opening 6A, the plating area does not decrease due to positional deviation during patterning and remains constant, so stable gold plating can be performed.

その後、第1図(e)のように、第2のフォトレジスト
膜4B及び第1のフォトレジスト膜4Aを順次除去した
後、金属導電膜であるチタン膜2をエツチング除去し各
々の金メッキ配線7を絶縁分離することより金メッキ配
線7を有する半導体装置が完成する。
Thereafter, as shown in FIG. 1(e), after sequentially removing the second photoresist film 4B and the first photoresist film 4A, the titanium film 2, which is a metal conductive film, is removed by etching, and each gold-plated wiring 7 is removed. By insulating and separating them, a semiconductor device having gold-plated wiring 7 is completed.

このように第1の実施例によれば、第1及び第2のフォ
トレジスト膜をマスクとして金メッキを行っているので
、金メッキの成長速度が基板内で多少ばらついても、金
メッキ配線を信頼性よく安定して形成することができる
。ここで、メッキ時の電流路としてのチタン膜や、下地
バリア膜としてのチタン・白金膜には他の金属を使用し
てもよく、また金属メッキ配線としては、全以外の金属
も使用することができる。
According to the first embodiment, gold plating is performed using the first and second photoresist films as masks, so even if the growth rate of the gold plating varies somewhat within the substrate, the gold plating wiring can be formed reliably. Can be formed stably. Here, other metals may be used for the titanium film as the current path during plating and the titanium/platinum film as the underlying barrier film, and metals other than all metals may be used for the metal plating wiring. I can do it.

第2図(a)〜(e)は本発明の第2の実施例を説明す
るための製造工程順に示した半導体チップの断面図であ
る。
FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip shown in the order of manufacturing steps for explaining a second embodiment of the present invention.

tず第2図(a)のように、素子及び下層配線を完成し
た後の半導体基板21の表面全体に、下地との密着力を
強化するための膜厚的0.5μmのチタン膜22を被着
する。次でこの上に下地と金メッキ配線が反応すること
を防止するための膜厚的0.1μmの白金膜23を被着
する。ここにチタン膜22及び白金膜23は基板表面全
体に被着しであるのでメッキを行う際の各金メッキ配線
間の電流路となる。さらにその上層に、メッキを行う際
のマスクの一部となる膜厚的3.0μmの第1のポジ型
フォトレジスト膜24Aを形成したのちパターニングし
て、金メッキ配線を形成する領域に第1の開口部26A
を形成し白金膜23の一部を露呈させる。
As shown in FIG. 2(a), a titanium film 22 with a thickness of 0.5 μm is applied to the entire surface of the semiconductor substrate 21 after completing the elements and lower wiring to strengthen the adhesion with the underlying layer. to adhere to. Next, a platinum film 23 with a thickness of 0.1 .mu.m is deposited on top of this to prevent reaction between the base and the gold-plated wiring. Since the titanium film 22 and the platinum film 23 are adhered to the entire surface of the substrate, they serve as current paths between the respective gold-plated wirings during plating. Furthermore, a first positive type photoresist film 24A with a film thickness of 3.0 μm is formed on top of the film to serve as a part of a mask during plating, and then patterned to form a first positive photoresist film 24A in the area where the gold-plated wiring is to be formed. Opening 26A
is formed to expose a part of the platinum film 23.

次に第2図(b)のように、膜厚的8.0μmのポリイ
ミド樹脂を塗布し第1の開口部26Aを埋めて基板表面
を平坦化した後、エッチバック法により第1のポジ型フ
ォトレジストM24にの膜厚才でポリイミド樹脂膜を均
一にエツチングし、第1のポジ型フォトレジストM24
Aの第1の開口部26A内のみにポリイミド樹脂膜25
を残す。
Next, as shown in FIG. 2(b), after applying a polyimide resin with a film thickness of 8.0 μm to fill the first opening 26A and flattening the substrate surface, the first positive type is formed by an etch-back method. The polyimide resin film is uniformly etched depending on the film thickness of the photoresist M24, and a first positive photoresist M24 is formed.
The polyimide resin film 25 is formed only within the first opening 26A of A.
leave.

その後、第2図(c)のように、常法によりパターニン
グした第2のポジ型フォトレジスト膜24Bを形成する
。この時ポリイミド樹脂I!25のポジ型フォトレジス
トの現象液に対する溶解性を利用して、第2のポジ型フ
ォトレジスト膜24Bの第2の開口部26Bを形成する
途中の現像工程で、ポリイミド樹脂膜25も同時にエツ
チング除去して白金膜23を露呈させる。また、ここで
第2のポジ型フォトレジスト膜24Bの第2の開口部2
6Bは第1のポジ型フォトレジストM24Aの第1の開
口部26Aより小さく、その断面形状はオーバーハング
状となっている。
Thereafter, as shown in FIG. 2(c), a second positive photoresist film 24B is formed by patterning using a conventional method. At this time, polyimide resin I! Utilizing the solubility of the positive type photoresist No. 25 in the phenomenon liquid, the polyimide resin film 25 is also etched away at the same time in the developing process during the formation of the second opening 26B of the second positive photoresist film 24B. The platinum film 23 is exposed. Also, here, the second opening 2 of the second positive photoresist film 24B
6B is smaller than the first opening 26A of the first positive photoresist M24A, and has an overhanging cross-sectional shape.

その後、第2図(d)のように、半導体基板21を金メ
ッキ液中に浸漬し、チタン膜22及び白金膜23を電流
路としてメッキ装置側の陽極電極板との間に電流を流し
てメッキを行うことにょリ、白金膜23の露呈されてい
る領域に金メッキ層、即ち膜厚的5.O)、tmの金メ
ッキ配線27を形成する。ここで、第1の実施例と同様
に、金メッキ配線は成長方向に対して垂直方向へ成長す
ることはなく、金メッキ配線27の配線間隔が縮まるこ
とはない。
Thereafter, as shown in FIG. 2(d), the semiconductor substrate 21 is immersed in a gold plating solution, and a current is passed between the titanium film 22 and the platinum film 23 as current paths and the anode electrode plate on the plating apparatus side, thereby plating the semiconductor substrate 21. By doing this, a gold plating layer is formed on the exposed area of the platinum film 23, that is, the film thickness is 5. O), tm gold-plated wiring 27 is formed. Here, as in the first embodiment, the gold-plated wiring does not grow in a direction perpendicular to the growth direction, and the interval between the gold-plated wiring 27 does not decrease.

その後、第2図(e)のように、第2のポジ型フォトレ
ジストl124B及び第1のポジ型フォトレジスト膜2
4Aを除去した後、アルゴンガスを用いた異方性ドライ
エツチングにより白金膜23及びチタン膜22を連続エ
ツチングし、各々の金メッキ配l!27を電気的に絶縁
分離することにより金メッキ配線27を有する半導体装
置が完成する。この際、金メッキ配lI27は成長方向
に対して垂直方向へ肥大していないので、導電膜である
白金膜23及びチタン膜22は異方性ドライエツチング
により金メッキ配線27のパターン通りにエツチング除
去されるため隣接する金メ・ツキ配線27が電気的に短
絡することはない。
After that, as shown in FIG. 2(e), the second positive photoresist film 124B and the first positive photoresist film 2 are
After removing 4A, the platinum film 23 and the titanium film 22 are continuously etched by anisotropic dry etching using argon gas, and each gold plating layer is removed. By electrically insulating and separating wires 27, a semiconductor device having gold-plated wiring 27 is completed. At this time, since the gold plated interconnect 27 does not enlarge in the direction perpendicular to the growth direction, the platinum film 23 and the titanium film 22, which are conductive films, are etched away according to the pattern of the gold plated interconnect 27 by anisotropic dry etching. Therefore, there is no possibility of electrical short-circuiting between adjacent gold-plated wirings 27.

本第2の実施例では、ポリイミド樹脂M25の除去を第
2のポジ型フォトレジストM24Bのパターニングと同
時に行えるので、第1の実施例に比ベニ程を少くできる
利点がある。
In the second embodiment, since the polyimide resin M25 can be removed at the same time as the patterning of the second positive photoresist M24B, there is an advantage over the first embodiment that the amount of burnout can be reduced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、メッキの際のマスクとし
て第1及び第2のフォトレジスト膜を用いているので、
金属メッキ膜の成長方向に対する垂直方向への肥大化を
抑えて、隣接した金属メッキ膜の接触、あるいはメッキ
の際の電流路である金属導電膜のエツチング残りによる
電気的な短絡を防止できる効果がある。
As explained above, the present invention uses the first and second photoresist films as masks during plating, so
It has the effect of suppressing the enlargement of the metal plating film in the direction perpendicular to the growth direction and preventing electrical short circuits due to contact between adjacent metal plating films or etching residue of the metal conductive film, which is the current path during plating. be.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明の第1の実施例を説明す
るための工程順に示す半導体チップの断面図、第2図(
a)〜(e)は本発明の第2の実施例を説明するための
工程順に示す半導体チップの断面図である。 1・・・半導体基板、2・・・チタン膜、3・・・チタ
ン・白金膜、4A・・・第1のフォトレジスト膜、4B
・・・第2のフォトレジスト膜、5・・・ポリイミド樹
脂膜、6A・・・第1の開口部、6B・・・第2の開口
部、7・・・金メッキ配線、21・・・半導体基板、2
2・・・チタン膜、23・・・白金膜、24A・・・第
1のポジ型フォトレジスト膜、24B・・・第2のポジ
型フォトレジスト膜、25・・・ポリイミド樹脂膜、2
6A・・・第1の開口部、26B・・・第2の開口部、
27・・・金メッキ配線。
1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIG.
FIGS. 7A to 8E are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Titanium film, 3... Titanium/platinum film, 4A... First photoresist film, 4B
...Second photoresist film, 5...Polyimide resin film, 6A...First opening, 6B...Second opening, 7...Gold plated wiring, 21...Semiconductor Substrate, 2
2...Titanium film, 23...Platinum film, 24A...First positive photoresist film, 24B...Second positive photoresist film, 25...Polyimide resin film, 2
6A...first opening, 26B...second opening,
27...Gold plated wiring.

Claims (1)

【特許請求の範囲】[Claims]  素子および下層配線が形成された半導体基板上に、メ
ッキ用電流路となる導電膜と密着用金属膜とバリア用金
属膜からなる下地膜を形成する工程と、下地膜を含む全
面に第1のフォトレジスト膜を形成したのちパターニン
グし金属メッキ層形成領域に第1の開口部を形成する工
程と、全面にポリイミド系樹脂膜を形成し前記第1の開
口部を埋め込んだのちエッチングし、前記第1のフォト
レジスト膜の表面を露出させると共に前記第1の開口部
内のみにポリイミド系樹脂膜を残す工程と、露出した前
記第1のフォトレジスト膜を含む全面に第2のフォトレ
ジスト膜を形成したのちパターニングし前記第1の開口
部の上部に第1の開口部より小さい第2の開口部を形成
する工程と、前記第2の開口部を有する第2のフォトレ
ジスト膜をマスクとし前記第1の開口部内のポリイミド
系樹脂膜を除去し前記下地膜を露出させる工程と、前記
第1および第2のフォトレジスト膜をマスクとしメッキ
法により露出した前記下地膜上に金属メッキ層を形成す
る工程とを含むことを特徴とする半導体装置の製造方法
A step of forming a base film consisting of a conductive film to serve as a current path for plating, a metal film for adhesion, and a metal film for barrier on the semiconductor substrate on which elements and lower layer wiring have been formed, and a step of forming a base film on the entire surface including the base film. A step of forming a photoresist film and patterning it to form a first opening in the metal plating layer formation area, forming a polyimide resin film on the entire surface, filling the first opening, etching it, and etching the first opening. exposing the surface of the first photoresist film and leaving a polyimide resin film only in the first opening, and forming a second photoresist film on the entire surface including the exposed first photoresist film. Thereafter, a step of patterning to form a second opening smaller than the first opening above the first opening, and using a second photoresist film having the second opening as a mask, a step of removing the polyimide resin film in the opening to expose the base film, and a step of forming a metal plating layer on the exposed base film by a plating method using the first and second photoresist films as masks. A method for manufacturing a semiconductor device, comprising:
JP21555990A 1990-08-15 1990-08-15 Manufacture of semiconductor device Pending JPH0497532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21555990A JPH0497532A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21555990A JPH0497532A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0497532A true JPH0497532A (en) 1992-03-30

Family

ID=16674437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21555990A Pending JPH0497532A (en) 1990-08-15 1990-08-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0497532A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19532343A1 (en) * 1994-09-08 1996-03-14 Mitsubishi Electric Corp Semiconductor device mfr. for microwave communication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19532343A1 (en) * 1994-09-08 1996-03-14 Mitsubishi Electric Corp Semiconductor device mfr. for microwave communication

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