JPS6179261A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6179261A JPS6179261A JP20059084A JP20059084A JPS6179261A JP S6179261 A JPS6179261 A JP S6179261A JP 20059084 A JP20059084 A JP 20059084A JP 20059084 A JP20059084 A JP 20059084A JP S6179261 A JPS6179261 A JP S6179261A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- hole
- layer
- small hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 238000010030 laminating Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 19
- 238000000605 extraction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 6
- 229910052719 titanium Inorganic materials 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000003486 chemical etching Methods 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はバイアホール（Ｖｉａ Ｈｏ１ｅ）を有する
半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device having a via hole.
以下、ＧａＡｓ電力用ＦＥＴを例にとり説明する。 A description will be given below using a GaAs power FET as an example.
電力用ＦＥＴは高出力化、高周波化に応じて単位チップ
当りのゲート幅を大きくする高密度化、電力利得の低下
を抑えるソースインダクタンスの低減化や低いチャンネ
ル温度での動作、即ち信頼性を高めるための熱抵抗の低
減化等について充分考慮されなければならない。その手
段の一つとしてソースインダクタンスの低減、熱抵抗の
低減に利点があるバイアホールｐ ）（５（ｐｌ、ａｔ
ｅｄ Ｈｅａｔｓｉｎｋ）構造がある。このバイアホー
ルＰＨ３構造は、ＦＥＴ基板にバイアホールを設け、表
面のソース電極と裏面の金属層との電気的導通を図り、
さらに裏面に厚いヒートシンク層を形成した構造上の特
徴を有する。Power FETs are becoming more dense by increasing the gate width per unit chip in response to higher output and higher frequencies, reducing source inductance to suppress a drop in power gain, and operating at a lower channel temperature, which improves reliability. Therefore, sufficient consideration must be given to reducing thermal resistance. One of the means for achieving this is via holes p ) (5 (pl, at
ed Heatsink) structure. This via hole PH3 structure provides a via hole in the FET substrate to establish electrical continuity between the source electrode on the front surface and the metal layer on the back surface.
Furthermore, it has a structural feature in which a thick heat sink layer is formed on the back surface.
次にバイアホールＰＨ８構造の電力用ＦＥＴの製造方法
につき第２図によって説明する。Next, a method for manufacturing a power FET having a via hole PH8 structure will be explained with reference to FIG.
ＧａＡｓ基板（１，０１）に能動層（１０２）を選択的
に形成し、さらにソース電極（１０３ｓ）、ドレイン電
極（１０３ｄ）、ゲート電極（１０３ｇ）を配置する（
図（ａ））。An active layer (102) is selectively formed on a GaAs substrate (1,01), and a source electrode (103s), a drain electrode (103d), and a gate electrode (103g) are further arranged (
Figure (a)).
次に、ＧａＡｓ基板の能動層側をシリコンウェーハ等の
支持板（１，０４）にワックス（１０５）で接着させ、
裏面より基板にラッピング、ケミカルエツチングを施し
、３０μｍの厚さまで薄層化する（図（ｂ））。Next, the active layer side of the GaAs substrate is bonded to a support plate (1,04) such as a silicon wafer with wax (105),
The substrate is lapped and chemically etched from the back side to reduce the thickness to 30 μm (Figure (b)).
次に、裏面から選択的にケミカルエツチングを施し、ソ
ース電極（１０３ｇ）が露出するように小孔（１０６）
を設ける（図（Ｃ））。なお、この工程による小孔は両
面マスク合わせ装置によってマスク合わせし、ソース引
出し電極に対向する位置に設けられる。Next, selective chemical etching is performed from the back side to form a small hole (106) so that the source electrode (103g) is exposed.
(Figure (C)). Note that the small holes formed in this process are mask-aligned using a double-sided mask aligning device, and are provided at positions facing the source extraction electrodes.
次に、全面にチタン、金が夫々１０００ Ａ、１０００
０人の厚さに蒸着された裏面金属層（１０７）を被着し
、さらに選択めっきを施しヒートシンク層となる厚さ５
０μｍの金めつき層（１０８）を被着する。このとき、
めっきされない領域は素子分離領域（１０９）となる（
図（ｄ））。なお、上記は通常のマスク合わせ装置によ
って行なわれる。これで裏面金属層（１０７）とソース
電極（１０３ｇ）は小孔（１０６）、すなわちバイアホ
ールを設けることにより接続された。ここでは、バイア
ホールを能動層領域外のソース電極、つまり、ソース引
出し電極に形成した例を示した。Next, titanium and gold are coated on the entire surface with 1000A and 1000A respectively.
A back metal layer (107) is deposited to a thickness of 0.0 mm, and selective plating is applied to form a heat sink layer with a thickness of 5.0 mm.
A gold plating layer (108) of 0 μm is applied. At this time,
The unplated area becomes an element isolation region (109) (
Figure (d)). Note that the above is performed by a normal mask alignment device. The back metal layer (107) and the source electrode (103g) were now connected by providing a small hole (106), that is, a via hole. Here, an example is shown in which the via hole is formed in the source electrode outside the active layer region, that is, in the source extraction electrode.
他に能動層領域内のソース電極にバイアホールを形成す
る方法もあるが、ソース、ドレイン、ゲート等の各電極
が密集しているためにバイアホール加工が非常に困難で
あり、歩留りが著るしく低下する。また、バイアホール
加工を容易にするために能動層領域内のソース電極幅を
広くすることも考えられるが、単位チップ面積当りのゲ
ート幅が狭くなり高密度化が達成できない。Another method is to form a via hole in the source electrode in the active layer region, but since the source, drain, gate, etc. electrodes are crowded together, it is extremely difficult to process the via hole, which significantly reduces the yield. decreases rapidly. It is also conceivable to widen the source electrode width in the active layer region in order to facilitate via hole processing, but this would result in a narrow gate width per unit chip area, making it impossible to achieve high density.
次に、上記素子分離領域直下の金属層およびＧａＡｓ基
板を夫々ケミカルエツチングにより除去し、個々のチッ
プに分離したのち洗浄を施し支持板（１０４）から取外
す。このようにして形成されたチップを図（ｅ）に示す
。なお、この工程では厚い金めつき層（１０８）をマス
クにして同種の蒸着金属層（１０７）にエツチングを施
しているが、これにより金めつき層の層厚は１μｍ程薄
くなるだけで何ら支障を来たさない。Next, the metal layer and the GaAs substrate immediately below the element isolation region are removed by chemical etching, separated into individual chips, and then cleaned and removed from the support plate (104). The chip thus formed is shown in Figure (e). Note that in this step, the thick gold-plated layer (108) is used as a mask to etch the vapor-deposited metal layer (107) of the same type, but this reduces the thickness of the gold-plated layer by only about 1 μm, without any effect. No hindrance.
ところが、上記の方法によると、小孔を設けるのに両面
マスク合わせ装置という特殊な装置を使＝３−
用する必要があり、操作が煩雑であった。However, according to the above method, it was necessary to use a special device called a double-sided mask alignment device to form the small holes, and the operation was complicated.
また１図（ｄ）に見られるように、小孔の形がこれに被
着されたヒートシンク層に現われ、四部のあるヒートシ
ンク層となった。Also, as seen in Figure 1(d), the shape of small holes appeared in the heat sink layer deposited thereon, resulting in a four-part heat sink layer.
さらに、図（ｅ）に示されたチップを金すずはんだ等の
合金はんだを介して外囲器にマウントする場合、チップ
裏面にヒートシンク層凹部に金すずはんだがなじまない
ので、良好なマウントができず放熱が悪くなり、チップ
の信頼性が低下するなどの問題点があった。Furthermore, when mounting the chip shown in Figure (e) on the envelope using alloy solder such as gold-tin solder, the gold-tin solder does not fit into the recessed part of the heat sink layer on the back of the chip, making it impossible to mount it well. There were problems such as poor heat dissipation and reduced chip reliability.
この発明は上記の欠点を除去するもので、素子の信頼性
を低下させることなく平坦にヒートシンク層が形成でき
るバイアホールを有する半導体装置の製造方法を提供す
ることを目的とする。The present invention aims to eliminate the above-mentioned drawbacks and provides a method for manufacturing a semiconductor device having via holes that allows a flat heat sink layer to be formed without reducing the reliability of the device.
この発明にかかる半導体装置の製造方法は、半導体基板
の表面に形成されたバイアホール引出し電極に開孔を設
けこの開孔内に基板表面の一部を露出させる工程と、前
記開孔内に小孔を設ける工程と、前記小孔内からこれに
連結した前記開孔内の基板面を経て前記引出し電極に接
続する接続電極を形成する工程と、前記基板を裏面側か
ら薄層化させ前記小孔内の接続電極を露出させる工程と
、前記基板の裏面にここに露出した前記接続電極に接触
させて第１の金属層を被着する工程と、前記第１の金属
層に積層させて放熱用の第２の金属層を被着する工程を
含むことを特徴とする。A method for manufacturing a semiconductor device according to the present invention includes the steps of: providing an opening in a via hole lead electrode formed on the surface of a semiconductor substrate, exposing a part of the substrate surface within the opening; a step of forming a hole, a step of forming a connection electrode connected to the extraction electrode through the substrate surface in the opening connected to the small hole, and a step of thinning the substrate from the back side to form the small hole. a step of exposing the connection electrode in the hole, a step of depositing a first metal layer on the back surface of the substrate in contact with the connection electrode exposed here, and a step of laminating the first metal layer to dissipate heat. the step of depositing a second metal layer.
〔発明の実施例〕
以下、この発明の１実施例を第１図を参照して説明する
。[Embodiment of the Invention] Hereinafter, one embodiment of the present invention will be described with reference to FIG.
ＧａＡｓ基板（１０１）に能動層（１０２）を選択的に
形成し、さらにドレイン電極（１０３ｄ）、ゲート電極
（１０３ｇ）および、基板が露出する開孔（１）を含む
ソース電極（３ｓ）を配置する（図（ａ））。上記開孔
の寸法を例えば８０μｍ′とする。An active layer (102) is selectively formed on a GaAs substrate (101), and a drain electrode (103d), a gate electrode (103g), and a source electrode (3s) including an opening (1) through which the substrate is exposed are arranged. (Figure (a)). The size of the opening is, for example, 80 μm'.
次に上記開孔（１）の内側にフォトレジスト膜（２）を
張り出させ開口寸法が例えば２０μ♂の開口（２ａ）を
設けてここに基板を露出させ、深さ３０μｍのエツチン
グを施して小孔（４）を設ける（図（ｂ））。ここで小
孔基板表面でサイドエツチングにより寸法が６０μｍｏ
程度になるが、開孔（１）の内側に位置することが重要
である。仮に小孔の基板表面が開孔（１）よりも外側に
位置すると、開孔周辺にあるソース電極（３ｓ）は直下
に何もなく張出した状態で不安定なものとなり、後工程
において小孔に金属層（接続電極）を被着する際この張
出し部で妨げられて小孔の内側面の特に」二部の金属層
が薄く、あるいは不連続となる。そこで、小孔（４）の
基板表面の寸法が開孔（１）の寸法よりも内側になるよ
うに、開孔の寸法、小孔（７１）の基板表面の寸法、お
よびエツチング深さ等を充分考慮して施す。また、エツ
チング深さは後の基板薄化工程での基板の厚さがきめら
れるものであるから重要である。Next, the photoresist film (2) is extended inside the opening (1), an opening (2a) with an opening size of, for example, 20 μm is provided, the substrate is exposed here, and etching is performed to a depth of 30 μm. A small hole (4) is provided (Figure (b)). Here, the size is 60μmo due to side etching on the surface of the small hole substrate.
It is important to be located inside the aperture (1), although this may be a minor issue. If the substrate surface of the small hole is located outside the hole (1), the source electrode (3s) around the hole will be unstable with nothing directly below it, and the small hole will be removed in the subsequent process. When a metal layer (connection electrode) is applied to the pore, this protruding portion obstructs the application of the metal layer, particularly on the inner surface of the small hole, resulting in a thin or discontinuous metal layer. Therefore, the dimensions of the opening, the dimensions of the substrate surface of the small hole (71), the etching depth, etc. are adjusted so that the dimensions of the substrate surface of the small hole (4) are inside the dimensions of the opening (1). Apply with due consideration. Further, the etching depth is important because it determines the thickness of the substrate in the subsequent substrate thinning process.
次に、フォトＩノジス１へ膜を除去したのち、開孔（１
）よりも外側にフォトレジス１へ膜（１２）を設けて、
例えば寸法が１０１００７ｚとなるように小孔（／ｌ）
および開孔周辺部のソース電極（３ｓ）を露出させ、例
えばチタン、金を夫々１０００人、１００００への厚さ
となる金属層を被着し、リフトオフ法によりフォトレジ
スト膜と、この膜上の金属層を同時に除去して接続電極
（５）を形成する（図（Ｃ））。これによりソース電極
（３ｓ）と小孔を覆う上記接続電極（５）が接続して形
成される。Next, after removing the film from the photo I nozzle 1, the opening (1
), a film (12) is provided on the photoresist 1 on the outside,
For example, make a small hole (/l) so that the dimension is 101007z.
Then, expose the source electrode (3s) around the opening, deposit a metal layer of titanium and gold to a thickness of 1000 and 10000, respectively, and remove the photoresist film and the metal on this film by lift-off method. The layers are simultaneously removed to form a connection electrode (5) (Figure (C)). As a result, the source electrode (3s) and the connection electrode (5) covering the small hole are connected and formed.
次に、ＧａＡｓ基板の能動層側を例えばシリコン基板等
の支持板（１０４）にワックス（１０５）で接着させた
のち、裏面から基板にラッピング、ケミカルエツチング
により接続電極（５）が露出するまで薄層化する（図（
ｄ））。これにより、ケミカルエツチング工程で接続電
極と基板が露出し、電池効果とみられる微小凹み（１０
）が接続電極と基板との境界面に生ずる。Next, the active layer side of the GaAs substrate is bonded to a support plate (104) such as a silicon substrate with wax (105), and then the substrate is lapped from the back side and thinned until the connection electrode (5) is exposed by chemical etching. Stratify (Figure (
d)). As a result, the connection electrode and substrate are exposed during the chemical etching process, resulting in minute dents (10
) occurs at the interface between the connection electrode and the substrate.
次に、全面にチタン、金が夫々をｌ０００人、５０００
人の厚さとなる裏面金属層（第１の金属層）（６）を蒸
着により被着し、前工程での凹みを目印として選択めっ
きを施し、ヒートシンク層となる厚さ５０μｍの金めつ
き層（第２の金属層）（７）を設ける。Next, the entire surface is made of titanium and gold, respectively, 1000 and 5000.
A back metal layer (first metal layer) (6) with a human thickness is deposited by vapor deposition, and selective plating is applied using the dents from the previous process as a mark to form a 50 μm thick gold plated layer that will become a heat sink layer. (Second metal layer) (7) is provided.
このとき、めっきされない領域は素子分離領域（８）と
なる（図（ｅ））。なお、実施例では上記凹み（１０）
−７＝
によってマスク合わせが行なわれるようになっているが
、通常１個の素子チップ内にバイアホール領域は数個形
成されており、ソース、ドレイン、ゲー１−の各電極形
成に用いられる微細マスク合わせ技術は必要でなく、従
って比較的簡単にマスク合わせできる。At this time, the area that is not plated becomes an element isolation area (8) (FIG. (e)). In addition, in the example, the above-mentioned recess (10)
Mask alignment is performed by -7=, but normally several via hole regions are formed in one element chip, and the microscopic holes used for forming source, drain, and gate electrodes are used. No mask matching techniques are required and therefore mask matching is relatively easy.
次に、素子分離領域直下の第の金属層（６）およびＧａ
Ａｓ基板（↑０１）を夫々ケミカルエツチングにより除
去して個々のチップに分離し、ついで洗浄を施して支持
板（１０４）から分離することによってチップ（」）が
得られる（図（ｆ））。Next, the second metal layer (6) directly under the element isolation region and the Ga
Chips ('') are obtained by removing the As substrates (↑01) by chemical etching and separating them into individual chips, followed by washing and separating them from the support plate (104) (FIG. (f)).
斜上の如くして得られたチップは図（ｄ）に示す工程で
、ソース電極が露出するので、従来の工程において必須
であった両面マスク合わせ（第２図（Ｃ））にて示され
る工程）を必要としない。In the process shown in Figure (d), the chip obtained in the diagonal manner exposes the source electrode, so the double-sided mask alignment (Figure 2 (C)), which is essential in the conventional process, is performed. process) is not required.
また、図（ｅ）に示すように、裏面が平坦でこれにヒー
トシンク層を形成しているので、得られるヒートシンク
層は平坦に得られる。In addition, as shown in FIG. 3(e), since the back surface is flat and the heat sink layer is formed on it, the resulting heat sink layer is flat.
さらに、図（ｆ）に示すように、チップはビー１−シ２
９層が平坦であるため、外囲器へのマウントも平坦にで
きると同時に放熱が良好である。Furthermore, as shown in Figure (f), the chips are
Since the nine layers are flat, it can be mounted flat on the envelope and at the same time has good heat dissipation.
なお、上記実施例では小孔の深さを３０μｍにしたが、
これに限定されるものでなく、説明した条件に適するよ
うに設定してよい。また、実施例における第１の金属層
にチタン、金の２重層を例示したがこれに限定されるも
のでない。In addition, in the above example, the depth of the small hole was 30 μm, but
The setting is not limited to this, and may be set to suit the conditions described. Further, although a double layer of titanium and gold is illustrated as the first metal layer in the embodiment, the present invention is not limited to this.
以上、この発明では電力用ＦＥＴについて説明したが、
１つのチップに受動回路およびＦＥＴを組合わせてでき
る集積回路素子にも適用できる。In the above, the power FET has been explained in this invention.
It can also be applied to integrated circuit elements formed by combining passive circuits and FETs on one chip.
以上述べたようにこの発明によれば、基板に薄層化を施
したのちのパターン形成工程が少くて達成できること、
両面マスク合わせが不要なのでこのための特殊な装置と
工程を必要としないこと、および、平坦なヒートシンク
層が形成できチップマウントに有利かつ放熱が良好であ
ること、などの顕著な利点がある。そして、歩留り良く
バイア ・ホールとＰＨ８を有する半導体装置を製造
できる。As described above, according to the present invention, the pattern formation process after thinning the substrate can be achieved with fewer steps.
There are significant advantages such as no need for double-sided mask alignment, so special equipment and processes are not required for this purpose, and a flat heat sink layer can be formed, which is advantageous for chip mounting and has good heat dissipation. Then, a semiconductor device having via holes and PH8 can be manufactured with high yield.
第１図（ａ）〜（ｆ）はこの発明の１実施例のパイアホ
ールＰＨＦ構造の電力用ＦＥＴの製造方法を工程順に示
すいずれも断面図、第２図（ａ）〜（ｅ）は従来の電力
用ＦＥＴの製造方法を工程順に示すいずれも断面図であ
る。FIGS. 1(a) to 1(f) are cross-sectional views showing the manufacturing method of a power FET with a piere-hole PHF structure according to an embodiment of the present invention in the order of steps, and FIGS. 2(a) to (e) are sectional views of the conventional method. 2A and 2B are cross-sectional views illustrating the manufacturing method of the power FET in order of steps.
Claims (1)
極に開孔を設けこの開孔内に基板表面の一部を露出させ
る工程と、前記開孔内に小孔を設ける工程と、前記小孔
内からこれに連続した前記開孔内の基板面を経て前記引
出し電極に接続する接続電極を形成する工程と、前記基
板を裏面側から薄層化させ前記小孔内の接続電極を露出
させる工程と、前記基板の裏面にこれに露出した前記接
続電極に接触させて第１の金属層を被着する工程と、前
記第１の金属層に積層させて放熱用の第２の金属層を被
着する工程を含むことを特徴とする半導体装置の製造方
法。A step of providing an opening in a via hole extraction electrode formed on the surface of a semiconductor substrate and exposing a part of the substrate surface within the opening, a step of providing a small hole within the opening, and a step of forming a small hole from within the small hole. a step of forming a connection electrode connected to the extraction electrode through the substrate surface in the continuous opening, and a step of thinning the substrate from the back side to expose the connection electrode in the small hole; A step of depositing a first metal layer on the back surface of the substrate in contact with the connection electrode exposed thereon, and depositing a second metal layer for heat dissipation by laminating on the first metal layer. 1. A method of manufacturing a semiconductor device, the method comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20059084A JPS6179261A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20059084A JPS6179261A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6179261A true JPS6179261A (en) | 1986-04-22 |
Family
ID=16426874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20059084A Pending JPS6179261A (en) | 1984-09-27 | 1984-09-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179261A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148505A (en) * | 1994-11-21 | 1996-06-07 | Nec Corp | High output millimetric wave mmic |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
| CN109771982A (en) * | 2019-02-25 | 2019-05-21 | 江苏沃德凯环保科技有限公司 | A kind of method and device preventing distillation fouling |
-
1984
- 1984-09-27 JP JP20059084A patent/JPS6179261A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08148505A (en) * | 1994-11-21 | 1996-06-07 | Nec Corp | High output millimetric wave mmic |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
| CN109771982A (en) * | 2019-02-25 | 2019-05-21 | 江苏沃德凯环保科技有限公司 | A kind of method and device preventing distillation fouling |
| CN109771982B (en) * | 2019-02-25 | 2023-09-22 | 江苏沃德凯环保科技有限公司 | Method and device for preventing distillation scaling |
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