JPH05152340A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce heat resistance of an FET, such as a power FET, without reducing the mechanical strength thereof. CONSTITUTION:The thickness, which is located in an active region 6 of a field- effect transistor, of a semiconductor substrate 1 is made thinner than that in other regions of the transistor and a metallic electrode 7 is formed on the rear of the substrate 1 and is connected to a source electrode 2 through a via hole 8. A heat resistance of the transistor can be reduced by making thinner its thickness, which is located in the region 6, of the substrate 1, while a reduction in the mechanical strength of the thinned region is prevented by forming the electrode 7 on the rear of the substrate 1.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to field effect transistors, and more particularly to power field effect transistors.

[0002]

2. Description of the Related Art In recent years, power field effect transistors in the microwave band (hereinafter abbreviated as power FETs) have been put to practical use with compound semiconductors such as GaAs having a high electron velocity. In this type of power FET, as shown in FIG. 3, a source electrode 2, a drain electrode 3 and a gate electrode 4 are formed on the surface of an active layer 5 formed on the surface of a semi-insulating semiconductor substrate 1. There is. Further, for the purpose of reducing the thermal resistance between the source and the drain, a gold-plated electrode 7 is formed on the back surface of the semiconductor substrate 1, and the source electrode 2 is connected to the gold-plated electrode 7 via a via hole 8.

[0003]

[Problems to be Solved by the Invention] Such a power FE
At T, the amount of heat generated in the active layer region 6 increases as the current flowing between the source and drain increases, and the thermal resistance increases. Therefore, in the past, attempts have been made to reduce the thermal resistance by reducing the thickness of the semiconductor substrate 1 as much as possible.
There is a problem that the thinness of the semiconductor substrate lowers the mechanical strength and the reliability of the power FET. An object of the present invention is to provide an FET having reduced thermal resistance without lowering mechanical strength.

[0004]

The FET of the present invention is FE
The thickness of the semiconductor substrate in the active layer region of T is made thinner than other regions, and a metal electrode is formed on the back surface of the semiconductor substrate. For example, the active layer region is selectively etched from the back surface side of the substrate to reduce the substrate thickness.

[0005]

In this FET, thermal resistance can be reduced by thinning the semiconductor substrate in the active layer region, and on the other hand, by forming a metal electrode on the back surface, the mechanical strength of the thinned region can be prevented from lowering.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the FET of the present invention.
An active layer 5 is formed on a semi-insulating semiconductor substrate 1, and a source electrode 2, a drain electrode 3 and a gate electrode 4 are formed on the surface of the active layer 5. Also, the back surface of the semiconductor substrate 1 is
Region 1a corresponding to the active layer region 6 between the source and drain
The substrate thickness of is formed thinner than other regions. Then, a gold-plated electrode 7 is formed on the back surface of the semiconductor substrate 1, and the gold-plated electrode 7 is electrically connected to the source electrode 2 through a via hole 8 provided in the semiconductor substrate 1.

As a method of forming the substrate thickness of the semiconductor substrate 1 thin, selective etching using a photolithography technique is performed from the back surface side of the semiconductor substrate 1 to form a recess in the region 1a of the semiconductor substrate 1 from the back surface side. It becomes possible by forming. In this embodiment, the thickness of the region 1a is set to 10 μm and the thickness of the other regions is set to 50 μm by using the dry etching method.

In this FET, the semiconductor substrate 1 in the active layer region 6 is thinner than the other regions, so that the thermal resistance is reduced. In this embodiment, the thermal resistance can be reduced by 30% as compared with the conventional structure shown in FIG. 3 by forming the above-mentioned thickness dimension. On the other hand, even if the semiconductor substrate 1 is formed thin, the gold plating electrode 7 formed on the back surface of the semiconductor substrate 1 increases the thickness of the region 1a to the same extent as the other regions, thus lowering the overall mechanical strength. The reliability of the FET is not impaired.

FIG. 2 shows another embodiment of the present invention, in which parts equivalent to those in FIG. 1 are designated by the same reference numerals. In this embodiment, when the region 1a of the semiconductor substrate 1 is selectively etched from the back surface side, a wet etching method is used to reduce the step difference at the boundary with other regions. According to this configuration, it is possible to further reduce the thermal resistance by 10% compared to the configuration of FIG.

[0010]

As described above, according to the present invention, the thickness of the semiconductor substrate in the active layer region of the FET is smaller than that of the other regions, so that the thermal resistance of the FET can be reduced. or,
By thinning only the active layer region and forming a metal electrode on the back surface, a reduction in mechanical strength of a portion thinned by the metal electrode is prevented and a reduction in reliability of the FET is prevented.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an embodiment of a FET of the present invention.

FIG. 2 is a sectional view of another embodiment of the FET of the present invention.

FIG. 3 is a cross-sectional view of a conventional FET.

[Explanation of symbols]

 1 semiconductor substrate 2 source electrode 3 drain electrode 4 gate electrode 5 active layer 6 active layer region 7 gold-plated electrode 8 via hole

Claims (2)

[Claims] 1. The thickness of a semiconductor substrate in an active layer region of a field effect transistor is made thinner than other regions, and a metal electrode is formed on the back surface of the semiconductor substrate, and the metal electrode is formed through a via hole. A field effect transistor characterized in that it is connected to a source electrode formed on the surface of a substrate. 2. The field effect transistor according to claim 1, wherein the active layer region is selectively etched from the back surface side of the substrate to reduce the thickness of the substrate.