JPH02102544A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02102544A JPH02102544A JP25777188A JP25777188A JPH02102544A JP H02102544 A JPH02102544 A JP H02102544A JP 25777188 A JP25777188 A JP 25777188A JP 25777188 A JP25777188 A JP 25777188A JP H02102544 A JPH02102544 A JP H02102544A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- layer
- thin film
- metal
- metal thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 19
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 8
- 238000000206 photolithography Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000004888 barrier function Effects 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- KWLSQQRRSAWBOQ-UHFFFAOYSA-N dipotassioarsanylpotassium Chemical compound [K][As]([K])[K] KWLSQQRRSAWBOQ-UHFFFAOYSA-N 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は電界効果トランジスタに関するものである。[Detailed description of the invention] [Industrial application field] This invention relates to field effect transistors.
電界効果トランジスタ、ここではＧａＡｓ （ヒ化カリ
ウム）を用いた電界効果型トランジスタ（以下、ＧａＡ
ｓＦＥＴと称す。）を例に説明する。A field effect transistor, here a field effect transistor using GaAs (potassium arsenide) (hereinafter referred to as a GaAs
It is called sFET. ) will be explained as an example.
第２図は従来のＧａＡｓＦＥＴの断面図であり、次のよ
うな構成になっている。半絶縁性基板（５）と、その−
主面上に 形活性層（４）が形成されている。FIG. 2 is a cross-sectional view of a conventional GaAsFET, which has the following configuration. Semi-insulating substrate (5) and its -
A shaped active layer (4) is formed on the main surface.
活性層（４）の上にソース電極（２）及びドレイン電極
（３）が形成されており、画電極＋２１ ＋３１の間に
ゲート電極（１）が位置している。図中、符号Ｉｌｌで
示した寸法はゲート長と称し、この寸法がＧａＡｓＦＥ
Ｔの性能に太き（影響する。A source electrode (2) and a drain electrode (3) are formed on the active layer (4), and a gate electrode (1) is located between the picture electrodes +21 and +31. In the figure, the dimension indicated by the symbol Ill is called the gate length, and this dimension is
It affects the performance of T.
ＧａＡｓＦＥＴはマイクロ波領域において、小信号およ
び電力用増巾器あるいは発振器などに利用されて右り、
このＧａＡｓ ＦＥＴの性能は主としてそのゲート長に
より左右され、ゲート長を短くすることがその要点の１
つとなっている。そして、このゲート電極は一般に光を
用いた密着露光−すなわち、フォトリングラフ法、電子
ビーム露光法、Ｘ線リングラフィ法などにより形成され
るが、量産性を考慮するとき、通常はフォトリングラフ
ィ法を採用している。GaAsFETs are used in small signal and power amplifiers and oscillators in the microwave region.
The performance of this GaAs FET is mainly influenced by its gate length, and one of the key points is to shorten the gate length.
It is one. This gate electrode is generally formed by contact exposure using light, that is, photophosphorography, electron beam exposure, X-ray phosphorography, etc. However, when mass production is considered, photophosphorography is usually law is adopted.
そして、このフォトリングラフィ法ではゲート長の形成
は０．５μｍ程度が限界とされている。In this photolithography method, the gate length is limited to approximately 0.5 μm.
この発明は従来のフォトリングラフィ法を用いてゲート
長を０．５μｍ以下を実現するためになされたもので、
従来の方法ではゲート長を細くするとゲート電極の断面
が小さくなり電気抵抗が大きくなってＧａＡｓＦＥＴの
性能を劣化させるが−この発明はゲート電気抵抗を大き
くすることなくゲート長を細くすることを目的とするも
のである。This invention was made to realize a gate length of 0.5 μm or less using the conventional photolithography method.
In conventional methods, when the gate length is made thinner, the cross section of the gate electrode becomes smaller and the electrical resistance increases, degrading the performance of the GaAsFET, but this invention aims to make the gate length thinner without increasing the gate electrical resistance. It is something to do.
この発明はゲート金属層を２種類以上の異なる金属で構
成し、通常のフォトリングラフィ法でゲート電極を形成
した後、 ＧａＡｓ面に接した金属層のみをエツチング
等の方法で細くし、丁字形のゲート電極を実現する。In this invention, the gate metal layer is composed of two or more different metals, and after a gate electrode is formed by a normal photolithography method, only the metal layer in contact with the GaAs surface is thinned by a method such as etching, and a T-shaped structure is formed. Realizes the gate electrode of
この発明によるゲート電極はＧａＡｓ面と接する金属層
は細くなり一細いショトキ−接合面が実現でき実効的に
細いゲートが実現され、又、この金属層の上方に位置す
る金属は太いため電気抵抗は従来の値と大差がなく、低
抵抗ゲート電極が実現される。In the gate electrode according to the present invention, the metal layer in contact with the GaAs surface is thin and a thin Schottky junction surface is realized, effectively realizing a thin gate.Also, since the metal layer located above this metal layer is thick, the electrical resistance is low. There is no big difference from the conventional value, and a low resistance gate electrode can be realized.
第１図はこの発明の一実施例を示すＧａＡｓ ＦＥＴの
断面図で、図中符号（６Ｌ （７）、 ＋８１はこの発
明の要部をなすゲート電極をなす金属薄膜層である。な
お、図中符号（２）〜（５）は前記従来のものと同一に
つき説明は省略する。通常の蒸着又はスパッタ法で金属
薄膜層（６）、（７）、（８）を形成し、その後フォト
リングラフィ法でゲート電極を作成する。金属薄膜層（
６）はＧａＡｓと接し、ショトキ−接合を形成する金属
である。例えば金属薄膜Ｒ＋６１はＡＩ、金属薄膜層（
８）はＡｕ、金属薄膜層（７）はＡＩとＡｕの反応を防
止するバリアメタル（ＮｉｏｒＭｏ ）である。ＡＩの
みをエツチングする溶液を用い金属薄膜層（６）の（９
）の部分をエツチングする。上層の金属薄膜層（７）、
（８）はエツチングされないため丁字形ゲート電極が実
現される。また、この時金属薄膜層（６）の厚みを金属
薄膜層（８）又は（７）層＋（８）層より十分に薄くし
て置けば、ゲート電極の断面層は従来の場合と大差がな
くゲート抵抗も従来と変らない。FIG. 1 is a cross-sectional view of a GaAs FET showing an embodiment of the present invention, and the symbols (6L (7) and +81 in the figure are metal thin film layers forming the gate electrode, which is the essential part of the present invention. Reference symbols (2) to (5) are the same as those in the conventional method, so explanations are omitted.Metal thin film layers (6), (7), and (8) are formed by ordinary vapor deposition or sputtering, and then photoresist is applied. The gate electrode is created using a graphic method.The metal thin film layer (
6) is a metal that comes into contact with GaAs and forms a Schottky junction. For example, metal thin film R+61 is AI, metal thin film layer (
8) is Au, and the metal thin film layer (7) is a barrier metal (NiorMo) that prevents the reaction between AI and Au. (9) of metal thin film layer (6) using a solution that etches only AI.
) part is etched. upper metal thin film layer (7),
Since (8) is not etched, a T-shaped gate electrode is realized. Also, if the thickness of the metal thin film layer (6) is made sufficiently thinner than the metal thin film layer (8) or (7) layer + (8) layer at this time, the cross-sectional layer of the gate electrode will be much different from the conventional case. The gate resistance is also the same as before.
このようにして、低ゲート抵抗でかつショトキ−接合の
小さい一つまり実効ゲート長の粗いゲート電極が実現さ
れる。In this way, a gate electrode with low gate resistance and a small Schottky junction, that is, a rough effective gate length, is realized.
なお、上記実施例では金属薄膜層を３層とした場合につ
いて説明したが、２層でも又３層以上でも可能である。In the above embodiment, the case where three metal thin film layers were used was explained, but it is also possible to use two or three or more layers.
又、ＧａＡｓＦＥＴの場合について説明したが、他の半
導体材料素子（例えばＩｎＰ ）でも又半導体集積回路
の場合でも適用が可能である。Further, although the case of GaAsFET has been described, the present invention can be applied to other semiconductor material elements (for example, InP) or to semiconductor integrated circuits.
以上のようにこの発明によれば、低ゲート抵抗でかつ短
ゲート電極が容易に形成され、高周波特性の優れた半導
体装置が安価に実現できる効果がある。As described above, according to the present invention, a short gate electrode with low gate resistance can be easily formed, and a semiconductor device with excellent high frequency characteristics can be realized at low cost.
第１図はこの発明のＧａＡｓ ＦＥＴの断面図、第２図
は従来のＧａＡｓＦＥＴの断面図を示す。
図中、（２）はソース電極、（３）はドレイン電極、（
４）は活性層−（５）はＧａＡｓ基板、（６）はＧａＡ
ｓとショトキ−接合を形成する金属薄膜層（例えばＡＩ
）、（７）−（８）は金属薄膜層（６）の上に形成され
た金属薄膜層（６）と異なる金属薄膜層、（９）はエツ
チングにより除去された部分、Ｑｌはゲート長である。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 shows a cross-sectional view of a GaAs FET of the present invention, and FIG. 2 shows a cross-sectional view of a conventional GaAs FET. In the figure, (2) is the source electrode, (3) is the drain electrode, (
4) is an active layer, (5) is a GaAs substrate, and (6) is a GaA
A thin metal film layer (e.g. AI) that forms a Schottky junction with
), (7)-(8) are metal thin film layers different from the metal thin film layer (6) formed on the metal thin film layer (6), (9) is the part removed by etching, and Ql is the gate length. be. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
イン電極を有する電界効果トランジスタ、又は半導体集
積回路において、ゲート電極層を２種類以上の積層金属
薄膜層により形成し、ＧａＡｓ活性層表面に接するゲー
ト金属層を選択的にエッチングし、このゲート金属薄膜
層をゲート金属の上方に積層された金属薄膜層より細く
したことを特徴とする半導体装置。In a field effect transistor or a semiconductor integrated circuit having a gate electrode, a source electrode, and a drain electrode on the surface of the GaAs active layer, the gate electrode layer is formed of two or more types of laminated metal thin film layers, and the gate metal layer is in contact with the surface of the GaAs active layer. A semiconductor device characterized in that the gate metal thin film layer is made thinner than the metal thin film layer laminated above the gate metal by selectively etching the gate metal thin film layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25777188A JPH02102544A (en) | 1988-10-12 | 1988-10-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25777188A JPH02102544A (en) | 1988-10-12 | 1988-10-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02102544A true JPH02102544A (en) | 1990-04-16 |
Family
ID=17310873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25777188A Pending JPH02102544A (en) | 1988-10-12 | 1988-10-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02102544A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459087A (en) * | 1992-08-03 | 1995-10-17 | Nec Corporation | Method of fabricating a multi-layer gate electrode with annealing step |
| JP2015099865A (en) * | 2013-11-20 | 2015-05-28 | 三菱電機株式会社 | Hetero-junction field effect transistor and manufacturing method of the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61216483A (en) * | 1985-03-22 | 1986-09-26 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS61216484A (en) * | 1985-03-22 | 1986-09-26 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS63193570A (en) * | 1987-02-06 | 1988-08-10 | Sharp Corp | Manufacture of semiconductor device |
-
1988
- 1988-10-12 JP JP25777188A patent/JPH02102544A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61216483A (en) * | 1985-03-22 | 1986-09-26 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS61216484A (en) * | 1985-03-22 | 1986-09-26 | Mitsubishi Electric Corp | Manufacture of field effect transistor |
| JPS63193570A (en) * | 1987-02-06 | 1988-08-10 | Sharp Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5459087A (en) * | 1992-08-03 | 1995-10-17 | Nec Corporation | Method of fabricating a multi-layer gate electrode with annealing step |
| JP2015099865A (en) * | 2013-11-20 | 2015-05-28 | 三菱電機株式会社 | Hetero-junction field effect transistor and manufacturing method of the same |
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