JPH0362017B2 - - Google Patents
Info
- Publication number
- JPH0362017B2 JPH0362017B2 JP12884483A JP12884483A JPH0362017B2 JP H0362017 B2 JPH0362017 B2 JP H0362017B2 JP 12884483 A JP12884483 A JP 12884483A JP 12884483 A JP12884483 A JP 12884483A JP H0362017 B2 JPH0362017 B2 JP H0362017B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- gate
- pattern
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000035945 sensitivity Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- LZYIDMKXGSDQMT-UHFFFAOYSA-N arsenic dioxide Chemical compound [O][As]=O LZYIDMKXGSDQMT-UHFFFAOYSA-N 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は小形化に伴うゲート抵抗の増加を抑制
した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that suppresses an increase in gate resistance due to miniaturization.
(b) 技術の背景
半導体IC，LSIなでの半導体装置は電算機駆動
の主要要素であり、より高送に、より大量の情報
を処理するために高速動作と高集積化が要求され
ている。(b) Technical background Semiconductor devices such as semiconductor ICs and LSIs are the main elements for driving computers, and high-speed operation and high integration are required to process higher transmission rates and larger amounts of information. .
こゝで高速化のためには各素子間を繁ぐ配線間
距離を短くし信号の遅れを少くすることが必要で
あり、また高集積化のためには一つのチツプ上に
できるだけ多くの素子形成を行う必要があり必然
的に素子が小形化し高密度化している。然し素子
が小形化すると素子内における電極抵抗が増加す
ると云う問題がある。 In order to increase speed, it is necessary to shorten the distance between the wiring between each element and reduce signal delay, and to achieve high integration, as many elements as possible can be placed on one chip. As a result, devices are inevitably becoming smaller and more dense. However, as the device becomes smaller, there is a problem in that the electrode resistance within the device increases.
本発明は電極パターン幅が減少すると特性が改
良される半導体装置について電極幅の減少による
抵抗増加を回避した電極形成方法に関するもので
ある。 The present invention relates to a method for forming an electrode in a semiconductor device whose characteristics are improved as the width of the electrode pattern is reduced, which avoids an increase in resistance due to a reduction in the width of the electrode.
(c) 従来技術と問題点
電極パターン幅が狭い程特性が改良される例と
して電界効果トランジスタ（FET）のゲート電
極が知られている。すなわちソース・ドレイン間
の電圧（Vsd）とソース・ドレイン間の電流
（Isd）との静特性をゲート電圧（Vg）をパラメ
ータとしてとる場合、そのVg依存性はゲート電
極幅が狭くなる程顕著となる。そこで素子の小形
化と同時にFETの場合ゲート電極幅（以後ゲー
ト長Lgと云う）の減少が推進されている。然し
ゲート長Lgが減少するに従つてゲート抵抗Rgが
増加し高速化を妨げている。(c) Prior art and problems Gate electrodes of field effect transistors (FETs) are known as an example in which characteristics improve as the electrode pattern width becomes narrower. In other words, when the static characteristics of the source-drain voltage (Vsd) and source-drain current (Isd) are taken as the gate voltage (Vg) as a parameter, the Vg dependence becomes more pronounced as the gate electrode width becomes narrower. Become. Therefore, along with the miniaturization of devices, the width of the gate electrode (hereinafter referred to as gate length Lg) of FETs is being reduced. However, as the gate length Lg decreases, the gate resistance Rg increases, which hinders speeding up.
以下高電子移動度トランジスタの形成の場合を
例として問題点を説明する。 The problems will be explained below using the case of forming a high electron mobility transistor as an example.
第１図はこのトランジスタを含むFETの構成
を示すもので、ゲート１を中心としてソース２と
ドレイン３の各電極がガリウム砒素（GaAs）か
らなる基板上に形成されている。 FIG. 1 shows the structure of an FET including this transistor, with a gate 1 at the center and source 2 and drain 3 electrodes formed on a substrate made of gallium arsenide (GaAs).
第２図は断面構造で半絶縁性のGaAs基板（S.
IGaAs）４の上にノンドーブのGaAs層５がMBE
法（分子線エピタキシー）で形成され、この上に
順次MBE法によりノンドープAl0.3Ga0.7As層６、
Al0.3Ga0.7As層７、Ｎ型グレーデイツトAlxGa1-x
As層８、Ｎ型GaAs層９が形成され、ソース２お
よびドレイン３は金−ゲルマニウム（Au−Ge）
とGaAsとの合金でオーミツクコンタクトが形成
されており、またゲート１はドライエツチング例
えばリアクテイブイオンエツチングでＮ型グレー
デイツトAlxGa1-xAs層８に到るまでリセス１０
を形成し、これにチタン−白金−金（Ti−Pt−
Au）の多層金属からなるゲート１がスパツタリ
ング或は蒸着法で形成されている。こゝでこのト
ランジスタの特徴は、ノンドーブGaAs層５とノ
ンドーブAl0.3Ga0.7As層６とのヘテロ接合面に発
生する高移動度電子層（２次元電子ガス層）を電
界により抑制するものである。 Figure 2 shows the cross-sectional structure of a semi-insulating GaAs substrate (S.
A non-doped GaAs layer 5 is formed on MBE
(molecular beam epitaxy), and a non-doped Al 0.3 Ga 0.7 As layer 6,
Al 0.3 Ga 0.7 As layer 7, N type gray date AlxGa 1-x
An As layer 8 and an N-type GaAs layer 9 are formed, and the source 2 and drain 3 are made of gold-germanium (Au-Ge).
An ohmic contact is formed with an alloy of GaAs and GaAs, and the gate 1 is etched by dry etching, such as reactive ion etching, to form a recess 10 down to the N-type graded AlxGa 1-x As layer 8.
and titanium-platinum-gold (Ti-Pt-
A gate 1 made of a multilayer metal (Au) is formed by sputtering or vapor deposition. The feature of this transistor is that the high mobility electron layer (two-dimensional electron gas layer) generated at the heterojunction interface between the non-doped GaAs layer 5 and the non-doped Al 0.3 Ga 0.7 As layer 6 is suppressed by an electric field. .
かかる構造においてゲート１のゲート長く短く
すると必然的にゲート抵抗Rgが増加するがこれ
は当然な現像であり、この増加は高速化の妨げと
なつている。 In such a structure, if the gate 1 is lengthened or shortened, the gate resistance Rg inevitably increases, but this is a natural development, and this increase is an obstacle to speeding up.
(d) 発明の目的
本発明はFETのゲート長を縮少する際に生ず
るゲート抵抗Rgの増大を防ぐと共に容量増加を
伴わないゲート電極の形成方法を提供することを
目的とする。(d) Object of the Invention The object of the present invention is to provide a method for forming a gate electrode that prevents an increase in gate resistance Rg that occurs when reducing the gate length of an FET and does not involve an increase in capacitance.
(e) 発明の構成
本発明の目的は半導体基板の最上層に絶縁層を
設けこの絶縁層をゲート電極形成領域を除いて除
去し、ソースおよびドレイン電極パターンの形成
を行つた後、この基板上に上層が通常感度で下層
が高感度の２層からなるレジスト層を形成し、ゲ
ート電極パターンの露光、現像と開口部へのドラ
イエツチングを行い、上層のレジストパターンに
より定まるリセスを形成し、次に上層のレジスト
パターンを除去し、下層のレジストパターンを用
いてゲート電極形成用金属の蒸着を行い、リフト
オフ法によりゲート電極パターンを形成する製法
をとることにより実現することができる。(e) Structure of the Invention The object of the present invention is to provide an insulating layer on the uppermost layer of a semiconductor substrate, remove this insulating layer except for the gate electrode formation region, and then form a source and drain electrode pattern on the substrate. Next, a resist layer consisting of two layers is formed, the upper layer being normal sensitivity and the lower layer being high sensitivity, and the gate electrode pattern is exposed, developed and the opening is dry etched to form a recess determined by the upper layer resist pattern. This can be achieved by removing the upper resist pattern, vapor-depositing a gate electrode forming metal using the lower resist pattern, and forming the gate electrode pattern using a lift-off method.
(f) 発明の実施例
第３図は本発明を実施した高電子移動度トラン
ジスタの断面構造で、第２図の従来構造と異なる
ところはリセス１０が幅狭く形成されていること
Ｎ型GaAs層９の上にノンドープGaAs層１１が
新たに設けられ、この上にゲート１２が設けられ
ている点が異つている。(f) Embodiments of the Invention Figure 3 shows the cross-sectional structure of a high electron mobility transistor embodying the present invention.The difference from the conventional structure shown in Figure 2 is that the recess 10 is formed narrower. The difference is that a non-doped GaAs layer 11 is newly provided on top of the gate 9, and a gate 12 is provided on top of the non-doped GaAs layer 11.
本発明はかゝる構造の形成方法に関するもので
あり、第５図Ａ〜Ｅはこの手順である。 The present invention relates to a method for forming such a structure, and FIGS. 5A to 5E illustrate this procedure.
すなわち従来と同様にS.IGaAs基板４の上に順
次MBE法によりノンドープGaAs層５、ノンド
ーブAl0.3Ga0.7As層６、Al0.3Ga0.7As層７、Ｎ型
グレーデイツトAlxGa1-xAs層８、Ｎ型GaAs層
９を形成し更にその上にMBE法により本発明に
係るノンドープGaAs層１１を形成する。 That is, as in the conventional case, a non-doped GaAs layer 5, a non-doped Al 0.3 Ga 0.7 As layer 6, an Al 0.3 Ga 0.7 As layer 7, an N-type graded AlxGa 1-x As layer 8, An N-type GaAs layer 9 is formed, and a non-doped GaAs layer 11 according to the present invention is further formed thereon by the MBE method.
このノンドープGaAs層１１は後述するゲート
電極による静電容量の増大を抑制するための絶縁
層で本実施例の場合は厚さ約5000〔Å〕である
（Ａ図）。 This non-doped GaAs layer 11 is an insulating layer for suppressing an increase in capacitance due to a gate electrode, which will be described later, and has a thickness of about 5000 Å in this embodiment (see Figure A).
次にゲート形成領域を除いてノンドープGaAs
層１１をエツチングしこゝにソース１３およびド
レイン１４電極を形成する（Ｂ図）。 Next, non-doped GaAs was used except for the gate formation region.
Layer 11 is etched to form source 13 and drain 14 electrodes (Figure B).
次にこの上に高感度のホトレジスト層１５と通
常感度のホトレジスト層１６を均一に被覆する。 Next, a high-sensitivity photoresist layer 15 and a normal-sensitivity photoresist layer 16 are uniformly coated thereon.
ここで例えば高感度レジストとしてはCMR
（Crosslinked Methyl meta−acrylate Resist）
がまた通常感度レジストとしては市販のPMMA
を挙げることができ、これを本実施例の場合約
0.5〔μm〕づつスピンコートして厚さ約１〔μm〕
の塗膜を作り、これにゲートパターンを位置合わ
せして電子ビーム露光を行い、これを現像してゲ
ートパターンが窓明けされる（図Ｃ）。 For example, as a high-sensitivity resist, CMR
(Crosslinked Methyl meta-acrylate Resist)
However, commercially available PMMA is also used as a normal sensitivity resist.
In this example, approximately
Spin coat in 0.5 [μm] increments to a thickness of approximately 1 [μm]
A coating film is created, a gate pattern is aligned with this film, electron beam exposure is performed, and this is developed to open the gate pattern (Figure C).
こゝで高感度レジスト層１５は通常感度レジス
ト層１６に較べてより広い面積に互つて感光して
いるため現像処理によりオーバーカツト形状１７
が形成される。 Here, since the high-sensitivity resist layer 15 is exposed to light over a wider area than the normal-sensitivity resist layer 16, an overcut shape 17 is created by the development process.
is formed.
次にCCl2F2ガスをエツチヤントとしリアクテ
イブイオンエツチングでエツチングすることによ
りＮ型グレーデイツドAlxGa1-xAs層８にまでリ
セス１０を形成する（図Ｄ）。 Next, by reactive ion etching using CCl 2 F 2 gas as an etchant, a recess 10 is formed up to the N-type graded AlxGa 1-x As layer 8 (FIG. D).
この形成方法は従来行われている方法と同じで
あるが、リセス１０の幅は通常感度レジスト層１
６で決められたパターンと同一である。 This formation method is the same as the conventional method, but the width of the recess 10 is normally the same as that of the sensitive resist layer 1.
The pattern is the same as that determined in step 6.
次に通常感度レジスト層１６のみを溶解して高
感度レジスト層１５のみを残す。かゝる選択的な
溶媒として本実施例の場合はアセトンを用いた。
すなわちアセトンはPMMAレジストは溶かすが
CMRレジストは溶解しない。 Next, only the normal sensitivity resist layer 16 is dissolved, leaving only the high sensitivity resist layer 15. In this example, acetone was used as such a selective solvent.
In other words, acetone dissolves PMMA resist, but
CMR resist does not dissolve.
次にこの状態でゲート電極用金属（この場合
Ti−Pt−Auをスパツタリング或は真空蒸着法で
形成するとリセス１０にセルフアライメントされ
たゲート電極１２が形成される（図Ｅ）。 Next, in this state, the metal for the gate electrode (in this case
When Ti--Pt--Au is formed by sputtering or vacuum evaporation, a gate electrode 12 that is self-aligned in the recess 10 is formed (FIG. E).
こゝでゲート電極１２の形状は高感度レジスト
層１５の開口部パターンと同じであり、リセス１
０の頂部にあるノンドープGaAs層１１にまたが
つてゲート電極１２が形成されることになる。 Here, the shape of the gate electrode 12 is the same as the opening pattern of the high-sensitivity resist layer 15, and the recess 1
A gate electrode 12 is formed spanning the non-doped GaAs layer 11 on top of the gate electrode.
次に高感度レジスト層１５をレジスト剥離液例
えば市販のAZ剥離液或はOMR剥離液を用いて除
去することにより第３図の構造をとることができ
る。このような構造をとる場合はFETのゲート
長はリセス１０の幅により決るため静特性は向上
し、一方ゲート抵抗Rgはゲート電極１２により
決るため抵抗値の増大を防ぐことができる。 Next, the structure shown in FIG. 3 can be obtained by removing the highly sensitive resist layer 15 using a resist stripping solution such as a commercially available AZ stripping solution or OMR stripping solution. When such a structure is adopted, the static characteristics are improved because the gate length of the FET is determined by the width of the recess 10, and on the other hand, the gate resistance Rg is determined by the gate electrode 12, so an increase in resistance value can be prevented.
次にこの構造をとる場合はゲート電極１２の張
り出しにより接触面積が増し、それによる静電容
量の増加が考えられるが、ノンドープGaAs層１
１が設けてあるため静電容量の増大は抑制されて
いる。こゝでゲート電極１２の張り出しによる静
電容量の増加を更に抑制する方法としてはノンド
ープGaAs層１１の代りにこれよりも誘電率が低
い二酸化硅素（SiO2）層を用いれば効果的であ
る。 Next, if this structure is adopted, the contact area will increase due to the overhang of the gate electrode 12, which may increase the capacitance, but the non-doped GaAs layer 1
1, the increase in capacitance is suppressed. Here, as a method for further suppressing the increase in capacitance due to the protrusion of the gate electrode 12, it is effective to use a silicon dioxide (SiO 2 ) layer, which has a lower dielectric constant, in place of the non-doped GaAs layer 11.
なおこの場合第５図Ｄに示すリセス１０の形成
を行うには初めCHF3ガスをエツチヤントとして
リアクテイブイオンエツチングを行つてSiO2層
を窓明けした後、ガスをCCl2H2ガスに置換して
再びリアクテイブイオンエツチングを行う必要が
ある。 In this case, to form the recess 10 shown in FIG. 5D, first perform reactive ion etching using CHF 3 gas as an etchant to open a window in the SiO 2 layer, and then replace the gas with CCl 2 H 2 gas. It is necessary to perform reactive ion etching again.
なおトランジスタ形式においてＮ型GaAs層９
の上に直接SiO2層を設けるよりも第４図に示す
ようにゲート形成領域をノンドープGaAs層１１
とSiO2１５の２層構成で形成すれば安定な表面
状態をもち且つ静電容量の増大のないトランジス
タを得ることができる。 Note that in the transistor format, the N-type GaAs layer 9
Rather than providing a SiO 2 layer directly on top of the gate formation region as shown in Figure 4,
By forming a two-layer structure of SiO 2 15 and SiO 2 15, a transistor having a stable surface state and no increase in capacitance can be obtained.
(g) 発明の効果
本発明の実施によりFETの小形化に伴うゲー
ト抵抗の増大を抑制することができ、従つて特性
を向上することが可能である。(g) Effects of the Invention By carrying out the present invention, it is possible to suppress an increase in gate resistance due to miniaturization of FETs, and therefore it is possible to improve characteristics.
第１図はFETの平面図、第２図は従来の高電
子移動度トランジスタの断面構造図、第３図およ
び第４図は本発明に係る方法で形成した同種トラ
ンジスタの断面構造図、また第５図Ａ〜Ｅは本発
明に係る製造工程の説明図である。
図において、１，１２はゲート、２，１３はソ
ース、３，１４はドレイン、１０はリセス、１１
はノンドープGaAs層、１５は高感度レジスタ
層、１６は普通感度レジスト層、１７はオーバカ
ツト形状、１８はSiO2層。
FIG. 1 is a plan view of an FET, FIG. 2 is a cross-sectional structural diagram of a conventional high electron mobility transistor, and FIGS. 3 and 4 are cross-sectional structural diagrams of the same type of transistor formed by the method according to the present invention. 5A to 5E are explanatory diagrams of the manufacturing process according to the present invention. In the figure, 1 and 12 are gates, 2 and 13 are sources, 3 and 14 are drains, 10 is a recess, and 11
15 is a non-doped GaAs layer, 15 is a high-sensitivity resist layer, 16 is a normal-sensitivity resist layer, 17 is an overcut shape, and 18 is a SiO 2 layer.
Claims (1)
導体基板の最上層に設けた絶縁層をゲート電極形
成領域を除いて除去し、ソースおよびドレイン電
極パターンの形成を行つた後、該基板上に上層が
通常感度で下層が高感度の２層からなるレジスト
膜を形成し、ゲート電極パターンの露光、現像と
開口部へのドライエツチングを行い、上層のレジ
ストパターンにより定まるリセスを形成し、次に
上層のレジストパターンを除去し、下層のレジス
トパターンを用いてゲート電極形成用金属の蒸着
を行いリフトオフ法によりゲート電極パターンを
形成することを特徴とする半導体装置の製造方
法。 ２ 半導体基板がガリウム砒素単結晶よりなり、
最上層に設けた絶縁層が分子線エピタキシーで形
成したノンドープガリウム砒素層からなることを
特徴とする特許請求の範囲第１項記載の半導体装
置の製造方法。 ３ 半導体基板がガリウム砒素単結晶よりなり最
上層に設けた絶縁層が二酸化砒素層からなること
を特徴とする特許請求の範囲第１項記載の半導体
装置の製造方法。[Claims] 1. In the manufacturing process of a field effect transistor, the insulating layer provided on the top layer of the semiconductor substrate is removed except for the gate electrode formation region, and the source and drain electrode patterns are formed. A resist film consisting of two layers, the upper layer having normal sensitivity and the lower layer having high sensitivity, is formed, and the gate electrode pattern is exposed and developed, and the opening is dry etched to form a recess determined by the upper layer resist pattern. 1. A method for manufacturing a semiconductor device, comprising: removing an upper resist pattern; using the lower resist pattern, depositing a metal for forming a gate electrode; and forming a gate electrode pattern by a lift-off method. 2. The semiconductor substrate is made of gallium arsenide single crystal,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating layer provided as the uppermost layer is composed of a non-doped gallium arsenide layer formed by molecular beam epitaxy. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made of a gallium arsenide single crystal, and the insulating layer provided as the uppermost layer is made of an arsenic dioxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12884483A JPS6021574A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12884483A JPS6021574A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6021574A JPS6021574A (en) | 1985-02-02 |
| JPH0362017B2 true JPH0362017B2 (en) | 1991-09-24 |
Family
ID=14994778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12884483A Granted JPS6021574A (en) | 1983-07-15 | 1983-07-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6021574A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2442030A (en) * | 2006-09-19 | 2008-03-26 | Innos Ltd | Resist exposure and patterning process |
| US8105889B2 (en) * | 2009-07-27 | 2012-01-31 | Cree, Inc. | Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions |
-
1983
- 1983-07-15 JP JP12884483A patent/JPS6021574A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6021574A (en) | 1985-02-02 |
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