JP3326928B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a field-effect transistor having a reduced parasitic resistance without deteriorating device characteristics due to an increase in source-gate capacitance, and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 7 and 8 are explanatory views of a conventional example. In the figure, 15 to 18 are semiconductor substrates, 25 to 28 are buffer layers,
35-38 channel layer, 45 is an electron supply layer, 46a is n ⁺ electron supply layer, 46b the n ^- electron supply layer, 47a the n ^- - InAlAs electron supply layer, 47b is i-InAlAs layer, is 55 to 58 Cap layer,
55a to 56a and 58a are n ^-- GaAs cap layers, and 55b to 56b
, 58b are n ⁺ -GaAs cap layers, 55c to 56c, 57b, 58
c is an n ⁺ -InGaAs cap layer, 85 to 88 are gate electrodes, 95
a to 98a are source electrodes, and 95b to 98b are drain electrodes.

[0003] For high integration and high performance of HEMTs and MESFETs, it is desired to use non-alloy ohmic electrodes with high reliability, high heat resistance, low resistance and miniaturization. To take full advantage of the non-alloy ohmic electrode, it is necessary to reduce the resistance between the electrode and the two-dimensional electron gas as low as possible. However, the conventional structure cannot make the resistance sufficiently low.

The reason will be described with reference to FIG. In a field-effect transistor having a recess gate structure, the lower layer of the cap layer 55 may come into contact with the gate electrode 85. Therefore, unless the carrier concentration in this portion is reduced, the gate breakdown voltage decreases and the gate-source capacitance also increases. As a result, the element characteristics deteriorate such that the response becomes slow. The contact can be prevented by increasing the distance between the source and the gate, but the parasitic resistance increases by the increase in the distance.

Therefore, the carrier concentration in the lower layer of the cap layer 55, which may come into contact with the gate electrode 85, is set to 1-2 × 10 ¹⁸
cm ^-3 , and the resistance in this area is not sufficiently low. In the HEMT of the n ⁻ -InAlAs / InGaAs layer, since the Schottky barrier of the InAlAs layer is low, the i-InAlAs layer 47b is inserted on the electron supply layer as shown in FIG. 8C. As shown in FIG. 7B, the electron supply layer formed on the semiconductor substrate 16 is composed of an HEMT of an InGaP layer or an AlGaAs layer.
Among them, in the structure in which the carrier concentration of the electron supply layer 46 is increased for higher performance, the carrier concentration in the upper layer portion of the electron supply layer 46 is reduced in order to secure the gate breakdown voltage.
These layers also exist in the source and drain portions, which cause an increase in parasitic resistance.

FIG. 8D shows an example of a conventional MESFET, which has the same problem in structure as the HEMT.

[0007]

As described above, in order to reduce the parasitic resistance, the resistance between the ohmic electrodes forming the source / drain electrodes and the two-dimensional electron gas in the electron supply layer is as low as possible, that is, as high as possible. Carrier concentration (5 × 10
⁽¹⁸ cm ^-3 or more), a low carrier concentration layer exists to prevent the introduction of other factors that degrade the device characteristics.

It is an object of the present invention to provide a field effect transistor which does not include a low carrier concentration layer between an ohmic electrode and a two-dimensional electron gas while preventing the introduction of other factors which deteriorate device characteristics, and a method of manufacturing the same. With the goal.

[0009]

FIG. 1 is an explanatory view of the principle of the present invention, and is a schematic cross-sectional view showing formation of an intrinsic compound semiconductor layer on a side wall of a cap layer. In the figure, 1 is a semiconductor substrate, 3
Is a channel layer, 4 is an electron supply layer, 5 is a cap layer, 6 is an opening, 7 is an intrinsic compound semiconductor layer, 8 is a gate electrode, 9
Denotes source / drain electrodes.

In the present invention, as shown in the schematic cross-sectional view of FIG. 1, in order to prevent contact between the gate electrode 8 and the high-concentration cap layer 5, a semiconductor layer having a low carrier concentration, for example, only between both layers, for example. An intrinsic compound semiconductor layer 7 is formed. Also,
When the electron supply layer 4 having a low Schottky breakdown voltage is used, a low-concentration semiconductor layer, for example, an intrinsic compound semiconductor layer 7 is formed just below the gate electrode 8.

FIG. 2 is an explanatory view of two kinds of manufacturing methods of a semiconductor layer having a low carrier concentration, for example, an intrinsic compound semiconductor layer 7 unique to the present invention. FIGS. 2A to 2C are explanatory diagrams of a method of forming the intrinsic compound semiconductor layer 7 having a low carrier concentration only on the side wall of the cap layer 5.

First, as shown in FIG. 2A, an opening for forming a recess gate electrode is formed by removing the cap layer 5 only in the recess region by dry etching using an insulating film mask such as a SiO ₂ film (not shown). The part 6 is formed.

Next, as shown in FIG. 2B, after removing the mask made of the SiO ₂ film with hydrofluoric acid, an i-GaAs layer, for example, as an intrinsic compound semiconductor layer 7 is grown on the entire surface. Since this growth is isotropic, the intrinsic compound semiconductor layer 7 also grows on the side wall of the opening 6.

Finally, as shown in FIG. 2C, the intrinsic compound semiconductor layer 7 having the same thickness as the grown intrinsic compound semiconductor layer 7 is dry-etched. Since this dry etching is anisotropic, only the intrinsic compound semiconductor layer 7 grown on the side wall is left in the opening 6.

FIGS. 2D to 2F are explanatory views of a method for forming a semiconductor layer having a low carrier concentration, for example, an intrinsic compound semiconductor layer 7 immediately below the side wall and the gate of the cap layer 5. First, as shown in FIG. 2D, the cap layer 5 is removed only in the recess region by dry etching using a mask made of an insulating film 10 such as an SiO ₂ film.

Next, as shown in FIG. 2E, an intrinsic compound semiconductor layer 7 having a low carrier concentration is selectively grown only in the exposed portion inside the opening 6 using the mask of the insulating film 10. Finally, as shown in FIG. 2F, the insulating film 10 used as a mask is removed with hydrofluoric acid to form a coating layer of the intrinsic compound semiconductor layer 7 only on the side walls and the bottom in the opening 6.

That is, as shown in FIG. 1, an object of the present invention is that at least a channel layer 3, an electron supply layer 4, and a cap layer 5 are laminated on a semiconductor substrate 1, and a recess structure is formed in an opening 6 of the cap layer 5. In the field effect transistor , the source / drain electrode 9 is provided on the gate electrode 8 and the cap layer 5, and the intrinsic compound semiconductor layer 7 is formed at least on the exposed portion of the side wall of the cap layer 5 close to the gate electrode 8. relates to a manufacturing method of a field effect transistor comprising Te, FIG. 2
As shown in (a) to (c), the semiconductor substrate 1
A tunnel layer 3, an electron supply layer 4, and a cap layer 5 are sequentially laminated.
And that step, a step of providing an opening 6 in the recess structure gate electrode formation region of the cap layer 5, including the opening 6,
Forming an intrinsic compound semiconductor layer 7 on the semiconductor substrate 1, the said vacuum compound semiconductor layer 7 to anisotropic dry etching, by leaving the intrinsic compound semiconductor layer 7 only on the side wall of the cap layer 5 Alternatively, FIGS. 2 (d) to 2 (f)
As shown in, for selective growth a step of providing an opening 6 the patterned insulating film 10 in the recess structure gate electrode formation region of the cap layer 5 as a mask, an intrinsic compound semiconductor layer 7 only the opening 6 a step is accomplished by including the step of removing the insulating film 10.

[0018]

There is a technique for preventing the contact between the gate electrode and the cap layer by forming an insulating film on the side wall of the cap layer, but differs from the present invention in the following points.

First, first, if an insulating film is used to cover the side wall, the damage caused during etching is large. However, in the present invention, the damage can be suppressed to a small level because a semiconductor etching technique can be used. It is possible.

Second, when an insulating film is used, a local difference is applied due to a large difference in thermal expansion coefficient between the insulating film and the semiconductor layer. However, in the present invention, a semiconductor layer having a close thermal expansion coefficient is used. , It is possible to suppress distortion.

Further, in the present invention, since a low carrier concentration layer is not interposed between the ohmic electrode and the two-dimensional electron gas, there is no increase in gate breakdown voltage and parasitic capacitance.

[0022]

3 to 6 are schematic sectional views of several embodiments of a field effect transistor according to the present invention.

In the figures, 11 to 14 are GaAs substrates, 21a to 22
a and 24a are i-GaAs buffer layers, 21b to 22b and 24b are i-AlG
aAs buffer layer, 23a is i-InP buffer layer, 23b is InAlA
s buffer layer, 31a to 32a are i-GaAs or AlGaAs channel layers, 33 is an i-InGaAs channel layer, 34 is an n ^-- GaAs channel layer, 41 to 42 are n ^-- GaInP or n ^-- AlGaAs electron supply layers, 43 is an n ^-- InAlAs electron supply layer, 51a to 52a, 54a
Are n ⁺ -GaAs cap layers, 51b to 52b, 54b are n ⁺ -InG
aAs cap layer, 53 is an n ⁺ -InGaAs cap layer, 71, 74
Is an i-GaAs layer, 72 is an i-InGaP or i-AlGaAs layer, 73 is i-In
An AlAs layer, 81 to 84 are gate electrodes, 91a to 94a are source electrodes, and 91b to 94b are drain electrodes.

First, a first embodiment of the present invention will be described with reference to FIG. MO on a semi-insulating GaAs substrate 11
A 2,000-mm-thick i-GaAs buffer layer 21 is formed by the VPE method.
a, 3,000 mm thick i-AlGaAs buffer layer 21b, 2,000
A 0Å thick i-GaAs channel layer 31a, a 100Å thick i-GaAs channel
N of the thickness of the InGaAs channel layer 31b, 400 Å ^{- -} GaInP or n ^- - AlGaAs electron supply layer, the thickness of 500 Å n ⁺ GaAs
Cap layer 51a, 500 nm thick n ⁺ InGaAs cap layer
51b are sequentially laminated.

Next, an n ⁺ GaAs having a high carrier concentration in the opening is formed by using a 1,000-mm-thick SiO ₂ film mask having an opening in a region where a recess is to be formed, formed by plasma CVD and photolithography. Cap layer 51a, n ⁺ In
Only the GaAs cap layer 51b was removed by dry etching with CCl ₂ F ₂ to form a recess structure.

After the SiO ₂ film used as the mask was removed with hydrofluoric acid, an i-GaAs layer 71 was grown on the entire surface of the GaAs substrate 11 to a thickness of 100 ° by MOVPE again. next,
By dry etching with CCl ₂ F ₂ , the high carrier concentration n ⁺ GaAs cap layer 51 a in the recess structure, the n ⁺ InGaAs cap layer 51 b, leaving only the i-GaAs layer 7 on the side wall, i-Ga
The As layer 7 was etched.

Finally, a source electrode 91a and a drain electrode 91b made of Ti / Al having a thickness of 3,000 mm and a gate electrode 81 made of an Al film having a thickness of 3,000 mm were formed. Next, a second embodiment of the present invention will be described with reference to FIG.

On the semi-insulating GaAs substrate 12, an i-GaAs buffer layer 22a having a thickness of 2,000 .ANG.
0 Å of the thickness of the i-AlGaAs buffer layer 22b, 2,000 Å of the thickness of the i-GaAs channel layer 32a, 100 Å of the thickness of the i-InGaAs channel layer 32b, the thickness of 2,000 Å n ^{- -} InGaP or n
^- - the thickness of the AlGaAs electron supply layer 42,500 Å thick of n ⁺ GaAs cap layer 52a, 500 Å n ⁺ InGaAs cap layer 52b
Are sequentially laminated.

Next, a high carrier concentration n ⁺ GaAs having a high carrier concentration in the opening is formed by using a 1,000-mm thick SiO ₂ film mask having an opening in a region where a recess is to be formed, which is formed by plasma CVD and photolithography. Cap layer 52a, n ⁺ In
Only the GaAs cap layer 52b was removed by dry etching with CH ₃ Br to form a recess structure.

Using this mask, an i-InGaP or i-AlGaAs layer 72 was grown only in the opening by MOVPE.
Thereafter, the mask is removed with hydrofluoric acid. Next, 3,000 Å
And drain electrodes 92a and 92a made of Ti / Au
A gate electrode 82 made of TI / Pt having a thickness of 2,000 mm was formed on 92b.

Next, a third embodiment of the present invention will be described with reference to FIG. MO on a semi-insulating GaAs substrate 13
A 500 厚 thick i-InP buffer layer 23a is formed by the VPE method.
3,000 3,000 thick InAlAs buffer layer 23b 2,500
I thick i-InGaAs channel layer 33, 4,000 厚 thick n
^- sequentially stacked n ⁺ InGaAs cap layer 53 having a thickness of -InGaAs electron supply layer 43,500 Å.

Next, a high carrier concentration n ⁺ InGaAs having a high carrier concentration in the opening is formed by using an SiO ₂ film mask having a thickness of 1,000 mm and having an opening in a region where a recess is to be formed, formed by using the plasma CVD technique and the photolithography technique. Only cap layer 53 is C
The recess was removed by dry etching with H ₃ Br to form a recess structure.

Using this mask, the MOVPE method
An i-InAlAs layer 73 was grown to a thickness of 1,000 mm only in the opening. Thereafter, the mask is removed with hydrofluoric acid. Finally, a 3,000-mm-thick source electrode 93a and a drain electrode 93b made of Ti / Al, and a 3,000-mm-thick gate electrode 83 made of an Al film were formed.

Next, the present invention will be described with reference to FIG.
A fourth embodiment applied to T will be described. On a semi-insulating GaAs substrate 14, an 2,000-mm-thick i-GaAs buffer layer 24a and a 3,000-mm-thick i-AlGa
As buffer layer 24b, 1,000Å thick n ^-- GaAs channel layer 34, 500Å thick n ⁺ -GaAs cap layer 54a, 500
An n ⁺ -InGaAs cap layer 54b having a thickness of Å is sequentially laminated.

[0035] Next, using the SiO ₂ film mask having a thickness of 1,000 Å with an opening to the recess forming area created by a plasma CVD technique and a photolithography technique, a high carrier concentration of the opening n ⁺ - GaAs cap layer 54a, n ⁺ -
Only the InGaAs cap layer 54b was removed by dry etching with CCl ₂ F ₂ to form a recess structure.

After removing the SiO ₂ film used as a mask with hydrofluoric acid, an i-GaAs layer 74 was grown on the entire surface of the GaAs substrate 11 to a thickness of 100 ° by MOVPE again. next,
By dry etching with CCl ₂ F ₂ , high carrier concentration n ⁺ -GaAs cap layer 54a in the recess structure, n ⁺ -InGa
The i-GaAs layer 74 was etched while leaving only the As cap layer 54b and the i-GaAs layer 74 on the side wall.

Finally, a source electrode 94a and a drain electrode 94b made of Ti / Al having a thickness of 3,000 mm, and a gate electrode 84 made of an Al film having a thickness of 3,000 mm were formed.

[0038]

As described above, according to the structure and the manufacturing method of the present invention, compared with the conventional example, a low-resistance semiconductor layer is formed on the side wall of the cap layer to make contact between the gate electrode and the cap layer. In order to prevent this, the parasitic resistance is reduced to ／, and the effect of reducing the parasitic resistance of the present invention is confirmed without deteriorating the element characteristics.
It greatly contributes to the improvement of the characteristics of the field effect transistor such as T.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention (part 1).

FIG. 2 is a diagram illustrating the principle of the present invention (part 2).

FIG. 3 is a block diagram of an apparatus according to a first embodiment of the present invention.

FIG. 4 is a block diagram of an apparatus according to a second embodiment of the present invention.

FIG. 5 is an apparatus configuration diagram according to a third embodiment of the present invention.

FIG. 6 is a configuration diagram of an apparatus according to a fourth embodiment of the present invention.

FIG. 7 is an explanatory view of a conventional example (part 1).

FIG. 8 is an explanatory view of a conventional example (part 2).

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 3 channel layer 4 electron supply layer 5 cap layer 6 opening 7 intrinsic compound semiconductor layer 8 gate electrode 9 source / drain electrode 10 insulating film 11-14 GaAs substrate 21a-22a, 24a i-GaAs buffer layer, 21b- 22b, 24b i-AlGaAs buffer layer 23a i-InP buffer layer 23b InAlAs buffer layer 31a to 32a i-GaAs or AlGaAs channel layer 33 i-InGaAs channel layer 34 n ^-- GaAs channel layer 41 to 42n ^-- GaInP or n ^- -AlGaAs electron supply layer 43 n ^- type InAlAs electron supply layer 51a ~52a, 54a n ⁺ -GaAs cap layer 51b ~52b, 54b n ⁺ -InGaAs cap layer 53 n ⁺ -InGaAs cap layer 71 and 74 i-GaAs layer 72 i-InGaP or i-AlGaAs layer 73 i-InAlAs layer 81 to 84 Gate electrode 91a to 94a Source electrode 91b to 94b Drain electrode

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 29/778 H01L 29/812

Claims (2)

(57) [Claims] 1. A channel layer and an electron supply on a semiconductor substrate.
Sequentially stacking a layer and a cap layer, and forming an opening in the recessed gate electrode formation region of the cap layer.
A step of the Ru provided, including the opening, an intrinsic compound semiconductor on the semiconductor substrate
Step of forming a layer, anisotropic dry etching of the intrinsic compound semiconductor layer,
The intrinsic compound semiconductor layer is left only on the side wall of the cap layer
And a method for manufacturing a field effect transistor. 2. A semiconductor device comprising : a channel layer on a semiconductor substrate;
Sequentially laminating a layer and a cap layer, and forming a pattern on the recessed gate electrode formation region of the cap layer.
The step of providing an opening using the patterned insulating film as a mask
If, selective growth of said vacuum compound semiconductor layer only on the opening in the
Field effect transistor comprising the steps, and removing the insulating film
Manufacturing method.