JP2002141499A - Field effect transistor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a gate leakage current of a field effect transistor comprising a gate electrode whose cross-section shape is T-like. SOLUTION: A first insulating film 11 comprising an SiO2 film and a second insulating film 12 comprising an SiO film are formed in different regions, respectively, on an ohmic contact layer 27. The ohmic contact layer 27 between them is removed by etching. The gate electrode 15 whose cross-section is T-like is formed to contact to one of the gaps. A gate leakage current is reduced because the ohmic contact layer 27 positioned between a source electrode 13 and the SiO2 film 11 as well as between a drain electrode 14 and the SiO2 film 11 is disconnected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, field effect transistors using a GaN-based semiconductor (InAlGaNB-based) instead of a GaAs-based semiconductor or an InP-based semiconductor have been actively developed. GaN-based semiconductors are characterized by a large forbidden band width and a large breakdown electric field. Also, because of the piezo effect in the AlGaN / GaN junction and a high two-dimensional electron gas density can be obtained, it has attracted attention as a high withstand voltage and high output element. In addition, the saturation speed of electrons is high, and it is expected as a high-frequency device.

In order to bring out the characteristics of these elements,
It is effective to make the gate length on the order of 0.1 micron. However, in general, in order to form a 0.1-micron class gate, it is necessary to form a gate pattern by electron beam lithography. However, electron beam writing requires a long writing time and has a low throughput. Further, the electron beam lithography system is expensive and is not suitable for mass production because it is a very expensive process.

Therefore, a method for forming a 0.1-micron class gate electrode at low cost using an optical exposure apparatus already used for mass production of DRAMs and the like has been devised (JP-A-9-246285, JP-A-9-246285). 11-97454, JP-A-11-97455, etc.).

[0005] However, although the methods described in these publications can form the gate in the order of 0.1 micron, there is a problem that the leak current increases between the gate electrode and the source or drain electrode.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and provides an electric field which can be formed to a gate size of 0.1 micron and which does not cause a leak current between the gate electrode and the source or drain electrode. An object of the present invention is to provide an effect transistor and a method for manufacturing the same.

Another object of the present invention is to provide a high performance field effect transistor using a GaN-based semiconductor and a method of manufacturing the same.

[0008]

In order to achieve the above object, a semiconductor substrate having at least a Schottky contact layer and an ohmic contact layer formed on an upper surface thereof, and a source electrode formed on the ohmic contact layer are provided. An insulating film and a drain electrode, and a gate electrode that penetrates the insulating film and the ohmic contact layer and is joined to the Schottky contact layer.
An ohmic contact layer formed under at least one of the source electrode and the drain electrode is separated from an ohmic contact layer formed under the insulating film.

In this case, it is preferable that the semiconductor substrate has a structure in which at least an electron transit layer, an electron supply layer, the Schottky contact layer, and the ohmic contact layer are sequentially laminated.

It is preferable that the semiconductor substrate includes a GaN-based semiconductor layer.

The present invention also provides a semiconductor device having at least a Schottky contact layer and an ohmic contact layer formed on an upper surface thereof, wherein the first insulating film and the first insulating film are sandwiched in an in-plane direction; Forming a source electrode and a drain electrode apart from each other; forming a first resist pattern so as to have a first opening in a part of the first insulating film; Using the pattern as a mask, isotropic etching is performed, and the first
Removing the first insulating film located in the opening and the first insulating film located in the region enlarged from the first opening to expose the ohmic contact layer;
Using the first resist pattern as a mask, forming a second insulating film on the ohmic contact layer so as to leave the enlarged region as a void, removing the first resist pattern, Source electrode,
Etching the ohmic contact layer exposed from the drain electrode, the first insulating film, and the second insulating film to expose the Schottky contact layer; and forming a second opening in at least a part of the gap. Forming a second resist pattern so as to have a portion, depositing a conductive film serving as a gate electrode on the Schottky contact layer and the second resist pattern exposed in the gap, Forming a gate electrode while leaving the conductive film in the gap by removing the resist pattern of No. 2 above.

In this case, it is preferable that the semiconductor substrate has a structure in which at least an electron transit layer, an electron supply layer, the Schottky contact layer, and the ohmic contact layer are sequentially laminated.

Preferably, the semiconductor substrate includes a GaN-based semiconductor layer.

In the present invention, a source electrode and a drain electrode are formed on a semiconductor substrate on which an ohmic contact layer has been formed. An SiO ₂ film, for example, is deposited as a first insulating film between the source electrode and the drain electrode. Next, Si
A first resist pattern is formed so as to open a predetermined region on the O ₂ film. Then, S is etched by isotropic etching.
The iO ₂ film is etched to expose the semiconductor substrate. In this case, the end surface of the SiO ₂ film is recessed from the opened side wall of the first resist pattern. That is, a part of the region is side-etched from the predetermined region to below the first resist pattern.

Next, an SiO film is deposited as a second insulating film, and the resist is removed. By doing so, a void of 0.1 micron class is formed between the end face of the SiO ₂ film and the end face of the SiO film.

Next, the ohmic contact layer is etched using the source electrode and the drain electrode, and the SiO ₂ film and the SiO film as masks. By doing so, the distance between the gate electrode, the source electrode, and the drain electrode is reduced to 0.1.
The 1-micron gap allows the ohmic contact layer to be cut, thereby preventing a leak current between the gate electrode, the source electrode, and the drain electrode without deteriorating device characteristics.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an AlGaN / GaN according to the present invention.
1 is a cross-sectional view of a system heterojunction field effect transistor (HFET).

On a sapphire substrate 21, a GaN buffer layer 22, an undoped GaN electron transit layer 23, an undoped AlGaN spacer layer 24, an n-type AlGaN electron supply layer 25, and an undoped AlGaN Schottky contact layer 26 are sequentially laminated.

On the undoped AlGaN Schottky contact layer 26, an n-type GaN ohmic contact layer 27 is formed. n-type GaN ohmic contact layer 27 is divided portion, the second insulating film 12 and the drain electrode 14 made of the first insulating film 11, SiO consisting source electrode 13, SiO ₂ thereon has been formed I have. Between the first insulating film 11 and the second insulating film 12, a gate electrode 1 having a T-shaped cross section and having a pillar portion and an eaves portion is provided.
5 are formed. The width of the portion of the gate electrode 15 that contacts the semiconductor substrate is 0.1 μm. These voids can be controlled by side etching when the first insulating film 11 is isotropically etched. Details of this manufacturing method will be described later.

These elements constitute a field effect transistor. Each element is etched and separated at least until the electron transit layer 23 is reached.

In the field effect transistor thus configured, at least the ohmic contact layer 27 is divided by the gate electrode 15 and the source electrode 13 at intervals of about 0.1 μm. Therefore, it is possible to prevent a leak current between the gate electrode 15 and the source electrode 13 without deteriorating element characteristics. In the present embodiment,
Although the example in which the gate electrode 15 is formed from the source electrode 13 is shown, the gate electrode 15 may be formed between the first insulating film 11 and the second insulating film 12 from the drain electrode 14.

Next, a method of manufacturing the field effect transistor will be described with reference to FIGS.

First, as shown in FIG. 2, molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOC)
A GaN buffer layer 22, an undoped GaN electron transit layer 23, an undoped AlGaN spacer layer 24, an n-type A
An lGaN electron supply layer 25, an undoped AlGaN Schottky contact layer 26, and an n-type GaN ohmic contact layer 27 are sequentially stacked.

The thickness of the GaN buffer layer 22 is 500 n
m, the thickness of the undoped GaN electron transit layer 23 is 2 μm,
The thickness of the undoped AlGaN spacer layer 24 is 3 nm,
The thickness of the n-type AlGaN electron supply layer 25 is 20 nm, the thickness of the undoped AlGaN Schottky contact layer 26 is 5 nm, and the thickness of the n-type GaN ohmic contact layer 27 is 20 nm.

The n-type AlGaN electron supply layer 25 is
Using Si as a dopant, Si concentration 2E18 cm
^-3 . n-type GaN ohmic contact layer 27
Uses Si as a dopant and has a Si concentration of 5E18c.
m ⁻³ . Here, the Al composition of the AlGaN layer was all set to 0.25.

Next, after depositing an SiO ₂ film on the entire surface of the ohmic contact layer 27 by a thermal CVD method or the like, a photoresist is patterned so as to protect the transistor formation region. Next, the SiO ₂ film is etched using the photoresist as a mask. As an etching method, dry etching such as a reactive ion etching (RIE) method or wet etching using ammonium fluoride is used.

Next, after removing the photoresist using oxygen ashing or an organic solvent, using the remaining SiO ₂ film as a mask, the transistor formation region is etched in a convex shape to perform element isolation. At this time, the etching is performed using n-type GaN.
The ohmic contact layer 27, the undoped AlGaN Schottky contact layer 26, the n-type AlGaN electron supply layer 25, the undoped AlGaN spacer layer 24, and the undoped GaN electron transit layer 23 are sequentially etched. The etching method uses, for example, ECR (Electron Cycl
otron Resonance)-Performed by RIBE.

The amount of etching of the undoped GaN electron transit layer 23 can be completely completed if the region where the two-dimensional electron gas is formed, that is, the interface surface region between the electron transit layer 23 and the spacer layer 24 is sufficiently etched. It is not necessary to remove by etching.

Next, S used as an etching mask
The iO ₂ film is once removed with ammonium fluoride.

Next, as shown in FIG.
₂The film 11 is deposited by a thermal CVD method or the like. Next, saw
To form openings in the gate electrode and drain electrode formation regions.
The photoresist 31 is patterned. Next, the photo cashier
SiO in the area where the strike 31 was opened₂Ammonium fluoride membrane
Etch isotropically with um. At this time, SiO ₂
A part of the film is formed by photoresist 31 by side etching.
Retreat to the lower part of the end face. Next, Ti / Al / N
An i / Au film 32 is sequentially deposited.

Next, the source electrode 1 made of Ti / Al / Ni / Au is formed on the n-type GaN ohmic contact layer 27 by lift-off by removing the photoresist 31.
3 and the drain electrode 14 can be formed. An ohmic junction between the electrode 13 and the drain electrode 14 is obtained. In this manner, the distance between the source electrode 13 and the first insulating film 11 and the distance between the drain electrode 14 and the first insulating film can be formed.

Next, as shown in FIG. 4, a photoresist is deposited on the entire surface to form a source electrode 13 and a drain electrode 1.
The first resist pattern 41 is formed by patterning so as to open a predetermined region of the first insulating film 11 at a position sandwiched between the first resist pattern 41 and the first resist pattern 41.

Next, as shown in FIG. 5, using the first resist pattern 41 as a mask, the first insulating film 11 is isotropically etched using ammonium fluoride. At this time, the first insulating film 11 is side-etched and receded to below the side surface of the first resist pattern 41. continue,
An SiO film is deposited on the entire surface, and the second insulating film 12 is formed so as to have a gap with the end surface of the first insulating film 11.

Next, as shown in FIG. 6, by removing the first resist pattern 41, the second insulating film 12 is formed by lift-off. In this step, the gap width between the second insulating film 12 and the first insulating film 11 can be adjusted to about 0.1 μm by adjusting the etching time of the first insulating film 11.

Next, as shown in FIG.
3. Using the first insulating film 11, the second insulating film 12, and the drain electrode 14 as a mask, the n-type GaN ohmic contact layer 27 is etched to expose the undoped AlGaN Schottky contact layer 26. As an etching method, for example, etching can be performed using an inert gas such as a chlorine-based gas or argon, or hydrogen. By this step, the ohmic contact layer 27 can be divided.

Next, as shown in FIG. 8, a second resist pattern is patterned so as to open the gate electrode formation region. Then, by sequentially depositing the Ni / Au film 15 on the entire surface, the gate electrode 15 having the pillar portion and the eaves portion and having a T-shaped cross section can be formed. This gate electrode 15
And the contact width between the contact and the Schottky contact layer 26 is 0.1 mm.
It can be controlled to about 1 micron. Next, the second resist pattern 81 is removed and lift-off is performed. Thereafter, a heat treatment is performed at 400 ° C. so that the gate electrode 1
5 is improved. Through the above steps, the field effect transistor shown in FIG. 1 can be manufactured.

In this embodiment, a substrate in which a GaN-based semiconductor layer is formed on a sapphire substrate is used as a semiconductor substrate, but a substrate in which a GaN-based semiconductor layer is formed on a SiC substrate may be used. Further, by using a GaN substrate or the like, a better field effect transistor can be formed without applying unnecessary strain to the growth layer made of each GaN-based semiconductor.

In this embodiment, the structure in which the insulating film remains under the eaves of the gate electrode has been described. However, these insulating films may be removed during the manufacturing process.

[0040]

According to the present invention, there is provided a field effect transistor which has a small leak current between a gate electrode and a source electrode or a drain electrode, can control a gate width to about 0.1 μm, and has high frequency characteristics and high withstand voltage. Can be.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a field-effect transistor according to the present invention.

FIG. 2 is a cross-sectional view in each manufacturing step of the field-effect transistor according to the present invention.

FIG. 3 is a cross-sectional view in each manufacturing step of the field-effect transistor according to the present invention.

FIG. 4 is a cross-sectional view in each manufacturing step of the field-effect transistor according to the present invention.

FIG. 5 is a cross-sectional view in each manufacturing step of the field-effect transistor according to the present invention.

FIG. 6 is a cross-sectional view of each step of manufacturing the field-effect transistor according to the present invention.

FIG. 7 is a cross-sectional view of each step of the manufacturing process of the field-effect transistor according to the present invention.

FIG. 8 is a cross-sectional view of a field-effect transistor according to the present invention in each manufacturing step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... 1st insulating film 12 ... 2nd insulating film 13 ... Source electrode 14 ... Drain electrode 15 ... Gate electrode 21 ... Sapphire substrate 22 ... GaN buffer layer 23 ... Undoped Ga
N-electron transit layer 24 undoped AlGaN spacer layer 25 n-type AlGaN electron supply layer 26 undoped AlGaN Schottky contact layer 27 n-type GaN ohmic contact layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/417 F term (Reference) 4M104 AA04 AA10 BB05 BB14 CC01 CC03 DD08 DD09 DD10 DD16 DD26 DD34 DD68 DD78 DD83 DD90 DD91 EE14 FF07 FF13 FF22 GG11 HH14 HH20 5F102 FA01 FA05 GA01 GB01 GC01 GD01 GJ04 GJ10 GK04 GL04 GM04 GM08 GN04 GQ01 GR00 GR04 GR09 GS02 GS04 GV07 HC01 HC17

Claims (6)

[Claims] A semiconductor substrate on which at least a Schottky contact layer and an ohmic contact layer formed on an upper surface thereof are formed; a source electrode, an insulating film, and a drain electrode formed on the ohmic contact layer; A source electrode and a drain electrode, wherein the ohmic contact layer formed under at least one of the source electrode and the drain electrode is separated from an ohmic contact layer formed under the insulating film. A field effect transistor characterized by the above-mentioned. 2. The field effect transistor according to claim 1, wherein said semiconductor substrate has a structure in which at least an electron transit layer, an electron supply layer, said Schottky contact layer and said ohmic contact layer are sequentially laminated. . 3. The field effect transistor according to claim 1, wherein said semiconductor substrate includes a GaN-based semiconductor layer. 4. A semiconductor device having at least a Schottky contact layer and an ohmic contact layer formed on an upper surface thereof, and a first insulating film and a source having the first insulating film sandwiched and separated in an in-plane direction. Forming an electrode and a drain electrode; forming a first resist pattern so as to have a first opening in a part of the first insulating film; using the first resist pattern as a mask Removing the first insulating film located in the first opening and the first insulating film located in a region enlarged from the first opening by isotropic etching, and removing the ohmic contact layer And forming a second insulating film on the ohmic contact layer using the first resist pattern as a mask so as to leave the enlarged region as a void. Removing the first resist pattern; etching the ohmic contact layer exposed from the source electrode, the drain electrode, the first insulating film, and the second insulating film; Exposing a contact layer; forming a second resist pattern so as to have a second opening in at least a part of the gap; and forming a second resist pattern on the Schottky contact layer exposed in the gap and the second resist pattern. Depositing a conductive film to be a gate electrode on the resist pattern, and removing the second resist pattern to form a gate electrode while leaving the conductive film in the gap. Of manufacturing a field effect transistor. 5. The field effect transistor according to claim 4, wherein said semiconductor substrate has a structure in which at least an electron transit layer, an electron supply layer, said Schottky contact layer and said ohmic contact layer are sequentially laminated. Manufacturing method. 6. The method according to claim 4, wherein the semiconductor substrate includes a GaN-based semiconductor layer.