JP3128601B2 - High electron mobility transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high electron mobility transistor.

[0002]

2. Description of the Related Art High electron mobility transistors of this type which have been proposed in the past have been proposed.
or, the so-called HEMT) is shown in FIG. 5 and FIG. Here, FIG. 5 is a cross-sectional view schematically showing the outline of the basic configuration of a conventional high electron mobility transistor. FIG. 6 is a cross-sectional view of the high electron mobility transistor having a recess structure according to the first embodiment. It is sectional drawing which shows the outline | summary of a basic structure typically.

That is, in the conventional high electron mobility transistor shown in FIG. 5, a non-doped GaAs semiconductor layer 2 is first placed on a semi-insulating substrate 1 made of GaAs, and then an n-type AlGaAs semiconductor layer. 3 are sequentially stacked, and the ohmic electrodes 5 and 6 are opposed to the central portion of the n-type AlGaAs semiconductor layer 3 so as to sandwich the Schottky electrode 4 therebetween.
Is formed on each of them.

In the case of the conventional structure shown in FIG. 5, the non-doped GaAs semiconductor layer 2 comprises an electron transit layer and the n-type A
The lGaAs semiconductor layer 3 functions as an electron supply layer, and the Schottky electrode 4 functions as a gate electrode, and the ohmic electrodes 5 and 6 function as a source electrode and a drain electrode, respectively. A two-dimensional electron gas (2DE) formed at the hetero interface between the GaAs semiconductor layer 2 and the n-type AlGaAs semiconductor layer 3
G) A high electron mobility transistor using the layer 7 is formed.

Further, in the conventional high electron mobility transistor having the recess structure shown in FIG.
On the semi-insulating substrate 11 made of P, first, a non-doped InP semiconductor layer 12, a non-doped InGaAs semiconductor layer 13, and a non-doped InAlAs semiconductor layer 14, and then an n-type semiconductor layer 15, a non-doped InAlAs semiconductor layer 16, and an n-type InAlAs semiconductor layer 17, n-type InG
aAs semiconductor layers 18 are sequentially stacked, and these n
-Type InAlAs semiconductor layer 17 and n-type InGaAs
Each layer of the semiconductor layer 18 is divided into two regions by a recess groove on the non-doped InAlAs semiconductor layer 16, and a Schottky electrode 19 and a Schottky electrode 1 are formed at the center on the non-doped InAlAs semiconductor layer 16.
N-type InGaAs semiconductor layer 1
Ohmic electrodes 5 and 6 are respectively formed on 8.

In the conventional structure shown in FIG. 6, the non-doped InP semiconductor layer 12 has a buffer layer and a non-doped InG semiconductor layer.
aAs semiconductor layer 13 is an electron transit layer, non-doped InAl
The As semiconductor layers 14 and 16 are spacer layers for more effectively performing selective impurity doping during the growth of the n-type semiconductor layer 15, the n-type semiconductor layer 15 is an electron supply layer, and the n-type InAlAs semiconductor layers 17 and n Type InGaAs
Each of the semiconductor layers 18 acts as a resistance reduction layer,
The Schottky electrode 19 has a gate electrode, the ohmic electrodes 20 and 21 have a source electrode,
It becomes a drain electrode, and here also, non-doped InG
A two-dimensional electron gas layer 22 is formed at a hetero interface between the aAs semiconductor layer 13 and the non-doped InAlAs semiconductor layer 14.

In this case, when a voltage is applied between the source electrode 20 and the drain electrode 21, a current flows through the two-dimensional electron gas layer 22. At this time, by applying a voltage to the gate electrode 19, The transistor operation can be performed by changing the two-dimensional electron gas concentration under the gate.

As described above, the device structure of the high electron mobility transistor here can be roughly classified into the above two types. At present, the device structure of the high electron mobility transistor is based on the latter recess structure which can relatively easily improve the characteristics. The device configuration is often used.

[0009]

However, the threshold voltage of the high electron mobility transistor having the recess structure is 2 times the film thickness of the semiconductor layer when the donor concentration of the semiconductor layer under the gate is constant. It is known that, when the thickness of the semiconductor layer is constant, it changes in proportion to the donor concentration of the semiconductor layer. In the device configuration, how to precisely control the formation of the depth of the recess groove is the biggest key point in improving the characteristics of the device, and when applying a dry process to the formation of this recess groove In general, wet etching is employed because good characteristics cannot be obtained due to damage or contamination during formation.

That is, in the high electron mobility transistor shown in FIG. 6, the n-type InGaAs semiconductor layer 18 and the n-type In
It is necessary to precisely control and remove each layer of the AlAs semiconductor layer 17 and to form the Schottky electrode 19 on the non-doped InAlAs semiconductor layer 16 at an accurate position.

However, in this case, the effective layer thickness of each of these semiconductor layers 18, 17, 16 is very thin, for example, 0.01 μm, 0.025 μm, and 0.02 μm, respectively. Each of these semiconductor layers 18, 1
Precisely removing only 7 is practically and practically very difficult. This is a major factor that hinders the reproducibility of the threshold voltage of the high electron mobility transistor and the yield. Has become.

On the other hand, in the high electron mobility transistor having the recess structure, the InA near the gate exposed by the side etching at the time of the gate recess is operated.
Since the surface of the lAs is deteriorated and characteristics are deteriorated such as an increase in gate leakage current and source resistance, usually, a surface protective film such as a SiN film is formed on the exposed surface of the semiconductor layer to improve the characteristics. Although measures have been taken to suppress fluctuations, the surface of InAlAs directly
When the SiN film is formed, there is a problem that an increase in gate leak current cannot be suppressed, and the SiN film cannot function as a good surface protection film.

Accordingly, the object of the present invention is to
This kind of conventional high electron mobility transistor, which fundamentally solves such a problem and has excellent controllability of the threshold voltage and a device configuration with good reproducibility, has been developed. Another object of the present invention is to provide a high electron mobility transistor having a recess structure.

[0014]

In order to achieve the above-mentioned object, a high electron mobility transistor according to the present invention has a structure in which a semiconductor which serves as an etching stop layer is provided below each semiconductor layer for selectively forming a recess structure. Forming a layer and selectively removing the former semiconductor layer and the latter semiconductor layer separately, or selectively removing only the former semiconductor layer,
In addition, a surface portion of each required semiconductor layer other than each electrode portion is covered with a surface protective film.

That is, the present invention has a larger band gap energy than the buffer layer made of the first semiconductor layer, the electron transit layer made of the second semiconductor layer, and the second semiconductor layer on the semiconductor substrate. A spacer layer composed of a third semiconductor layer, a carrier supply layer composed of a fourth semiconductor layer doped with an impurity of one conductivity type, a fifth semiconductor layer composed of a semiconductor similar to the third semiconductor layer, and a second semiconductor layer. An etching stop layer composed of a sixth semiconductor layer having a band gap energy between the semiconductor layer and the third semiconductor layer, and a seventh semiconductor composed of a semiconductor layer doped with an impurity of the same conductivity type in the third semiconductor layer a layer, and the eighth laminated structure in which semiconductor layers are sequentially laminated consisting of a semiconductor layer doped with impurities of the same conductivity type in the second semiconductor layer, the eighth, seventh and Wherein each semiconductor layer 6 fifth semiconductor
Selectively etched away until the body layer is exposed.
Has a recess structure consisting of recesses, also the first electrode to the fifth semiconductor layer in said recess structure, the first electrode to an eighth semiconductor layer which faces the outside of the recess structure And the second and third electrodes are selectively formed, and a surface protective film is formed on at least the surface of the eighth, seventh and sixth semiconductor layers other than these electrode portions. A high electron mobility transistor characterized by being formed by coating. Further, the eighth and seventh semiconductor layers are
Selectively etch away until the sixth semiconductor layer is exposed
And a recess structure formed by forming a recess , and a first electrode is formed on the sixth semiconductor layer in the recess structure.

[0016]

Therefore, according to the present invention, the eighth, seventh, and sixth semiconductor layers are selectively removed to expose the fifth semiconductor layers, and the eighth, seventh, sixth, and sixth semiconductor layers are exposed. Forming a recess structure on the surface of each fifth semiconductor layer, or
The eighth and seventh semiconductor layers are selectively removed to form a sixth semiconductor layer.
In order to expose each of the semiconductor layers and selectively form a recess structure on each of the eighth, seventh, and sixth semiconductor layer surfaces, the recess structure can be formed with good reproducibility. A first electrode is formed on the exposed fifth semiconductor layer or the sixth semiconductor layer, and a second electrode is formed on an opposing eighth semiconductor layer outside the recess structure with the first electrode interposed therebetween. 3
After selectively forming the respective electrodes, the surface portions of at least the eighth, seventh, and sixth semiconductor layers other than the respective electrode portions are covered with a surface protective film. Insulation can be achieved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high electron mobility transistor according to the present invention will be described below in detail with reference to FIGS.

FIG. 1 is a cross-sectional view schematically showing a schematic configuration of a high electron mobility transistor having a recess structure to which one embodiment of the present invention is applied. FIGS. 2 (a) to 2 (h) show the same. FIG. 3 is a cross-sectional view schematically showing main steps in manufacturing a transistor in sequence, and FIG.
FIG. 4 is a graph for explaining an operation in the recess etching, and FIG. 4 is a cross-sectional view schematically showing a schematic configuration of a high electron mobility transistor having a recess structure to which another embodiment of the present invention is applied. These figures 1 and 2
In the configuration of each embodiment shown in FIGS. 2 and 4, the same reference numerals as those of the conventional configuration shown in FIG. 6 indicate the same or corresponding parts.

That is, in the device of the embodiment shown in FIG. 1, for example, on a semi-insulating substrate 11 made of InP, first, a non-doped high-purity I
an nP semiconductor layer 12, a non-doped high-purity InGaAs semiconductor layer 13 as a second semiconductor layer, and a non-doped high-purity InAlAs semiconductor layer 14 as a third semiconductor layer having a bandgap energy larger than that of the second semiconductor layer. Next, a semiconductor layer 1 of one conductivity type, for example, an n-type (hereinafter the same) as a fourth semiconductor layer 1
5, Non-doped high purity InAl as fifth semiconductor layer
The As semiconductor layer 16, the non-doped high-purity InP semiconductor layer 23 as a sixth semiconductor layer having a band gap energy between the second semiconductor layer and the third semiconductor layer, and subsequently, the seventh semiconductor layer as a seventh semiconductor layer. An n-type InAlAs semiconductor layer 17 and an n-type InGaAs semiconductor layer 18 as an eighth semiconductor layer are sequentially laminated, and the non-doped high-purity InP semiconductor layer 23 and the n-type InAlA
s semiconductor layer 17 and n-type InGaAs semiconductor layer 18
Are divided into two regions by a recess groove on the non-doped high-purity InAlAs semiconductor layer 16, and the first layer is formed at the center on the non-doped InAlAs semiconductor layer 16.
A Schottky electrode 19 as an electrode, and n-type InGaAs
Ohmic electrodes 20 and 21 as second and third electrodes are respectively formed on the semiconductor layer 18, and at least the eighth, seventh and sixth semiconductor layers other than these electrode portions are formed. Is formed by coating an insulating film 24 as a surface protective film.

Even in the case of the embodiment shown in FIG. 1, the non-doped InP semiconductor layer 12 is composed of a buffer layer and the non-doped high-purity InGaAs semiconductor layer 13.
Are the electron transit layer, the non-doped high-purity InAlAs semiconductor layers 14 and 16 are a spacer layer for more effectively performing selective impurity doping during the growth of the n-type semiconductor layer 15, and the n-type semiconductor layer 15 is , Electron supply layer, n-type InAlAs semiconductor layer 17 and n-type InGaAs
The semiconductor layer 18 functions as a resistance reduction layer. Similarly, the Schottky electrode 19 becomes a gate electrode, and the ohmic electrodes 20 and 21 become a source electrode and a drain electrode, respectively. However, the non-doped high-purity InGaAs semiconductor layer 1
A two-dimensional electron gas layer 22 is formed at the hetero interface between the semiconductor layer 3 and the non-doped high-purity InAlAs semiconductor layer 14.

In the case of this embodiment, when a voltage is applied between the source electrode 20 and the drain electrode 21,
A current flows through the two-dimensional electron gas layer 22. At this time, by applying a voltage to the gate electrode 19, the concentration of the two-dimensional electron gas under the gate changes, so that a transistor operation can be performed.

Next, the main steps in manufacturing the high electron mobility transistor shown in FIG. 1 will be described with reference to FIGS.
(h) is described.

That is, in this case, for example, InP
First, a non-doped InP semiconductor layer (for example, a carrier concentration of 10 ¹⁵ c
m ^-3 , thickness 0.2 μm) 12, non-doped high purity InG
aAs semiconductor layer (for example, carrier concentration of 10 ¹⁵ cm ^-3 ,
Thickness 0.03 μm) 13, Non-doped high purity InAlA
s semiconductor layer (for example, carrier concentration 10 ¹⁵ cm ⁻³ , thickness 0.005 μm) 14, n-type semiconductor layer (for example, silicon planar doped 10 ¹² cm ⁻² ) 15, non-doped high-purity InAlAs semiconductor layer (for example, carrier) Concentration 10 ¹⁵
cm ^-3 , thickness 0.02 μm) 16, non-doped high purity I
An nP semiconductor layer (for example, a carrier concentration of 10 ¹⁵ cm ⁻³ and a thickness of 0.005 μm) 23, an n-type InAlAs semiconductor layer (for example, a carrier concentration of 10 ¹⁵ cm ⁻³ and a thickness of 0.02 μm)
m) 17, and n-type InGaAs semiconductor layer (for example,
Crystals 18 each having a carrier concentration of 10 ¹⁵ cm ⁻³ and a thickness of 0.01 μm are sequentially grown and laminated (see FIG. 2A). In addition, as a crystal growth means for laminating these layers, for example, a growth method such as an MBE method (molecular beam epitaxy) or a MOCVD method (metal organic material method) can be used.

Using a photoresist (not shown) as a mask, isolation is performed by mesa etching (mesa etching portion 25) from the uppermost n-type InGaAs semiconductor layer 18 side to the semi-insulating InP substrate 11. After that (see FIG. 2B), the uppermost n-type I
A source electrode 20 and a drain electrode 21 are formed on the nGaAs semiconductor layer 18 so as to face each other at a predetermined interval (FIG. 2).
(c)).

Next, each layer on the semi-insulating InP substrate 11 is covered with a photoresist, and this is patterned (resist pattern 26a) to open a recess window 27a (see FIG. 2D). Using the resist pattern 26a as a mask, the n-type InGaAs semiconductor layer 18 and the n-type InAlAs semiconductor layer 17 are selectively wet-etched by the first etching with a corresponding selective etching solution to form the recess groove portion 28. Then, the corresponding non-doped high-purity InP semiconductor layer 23 is partially exposed (see FIG. 2E). The selective etching solution used here is the respective semiconductor layers 18 and 17.
These can be selectively removed in accordance with
An etchant suitable for the layer 3 to act as an etching stopper layer, for example, a sulfuric acid-based or citric acid-based etchant can be used.

Subsequently, similarly, the recess groove portion 2 is formed.
Each layer on the semi-insulating InP substrate 11 including the side surface of No. 8 is covered with a photoresist, and is patterned (resist pattern 26b) to open an etching window 27b, and using the resist pattern 26b as a mask, Again, a second etch with the appropriate selective etchant
This time, the non-doped high-purity InP semiconductor layer 23 previously used as an etching stopper layer is selectively wet-etched to form a removed portion 29, and the corresponding non-doped high-purity InAlAs semiconductor layer 16 is partially exposed. (See FIG. 2 (f)). The selective etching liquid used here is also the semiconductor layer 23.
An etchant suitable for selectively removing this, for example, a hydrochloric acid-based etchant can be used. In the recess structure thus formed,
Excellent reproducibility.

Subsequently, after depositing a gate metal thereon, the gate electrode 19 is selectively formed on the non-doped high-purity InAlAs semiconductor layer 16 which is partially exposed by lift-off (see FIG. 2 (g)). 2), an insulating film 24 is further formed on the exposed surface of each semiconductor layer other than each electrode portion (see FIG. 2 (h)), so that stable insulation can be achieved and reliability is improved. Thus, the high electron mobility transistor having the recess structure shown in FIG. 1 can be configured as expected.

FIG. 3 shows the relationship between the current value and the etching time when recess etching is performed with a sulfuric acid-based etching solution while measuring the current value flowing between the source electrode 20 and the drain electrode 21. Are plotted in comparison with the conventional example. In the figure, sample A shows the characteristics of this embodiment (FIGS. 1 and 2), and sample B shows the characteristics of the conventional example (FIG. 6). It is.

That is, as is apparent from FIG.
In the A sample and the B sample, the current between the source and the drain gradually decreases as the etching time elapses. However, after the elapse of a certain etching time, in the case of the conventional B sample, the etching time (several seconds) is obtained. In the case of the sample A in this embodiment, a certain etching time is required even if the current value is greatly reduced and the recess depth is very difficult to control. After that,
It can be seen that the current is kept at a substantially constant value, and thereafter it does not change even if the etching time becomes long.
The reason for this is that, in the case of the A sample, after the n-type InGaAs semiconductor layer 18 and the n-type InAlAs semiconductor layer 17 are recess-etched, the non-doped high-purity InP semiconductor layer 23 effectively acts as an etching stop layer. As a result, in this embodiment, good selective etching is performed. Therefore, in the case of the structure of this embodiment, even if the etching conditions such as the etching rate and the etching time are not precisely controlled, a high electron mobility transistor having a recess structure with good reproducibility and excellent uniformity can be obtained. You get it. Note that the thickness of the non-doped high-purity InP semiconductor layer 23 as an etching stop layer here is, for example,
It was confirmed that a sufficient function could be achieved even with a thickness of about 0.002 μm.

Further, in the embodiment shown in FIG. 1, the gate electrode 19 is made of a non-doped high-purity InAlAs semiconductor layer 1.
6, only the n-type InGaAs semiconductor layer 18 and the n-type InAlAs semiconductor layer 17 are recess-etched to form the gate electrode 1 as shown in FIG.
Even when 9 is selectively formed on the non-doped high-purity InP semiconductor layer 23, almost the same function and effect can be obtained.

[0031]

As described in detail in each embodiment, according to the present invention, required first, second, third, and eighth semiconductor layers are stacked, and the eighth, seventh, and sixth semiconductor layers are formed. By selectively removing each semiconductor layer to expose the fifth semiconductor layer, a recess structure is selectively formed on each of the eighth, seventh, sixth, and fifth semiconductor layers. Alternatively, the eighth and seventh semiconductor layers are selectively removed to remove the sixth and seventh semiconductor layers.
By exposing the semiconductor layer, the recess structure is selectively formed on the surface of each of the eighth, seventh, and sixth semiconductor layers. It can be formed with good reproducibility, and
A first electrode is selectively formed on the exposed fifth semiconductor layer or the sixth semiconductor layer in the recess structure, and is formed on the opposing eighth semiconductor layer outside the recess structure. After selectively forming the second and third electrodes with the first electrode interposed therebetween, at least the eighth, seventh, and sixth semiconductors corresponding to the recess structure other than the respective electrode portions are formed. Since the surface portion of the layer is covered with the surface protective film, stable and good insulation of each semiconductor layer, particularly the sixth semiconductor layer, in the recess structure can be obtained. There are excellent features such as the reliability of the device can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a schematic configuration of a high electron mobility transistor having a recess structure to which an embodiment of the present invention is applied.

FIGS. 2 (a) to 2 (h) are cross-sectional views schematically showing main steps in manufacturing the high electron mobility transistor in the same manner.

FIG. 3 is a graph illustrating an operation in recess etching according to the first embodiment;

FIG. 4 is a cross-sectional view schematically showing a schematic configuration of a high electron mobility transistor having a recess structure to which another embodiment of the present invention is applied.

FIG. 5 is a cross-sectional view schematically showing a basic schematic configuration of a high electron mobility transistor having a recess structure in a conventional example.

FIG. 6 is a cross-sectional view schematically showing a basic schematic configuration of a high electron mobility transistor having a recess structure in another conventional example.

[Explanation of symbols]

Reference Signs List 11 semi-insulating InP substrate 12 non-doped high-purity InP semiconductor layer (first semiconductor layer, buffer layer) 13 non-doped high-purity InGaAs semiconductor layer (second semiconductor layer, electron transit layer) 14 non-doped high-purity InAlAs semiconductor layer (first 3 n-type semiconductor layer (fourth semiconductor layer, carrier supply layer) 16 non-doped high-purity InAlAs semiconductor layer (fifth semiconductor layer) 17 n-type InAlAs semiconductor layer (seventh semiconductor layer) Layer) 18 n-type InGaAs semiconductor layer (eighth semiconductor layer) 19 Schottky electrode (first electrode, gate electrode) 20 ohmic electrode (second electrode, source electrode) 21 ohmic electrode (third electrode, drain electrode) 22) two-dimensional electron gas layer 23 non-doped high-purity InP semiconductor layer (sixth semiconductor layer, etching stock) 24 Insulating film 25 Mesa etched portion 26a, 26b Resist pattern 27a Recess window 27b Etching window 28 Recess groove portion 29 Removed portion

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takanori Enoki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Yuji Akatsu 1-6-1 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (56) References JP-A-63-204662 (JP, A) JP-A-1-117069 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 29/778 H01L 29/80-29/812

Claims (2)

(57) [Claims] A first semiconductor layer, a second semiconductor layer, an electron transit layer, and a third semiconductor having a bandgap energy higher than that of the second semiconductor layer. Spacer layer, a carrier supply layer made of a fourth semiconductor layer doped with one conductivity type impurity, a fifth semiconductor layer made of a semiconductor similar to the third semiconductor layer, a second semiconductor layer and a fourth semiconductor layer made of a semiconductor similar to the third semiconductor layer. An etching stop layer made of a sixth semiconductor layer having a band gap energy between the third semiconductor layer and a seventh semiconductor layer made of a semiconductor layer doped with an impurity of the same conductivity type in the third semiconductor layer.
And a second semiconductor layer and an eighth semiconductor layer composed of a semiconductor layer doped with an impurity of the same conductivity type on the second semiconductor layer, wherein the eighth, seventh and sixth semiconductor layers are sequentially stacked . Each semiconductor layer is connected to the fifth half.
Formed by selective etching and removal until conductor layer is exposed
A first electrode on a fifth semiconductor layer inside the recess structure, and a first electrode on an opposing eighth semiconductor layer outside the recess structure. And the second and third electrodes are selectively formed, respectively. Further, at least the eighth and third electrodes other than these electrode portions are formed.
A high electron mobility transistor wherein a surface protective film is formed on the surface of each of the seventh and sixth semiconductor layers. 2. A semiconductor device comprising: a buffer layer comprising a first semiconductor layer; an electron transit layer comprising a second semiconductor layer; and a third semiconductor having a bandgap energy larger than that of the second semiconductor layer. Spacer layer, a carrier supply layer made of a fourth semiconductor layer doped with one conductivity type impurity, a fifth semiconductor layer made of a semiconductor similar to the third semiconductor layer, a second semiconductor layer and a fourth semiconductor layer made of a semiconductor similar to the third semiconductor layer. An etching stop layer made of a sixth semiconductor layer having a band gap energy between the third semiconductor layer and a seventh semiconductor layer made of a semiconductor layer doped with an impurity of the same conductivity type in the third semiconductor layer.
And a second semiconductor layer and an eighth semiconductor layer comprising a semiconductor layer doped with an impurity of the same conductivity type on the second semiconductor layer. The sixth semiconductor layer
Was formed by etching selectively until was exposed
A recess having a recess structure, wherein the first electrode is sandwiched between the sixth semiconductor layer inside the recess structure and the opposing eighth semiconductor layer outside the recess structure; To selectively form the second and third electrodes respectively. Further, at least the eighth and third electrodes other than these electrode portions are formed.
A high electron mobility transistor, wherein a surface protection film is formed on the surface of each of the seventh and sixth semiconductor layers.