JPH02191345A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field-effect transistor having high uniformity and high performance by a method wherein a semiconductor layer different from the surface semiconductor layer of a wafer is selectively built up on the wafer surface on both the sides of a temporary gate electrode and, after a recess is formed in the semiconductor layer from which the temporary gate electrode is removed, a gate electrode, a source electrode and a drain electrode are formed simultaneously. CONSTITUTION:A high purity GaAs layer 2, an Si-doped N-type AlGaAs layer 3 and an Si-doped N-type GaAs layer 4 are successively built up on a semi- insulating GaAs substrate 1. On a wafer prepared like this, a temporary gate electrode 9 is formed by dry etching. After that, AlGaAs layer 10 are formed on both sides of the temporary gate electrode 9 by selective epitaxial growth. After the temporary gate electrode 9 is removed, a gate recess 11 is formed by dry etching. After that, TiAu is applied by self-alignment deposition to provide a gate metal which forms non-alloy ohmic contact with the high impurity concentration GaAs layer 4. A FET is thus completed by forming a gate electrode 7, a source electrode 5 and a drain electrode 6 simultaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor using a heterojunction.

[Conventional technology]

As an example of conventional technology, GaAS and Aj? The case of a GaAs heterojunction will be explained. GaAS and Aj'GaA
A field effect transistor using a heterojunction of s (hereinafter referred to as F
ET) is an FET (ME
It is considered to be a faster and more efficient device than SFET (SFET), and is applied to low-noise devices and high-speed ICs.

To improve the performance of FET0, it is essential to form a fine gate electrode and reduce source resistance. In order to reduce the source resistance, as shown in FIG. 2(a), a recessed structure is adopted in which the gate portion is dug and the source/drain regions are formed on the side surfaces of the gate electrode 7. Regarding the formation of fine gate electrodes, gate electrodes of 0.3 to 0.4 μm have recently been formed using electron beam (hereinafter referred to as EB) straight grooves. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a high-purity GaAs layer, 3 is an N-type Al1GaAS layer,
4 is an N-type GaAs layer, 5 is a source electrode, and 6 is a drain electrode.

FETs having such a structure are basically manufactured through the following steps. FIGS. 2(b) to 2(d) show cross-sectional views of the device, and the steps will be explained.

First, as shown in FIG. 2(b), high-purity G was deposited on a high-resistance GaAs substrate 1 by molecular beam epitaxy (MBE).
aAs layer 2. An N-type AlGaAs layer 3 and an N-type GaAS layer 4 are formed. Here, high purity Ga As Ji!
2 is a channel layer, N-type AlGaAsN3 is a carrier supply layer, and N-type GaAs'ffJ 4 is a camp layer for reducing source resistance.

Next, device isolation is performed by mesa etching or B'' ion implantation.Next, as shown in FIG. 2(c), ohmic electrodes of a source electrode 5 and a drain electrode 6 are formed at a predetermined interval. Subsequently, as shown in FIG. 2(d), a resist N8 is formed to leave an opening at a desired position in the so-called channel region between the source electrode 5 and the drain electrode 6, and to cover the rest. As shown in FIG. 2(a), after forming a concave portion, a so-called recess region, in the semiconductor N4 using a resist as a mask, T is formed using a well-known vacuum evaporation method.
A gate electrode material such as i/A u is deposited, and then a lift-off method is applied to obtain a recessed gate structure in which a Schottky barrier gate electrode 7 is selectively formed within the recess.

[Problem to be solved by the invention]

In the above manufacturing method, the recesses are opened using a phosphoric acid-based etching solution that does not have selectivity between AJGaAS and GaAS, resulting in large variations in the threshold voltage and characteristics of the devices and poor uniformity within the wafer surface. Very bad.

On the other hand, AI as shown in Figure 3! It is also conceivable to form the recess opening by dry etching using a CCl t F z + He type gas which has a high selectivity between GaAs and GaAs. In this case, the depth of the recess is A
j? It stops at the GaAS layer, and high uniformity is expected. However, since the resist for EB exposure does not have dry etch resistance, dry etching cannot be used even if a thin gate is to be formed by EB exposure. Further, even if a gate is formed using an optical exposure resist having dry etching resistance, a gate having a length of 0.3 to 0.4 .mu.m cannot be formed.

An object of the present invention is to overcome the performance limitations of the conventional techniques as described above and to provide a method for manufacturing highly uniform and high-performance field effect transistors.

[Means to solve the problem]

A method for manufacturing a field effect transistor according to the present invention includes: forming a wafer by stacking different types of semiconductor materials; forming a temporary gate electrode on the wafer; and wafers on both sides of the temporary gate electrode. a step of selectively laminating a semiconductor layer different from the semiconductor layer on the surface on the surface; a step of removing the temporary gate electrode and selectively etching the semiconductor layer in the removed gate region;
The method is characterized in that it includes a step of simultaneously forming a source electrode and a drain electrode.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. 1st
The figure is a schematic cross-sectional view for explaining one embodiment of the present invention.

This element is manufactured as follows. First, as shown in FIG. 1(a), M
High-purity GaAs that becomes the channel layer using BE method
N2 to 1 μm, then Si-doped N-type AllG with an impurity concentration of 2XIO"cm-' to form a carrier supply layer.
200 layers of aAs layer 3 are grown, and then 2000 layers of SL-doped N-type GaAs layer 4 with an impurity concentration of IXIO''cm-' are grown as a camp layer.Using the wafer thus formed, B'' is grown as a device isolation layer. 100k e V,
Ion implantation is performed with l xlQ"cm-".

Next, a 5i02 film was deposited on the entire surface of the wafer for 20 minutes using the CVD method.
After 0.000 µm deposition, dry etching is performed using SF6 gas using the resist as a mask to form a temporary gate electrode 9 having a length of 0.3 μm, as shown in FIG. 1(b). Thereafter, as shown in FIG. 1(C), by selective epitaxial growth of the GaAs layer and SiO□ of the temporary gate electrode, AI!
Fifty layers of GaAsJilO are grown and laminated on both sides of the temporary gate electrode 9.

Next, after removing the temporary gate electrode 9 with HF or the like, CCβz
Fz+l (dry etching using e-based gas,
A gate recess 11 is formed as shown in FIG. 1(d). As explained in FIG. 3, C(ltF, +He
Depending on the gas in the system, GaAs and Aj! GaAs can be selectively dry etched.

Therefore, only the region of GaAsJ 14 from which temporary gate electrode 9 has been removed is dug.

Thereafter, as shown in FIG. 1(6), Ti/Au, which becomes the gate metal and is non-alloyohmic with the high-concentration GaAS layer 4, is deposited in a self-line manner to form the gate electrode 7. Source electrode5. A drain electrode 6 is formed at the same time to complete the device.

In FETs fabricated in this manner, selective dry etching is used to form recesses, so the threshold voltage and device characteristics within the wafer surface are very uniform, and the gate length is Since it is determined by the length of the gate electrode, a fine gate of 0.3 to 0.4 μm, which is comparable to EB exposure, was formed, and a high-performance device was realized.

The above embodiment uses high-purity GaAs and N-type Aj! We have described the case of a GaAS junction field effect transistor.
High-purity AIGaAS layer on A sJi, this high-purity A
A field effect transistor having a junction of N-type GaAs and high-purity Δ1GaAs, in which three N-type GaA layers are laminated on a 1GaAs layer, is manufactured in the same manner. Furthermore, field effect transistors using other different materials can also be manufactured in the same way using gases with selectivity.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a high performance and highly uniform field effect transistor with a fine gate and selective dry etching.

[Brief explanation of the drawing]

1(a) to (e) are sectional views of an element for explaining the present invention in detail; FIGS. 2(a) to 2(d) are sectional views of an element for explaining a conventional example; The figure shows the etching rate of CC1zFt+He system. 1... Semi-insulating GaAs substrate 2... High purity GaAsM 3... N-type AlGaAs layer 4... N-type GaAs layer 5... Source electrode 6. ... Drain electrode 7 ... Gate electrode 8 ... Resist 9 ... SiO□ Temporary gate electrode 10 ... Regrown ArGaAs layer 11 ... Gate recess ( G) (b) Agent Patent attorney Yoshiyuki Iwasa (C) Fig. 1 (d) (ei) Fig. 1 Fig. 2 (C) Fig. 2 Era child I: J time (sec) Fig. 3

Claims (1)

[Claims] (1) forming a wafer by stacking different types of semiconductor materials; forming a temporary gate electrode on the wafer; a step of selectively stacking a semiconductor layer; a step of removing the temporary gate electrode and selectively etching the semiconductor layer in the removed gate region;
A method for manufacturing a field effect transistor, comprising the step of simultaneously forming a source electrode and a drain electrode.