JPH02191344A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain a field-effect transistor having high uniformity and high performance by a method wherein, after ions are implanted by using a temporary gate electrode as a mask, the temporary gate electrode is removed and, after a recess is formed in the removed gate region, a gate electrode, a source electrode and a drain electrode are formed simultaneously. CONSTITUTION:A high purity GaAs channel layer 2, an Si-doped N-type AlGaAs carrier supply layer 3 and an Si-doped N-type GaAs layer 4 successively built up on a semi-insulating GaAs substrate 1. On a wafer prepared like this, a temporary gate electrode 9 is formed by dry etching. After that, Al<+> ions are implanted by using the temporary gate 9 as a mask. After the temporary gate 9 is removed, a gate recess 11 is formed by dry etching. Then Au is evaporated in a self-alignment manner to form a gate electrode 7, a source electrode 5 and a drain electrode 6 simultaneously and a device is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor using a heterojunction.

[Conventional technology]

As an example of the prior art, a case of heterojunction of GaAs and Aj2GaAs will be described. GaAs and Aj! GaA
A field effect transistor using a heterojunction of s (hereinafter referred to as F
ET) is an FET (ME
It is considered to be a faster and more efficient device than SFET (SFET), and is applied to low-noise devices and high-speed ICs.

To improve the performance of FET0, it is essential to form a fine gate electrode and reduce source resistance. In order to reduce the source resistance, as shown in FIG. 2(a), a recessed structure is adopted in which the gate portion is dug and the source/drain regions are formed on the side surfaces of the gate electrode 7. Regarding the formation of fine gate electrodes, gate electrodes of 0.3 to 0.4 μm have recently been formed using electron beam (hereinafter referred to as EB) straight grooves. In the figure, l is a semi-insulating GaAs substrate, 2 is a high-purity GaAs layer, 3 is an N-type AIGaAS layer, and 4 is a semi-insulating GaAs substrate.
is an N-type GaAs layer, 5 is a source electrode, and 6 is a drain electrode.

FETs having such a structure are basically manufactured through the following steps. FIGS. 2(b) to 2(d) show cross-sectional views of the device, and the steps will be explained.

First, as shown in FIG. 2(b), high-purity G was deposited on a high-resistance GaAs substrate 1 by molecular beam epitaxy (MBE).
aAs layer 2. N type Aj! GaAs layer 3, N-type GaAs
Form layer 4. Here, the high-purity GaAs layer 2 is a channel layer, the N-type AffiGaAs layer 3 is a carrier supply layer, and the N-type AffiGaAs layer 3 is a carrier supply layer.
The type G a SMA 4 is a cap layer for reducing source resistance.

Next, element isolation is performed by mesa etching or B ion implantation. Next, as shown in FIG. 2(C), ohmic electrodes of the source electrode 5 and the drain electrode 8i6 are formed at predetermined intervals. Subsequently, as shown in FIG. 2(d), a resist N8 is formed to leave an opening at a desired position in the so-called channel region between the source electrode 5 and the drain electrode 6, and to cover the rest. Next, as shown in FIG. 2(a), a concave portion, a so-called recess region, is formed in the semiconductor layer 4 using a resist as a mask, and then T
A gate electrode material such as i/Au is deposited, and then a lift-off method is applied to selectively form a Schittky barrier gate electrode 7 in the recess or obtain a recess gate structure.

[Problem to be solved by the invention]

In the above manufacturing method, the recess is 1. Since the openings are made using a phosphoric acid-based etching solution that does not have selectivity between GaAs and GaAs, the threshold voltage and characteristics of the devices vary widely and the uniformity within the wafer surface is very poor.

On the other hand, as shown in FIG. 3, CG 12 F has a high selection ratio between AlGaAs and GaAs! A method of forming the recess opening by dry etching using + He type gas is also considered. In this case, the recess should be dug with Al.
It stops at the GaAs layer, and high uniformity is expected. However, since the resist for EB exposure does not have dry etching resistance, dry etching cannot be used even if an attempt is made to form a fine gate using EBn light. Furthermore, even if gate formation is performed using an optical exposure resist that has dry etching resistance, 0.
A gate with a length of 3 to 0.4 μm is not possible.

An object of the present invention is to overcome the performance limitations of the conventional techniques as described above and to provide a method for manufacturing highly uniform and high-performance field effect transistors.

[Means to solve the problem]

A method for manufacturing a field effect transistor according to the present invention includes: forming a wafer by stacking different types of semiconductor materials; forming a temporary gate electrode on the wafer; and implanting ions using the temporary gate electrode as a mask. a step of removing the temporary gate electrode and selectively etching the semiconductor layer in the removed gate region;
The method is characterized in that it includes a step of simultaneously forming a source electrode and a drain electrode.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. 1st
The figure is a schematic cross-sectional view for explaining one embodiment of the present invention.

This element is manufactured as follows. First, as shown in FIG. 1(a), M is placed on a semi-insulating GaAs substrate 1.
A high purity GaAs layer 2 that will become a channel layer is formed using the BE method.
μm, then the impurity concentration 2xlO which becomes the carrier supply layer
20cm-3 St-doped N-type AlGaAs layer 3
0, then the impurity concentration I XIO”c as a cap layer
2000 m-3 Si-doped N-type GaAs layers 4 are grown. Using the wafer thus formed, B' is ion-implanted at 100 keV and IXIOI 4 cm-2 for element isolation.

Next, a 20% SiO
After depositing the resist, dry etching is performed using SF and gas using the resist as a mask to form a temporary gate electrode 9 having a length of 0.3 μm as shown in FIG. 1(b). Thereafter, as shown in FIG. 1(c), ions of ``Al'' are implanted using the temporary gate electrode 9 as a mask at a depth of 30 keys and a thickness of 1012 cm-1.

Next, after removing the temporary gate electrode 9 with HF or the like, CCl
tF! + Dry etching is performed using a He-based gas to form a gate recess 11 as shown in FIG. 1(d). In the figure, numeral 10 indicates a GaAs layer into which Al ions have been implanted.

At this time, CCj! z F z + l (GaAs and AlGaAs can be selectively dry etched using e-based gas. The principle is that AI is CC12F t f
It reacts with He-based gas to generate /lF3, which acts as an etching stop layer. Therefore, the ion-implanted layer 10 of Aj2'' is not etched like AlGaAs. Therefore, the Ga layer 10 from which the temporary gate electrode 9 has been removed
Only the region of the As layer 4 is dug.

Thereafter, as shown in FIG. 1(e), Ti/Au, which becomes the gate metal and is non-alloyohmic with the high-concentration GaAs layer 4, is deposited in a self-line manner to form the gate electrode 7. Source electrode5. A drain electrode 6 is formed at the same time to complete the device.

In FETs fabricated in this manner, selective dry etching is used to form recesses, so the threshold voltage and device characteristics within the wafer surface are very uniform, and the gate length is Since it is determined by the length of the gate electrode, a fine gate of 0.3 to 0.4 μm, which is comparable to EB exposure, was formed, and a high-performance device was realized.

The above embodiment describes the case of a field effect transistor with a junction of high purity GaAs and N-type A#GaAS.
A high-purity AlGaAs layer on the s-layer, this high-purity AlGaA
N-type GaA with N-type GaAsN stacked on sJi
A field effect transistor having a junction of S and high-purity AlGaAs is manufactured in the same manner. Furthermore, field effect transistors using other different materials can also be manufactured in the same way using gases with selectivity.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a high performance and highly uniform field effect transistor with a fine gate and selective dry etching.

[Brief explanation of the drawing]

1(a) to (e) are sectional views of an element for explaining the present invention in detail; FIGS. 2(a) to 2(d) are sectional views of an element for explaining a conventional example; The figure is CCj! 2 is a diagram showing the etching rate of 2F, +He system. 1... Semi-insulating GaAs substrate 2... High purity GaAs layer 3 --- N-type AlGaAs layer 4... N-type GaAs layer 5... Source electrode 6 ...Drain electrode 7 ...Gate electrode 8 ...Resist 9 ...Sin, temporary gate electrode 10 ...GaAs layer 11 ion-implanted with Al'''' ...Gate recess (G) (b) Agent Patent attorney Yoshiyuki Iwasa (C) Figure 1 (d) (e) Figure 1 (d) Figure 2 (C) Figure 2 Elatin σ time (sec) Figure 3

Claims (1)

[Claims] (1) forming a wafer by stacking different types of semiconductor materials; forming a temporary gate electrode on the wafer; implanting ions using the temporary gate electrode as a mask; and the temporary gate. a step of removing the electrode and selectively etching the semiconductor layer in the removed gate region;
A method for manufacturing a field effect transistor, comprising the step of simultaneously forming a source electrode and a drain electrode.