JP3295897B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a multi-device having two or more emitters.
The present invention relates to an emitter transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Recently, demands for higher speed and higher integration of semiconductor devices have been increasing. Response e <br/> because this requirement, HET using a high-speed hot electrons as carriers (Hot Electron Transistor; hot electron transistor) has been proposed. Furthermore, this HE
A so-called ME-HET (multi-emitter type HET) which uses two or more T emitter portions and does not use a base electrode has been proposed (see Japanese Patent Application Laid-Open No. 4-96274). became.

FIG. 13 is a sectional view showing the structure of a conventional ME-HET. For example, on a semi-insulating InP substrate 60, n-In
A GaAs collector layer 62 is formed, and the n-InGa
An n-InGaAs base layer 6 is formed on the As collector layer 62 via an i-InAIGaAs collector barrier layer 64.
6 are formed. On the n-InGaAs base layer 66, an i-InAlAs emitter barrier layer 6 is formed.
8, n-InGaAs emitter layers 70a, 70
b is formed in the shape of two islands.

Further, the n-InGaAs emitter layer 70
a and 70b on the emitter electrodes 72a and 72b, respectively.
b is formed, and a collector electrode 74 is formed on the n-InGaAs collector layer 62.

[0005]

However, in the above-mentioned conventional ME-HET, similar to the ordinary HET,
It is required to make the base layer thin. Also, ME-H
The ET has two or more emitter regions and features a structure in which the base electrode is not directly taken out of the base layer, so that the structure can be simplified and the circuit can be simplified.
Reduction of the parasitic resistance related to the base layer between the emitter electrodes has been a particular problem.

Here, it is possible to reduce the parasitic resistance by previously increasing the concentration or increasing the thickness of the base layer, but hot electrons injected into the base layer are liable to be scattered in the base. This method cannot be used because the current gain is greatly reduced. Accordingly, the present invention provides a semiconductor device of a multi-emitter type semiconductor device which reduces parasitic resistance relating to a base layer between emitter electrodes, enables high speed and low power consumption, and a method of manufacturing the same. Aim.

[0007]

The object of the present invention is to provide a collector comprising a first semiconductor layer; a base comprising a second semiconductor layer formed on the first semiconductor layer;
And a third semiconductor layer separated into two or more islands in the semiconductor device, wherein the emitter portion is formed on the third semiconductor layer and is separated into two or more islands. This is achieved by a semiconductor device having a low resistance region.

[0008] Also, a substrate, a collector layer formed on the substrate, a collector barrier layer formed on the collector layer, a base layer formed on the collector barrier layer, and a The formed emitter barrier layer, two or more island-shaped emitter layers formed on the emitter barrier layer, a collector electrode that forms an ohmic junction on the collector layer, and In a semiconductor device having two or more emitter electrodes each forming an ohmic junction, a low-resistance region is provided in or on the base layer between the two or more island-shaped emitter layers. This is achieved by a semiconductor device.

Also, a substrate, a collector layer formed on the substrate, a collector barrier layer formed on the collector layer, a base layer formed on the collector barrier layer, and a The formed emitter resonance tunnel barrier layer, two or more island-shaped emitter layers formed on the emitter resonance tunnel barrier layer, a collector electrode that forms an ohmic junction on the collector layer, and the two or more island-shaped Ohmic junction on emitter layer 2
In the semiconductor device having the above emitter electrode, a low resistance region is provided in or on the base layer between the two or more island-shaped emitter layers. You.

[0010] Also, a substrate, a collector contact layer formed on the substrate, a collector layer formed on the collector contact layer, a base layer formed on the collector layer, and a The formed emitter layer, two or more island-shaped emitter contact layers formed on the emitter layer, a collector electrode that forms an ohmic junction on the collector contact layer, and A semiconductor device having two or more emitter electrodes each in ohmic junction with
This is achieved by a semiconductor device having a low resistance region provided in or on the emitter layer between the two or more island-shaped emitter contact layers.

Further, in the above semiconductor device, the low resistance region is a metal alloy layer, which is achieved by a semiconductor device. In the above-described semiconductor device, the low-resistance region is a semiconductor layer having a low resistivity. In the above-described semiconductor device, the low-resistance region is a metal layer.

Further, the above object is to provide a collector layer, a collector barrier layer, a base layer, an emitter barrier layer,
And an emitter layer are sequentially grown, and on the emitter layer,
A first step of forming an emitter electrode layer, and after patterning the emitter electrode layer into a predetermined shape to form two or more emitter electrodes, selecting the emitter layer using the two or more emitter electrodes as a mask Etching
A second step of forming two or more island-shaped emitter layers, and forming a metal layer on the emitter barrier layer between the two or more island-shaped emitter layers using the two or more emitter electrodes as a mask; A third step of performing a heat treatment to form a metal alloy layer in the emitter barrier layer and the base layer below the metal layer; and mesa etching the emitter barrier layer, the base layer, and the collector barrier layer. And then forming a collector electrode on the exposed collector layer.

In the method of manufacturing a semiconductor device, instead of the third step, the emitter barrier layer is selectively etched using the two or more emitter electrodes as a mask, thereby forming the two or more islands. A step of exposing the base layer between the emitter layers, and selectively growing a low-resistivity semiconductor layer on the exposed base layer. You.

In the method of manufacturing a semiconductor device, instead of the third step, the emitter barrier layer is selectively etched using the two or more emitter electrodes as a mask, thereby forming the two or more islands. Forming a metal layer on the exposed base layer by ohmic contact using the two or more emitter electrodes as a mask after exposing the base layer between the emitter layers in a semiconductor shape. This is achieved by a method of manufacturing the device.

[0015]

According to the present invention, in a multi-emitter type semiconductor device, a low-resistance region formed of a metal alloy layer or a semiconductor layer having a low resistivity is provided between two or more island-shaped separated emitter portions. Thereby, the parasitic resistance of the base portion can be reduced. As a result, it is possible to further increase the speed and reduce the power consumption of the multi-emitter type semiconductor device, and to contribute to the high integration thereof.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the illustrated embodiments. FIG. 1 shows M according to a first embodiment of the present invention.
It is sectional drawing which shows E-HET. Semi-insulating InP substrate 1
0, a thickness of 300 nm and a Si doping amount of 1 × 10 ¹⁹ c
n-In _0.53 Ga _0.47 As collector layer 12 m ^-3 is formed on the n-In _0.53 Ga _0.47 As collector layer 12, a thickness of 200nm undoped i-In _0.52 (AI
An n-In _0.53 Ga _0.47 As base layer 16 having a thickness of 30 nm and a Si doping amount of 1 × 10 ¹⁸ cm ⁻³ is formed via a _0.8 Ga _0.5 ) _0.48 As collector barrier layer 14.

On the n-In _0.53 Ga _0.47 As base layer 16, a 5 nm-thick non-doped i-In
_0.52 Al _0.48 As n-I having a thickness of 200 nm and an Si doping amount of 1 × 10 ¹⁹ cm ⁻³ is interposed via the emitter barrier layer 18.
The n _0.53 Ga _0.47 As emitter layers 20a and 20b are formed in two islands. And these two n-In
I-I between _0.53 Ga _0.47 As emitter layers 20a and 20b
n _0.52 Al _0.48 As On the emitter barrier layer 18, a thickness of 3
A Pd / Ge metal layer 22 is formed by laminating a 0 nm Pd layer and a 40 nm thick Ge layer.
This embodiment is characterized in that a metal alloy layer 24 is formed in the i-In _0.52 Al _0.48 As emitter barrier layer 18 and the n-In _0.53 Ga _0.47 As base layer 16 under the metal layer 22. Note that a Pd / Zn metal layer may be used instead of the Pd / Ge metal layer 22.

On the n-In _0.53 Ga _0.47 As emitter layers 20a and 20b, a 400 nm-thick W
Si emitter electrodes 26a and 26b are formed. Further, on the n-In _0.53 Ga _0.47 As collector layer 12,
The Cr / Au collector electrode 28 is formed by laminating a 10 nm thick Cr layer and a 200 nm thick Au layer.

Next, the method for manufacturing the ME-HET shown in FIG.
This will be described with reference to the process sectional views shown in FIGS. On the semi-insulating InP substrate 10, a thickness of 300 nm and a Si doping amount of 1 × 10 ¹⁹ cm ⁻³ are formed by MBE or MOCVD.
N-In _0.53 Ga _0.47 As collector layer 12, thickness 20
0 nm undoped i-In _0.52 (AI _0.8 G
a _0.5 ) _0.48 As collector barrier layer 14, thickness 30 n
n-In _0.53 G with a doping amount of m and Si of 1 × 10 ¹⁸ cm ⁻³
a _0.47 As base layer 16, 5 nm thick non-doped i
-In _0.52 Al _0.48 As emitter barrier layer 18 and n- having a thickness of 200 nm and a Si doping amount of 1 × 10 ¹⁹ cm ⁻³ .
The In _0.53 Ga _0.47 As emitter layer 20 is epitaxially grown in order.

Subsequently, a 400 nm-thick film is formed on the n-In _0.53 Ga _0.47 As emitter layer 20 by sputtering.
Is formed (see FIG. 2A). Next, the WSi layer 26 is patterned into a predetermined shape by a photolithography technique, an RIE method using CF ₄ and O _2, and the two WSi emitter electrodes 26a and 26b are formed.
After forming the photoresist, the photoresist is removed (FIG. 2B).
reference).

Next, the WSi emitter electrodes 26a, 26
Using b as a mask, the n-In _0.53 Ga _0.47 As emitter layer 20 is etched using a mixed solution of citric acid, H ₂ O, and H ₂ O ₂ to form two island-shaped n-In _0.53 Ga _0.47 A.
The s emitter layers 20a and 20b are formed. At this time, since the citric acid-based etchant is used, the WSi emitter electrodes 26a and 26b and the n-In _0.53 Ga _0.47 As emitter layers 20a and 20b have a so-called T-shape. Further, the n-In _0.53 Ga _0.47 As emitter layer 20 is formed with respect to the i-In _0.52 Al _0.48 As emitter barrier layer 18.
Is selectively etched, this etching is
-In _0.52 Al _0.48 As can be stopped at the surface of the emitter barrier layer 18 (see FIG. 3C).

Next, using the WSi emitter electrodes 26a and 26b as a mask, a thickness of 30
A Pd layer having a thickness of 40 nm and a Ge layer having a thickness of 40 nm are sequentially deposited to form a Pd / Ge metal layer 22. This gives n
The Pd / Ge metal layer 22 is also formed on the i-In _0.52 Al _0.48 As emitter barrier layer 18 between the -In _0.53 Ga _0.47 As emitter layers 20a and 20b.

At this time, the WSi emitter electrode 26
a, 26b and n-In _0.53 Ga _0.47 As emitter layer 20
Since a and 20b have a T-shaped shape, n-In
Pd on the side surfaces of the _0.53 Ga _0.47 As emitter layers 20a and 20b
The / Ge metal layer does not adhere (see FIG. 3D). Then, heat treatment is performed at a temperature of 250 ° C. for 7 minutes.
Further, heat treatment is performed at a temperature of 350 ° C. for 30 seconds. By this heat treatment, i-In _0.52 Al under the Pd / Ge metal layer 22
_0.48 As emitter barrier layer 18 and n-In _0.53 Ga
_A metal alloy layer 24 is formed in the _0.47 As base layer 16.

At this time, Pd and n contained in the Pd / Ge metal layer 22 are first heat-treated at a temperature of 250 ° C.
-In _0.53 Ga _0.47 As forms a thin PdAs layer with As of the base layer 16, and further alloying does not proceed, so that the metal alloy layer 24 has a thin n-In _0.53 Ga _0.47.
It does not penetrate the As base layer 16 (FIG. 4E)
reference). Note that, instead of the Pd / Ge metal layer 22, Pd / Z
The same effect is obtained when an n metal layer is used.

Next, i-In_0.52Al_0.48As Emi
Ta barrier layer 18, n-In_0.53Ga _0.47As base layer 1
6, and i-In_0.52(AI_0.8Ga_0.5)_0.48Asko
The lector barrier layer 14 is mesa-etched to obtain n-In
_0.53Ga_0.47After exposing the As collector layer 12,
n-In_0.53Ga_0.47On the As collector layer 12, a thickness
A 10 nm Cr layer and a 200 nm thick Au layer are laminated.
The formed Cr / Au collector electrode 28 is formed. In this way
The ME-HET shown in FIG. 1 is completed (see FIG. 4 (f)).
See).

Thereafter, an interlayer insulating film 30 made of a SiO ₂ film, a SiON film or the like is formed on the entire surface (see FIG. 5G). Further, the interlayer insulating film 30 on the WSi emitter electrodes 26a and 26b is selectively removed by etching to open a contact hole.
T connected to the Si emitter electrodes 26a and 26b respectively
Ti / Pt / A in which an i layer, a Pt layer, and an Au layer are stacked
The u wiring layers 32a and 32b are formed (see FIG. 5H).

In the step shown in FIG.
The Pd / Ge metal layer 22 having a thickness of 70 nm was formed. However, since the Pd / Ge metal layer 22 is not used as an electrode, it is not necessary to increase the thickness. Conversely, as shown in FIG. 6, the thickness of the Pd / Ge metal layer 23 is
n-In _0.53 Ga _0.47 As emitter layers 20a, 20b,
Further, if the thickness becomes large enough to be flush with the WSi emitter electrodes 26a and 26b, a process problem occurs. That is, in the step of opening a contact hole in the interlayer insulating film 30 formed on the entire surface, the WSi emitter electrodes 26a, 26b
When the distance between them is very short, there is no room for alignment, and a contact hole is opened not only on the WSi emitter electrodes 26a and 26b but also on the Pd / Ge metal layer 23. The wiring layer formed via the short circuit is short-circuited. Therefore, in order to prevent such a problem, as shown in FIG. _3D , the n-In _0.53 Ga _0.47 As emitter layers 20a, 2
0b, the thickness of the Pd / Ge metal layer 22 is n-
It is necessary that the thickness of the In _0.53 Ga _0.47 As emitter layer 20a, 20b be sufficiently smaller than the thickness thereof.

Next, the operation of the ME-HET shown in FIG. 1 will be described. This is basically the same as the case of the conventional ME-HET. That is, one of the two WSi emitter electrodes 26a and 26b, for example, the WSi emitter electrode 26a
When a low voltage is applied, electrons are injected from the n-In _0.53 Ga _0.47 As emitter layer 20a to the n-In _0.53 Ga _0.47 As base layer 16 via the i-In _0.52 Al _0.48 As emitter barrier layer 18, For example, WSi emitter electrode 2
When a high voltage is applied to 6b, this WSi emitter electrode 26b functions as a base electrode, and n-In _0.53 Ga
_0.47 Electrons are extracted from the As base layer 16. Therefore, the potential difference between the two WSi emitter electrodes 26a, 26b is i-In _0.52 Al _0.48 As emitter barrier layer 18
Turns on when the sum of the rising voltages in the forward and reverse directions with respect to

As described above, according to the present embodiment, n-In
N-I between _0.53 Ga _0.47 As emitter layers 20a and 20b
n _0.53 Ga _0.47 As metal layer 24 in base layer 16
Is formed, the parasitic resistance of the base can be reduced. Specifically, n-In _0.53 Ga _0.47 A
s emitter layers 20a, 20b and i-In _0.52 Al _0.48 A
The junction area with the s emitter barrier layer 18, that is,
The base junction area is 2 × 2 μm ² and n-In _0.53 Ga
_0.47 As When the distance between the emitter layers 20a and 20b is 1 μm, the base resistance is 120Ω (the contact resistance of the emitter electrode is 20Ω, and the sheet resistance of the base is 100Ω).
It was about. This resistance value is 以下 or less as compared with a conventional ME-HET structure having a base resistance of about 270 Ω under the same conditions (a contact resistance of the emitter electrode is 20 Ω, and a sheet resistance of the base is 250 Ω). Has been reduced to

Therefore, the integrated circuit using the ME-HET according to the present embodiment can achieve higher speed and lower power consumption, and can contribute to higher integration. Next, an ME-HET according to a second embodiment of the present invention will be described with reference to FIG. FIG. 7 is a sectional view showing the ME-HET according to the present embodiment. The ME shown in FIG.
The same components as those of -HET are denoted by the same reference numerals, and description thereof is omitted.

The present embodiment is characterized in that a low-resistance semiconductor layer is used in place of the metal alloy layer 24 in the first embodiment. An n-In _0.53 Ga _0.47 As collector layer 12 is formed on the semi-insulating InP substrate 10, and an i-In _0.52 (AI _0.8 Ga _0.5 ) _0.48 As collector is formed on the n-In _0.53 Ga _0.47 As collector layer 12. through the barrier layer _{14, n-in 0.53 Ga 0.} 47 As the base layer 16 is formed. The n-In _0.53
On the Ga _0.47 As base layer 16, i-In _0.52 Al
_0.48 As via the emitter barrier layer 18, n-In _0.53
Ga _0.47 As emitter layers 20a and 20b are formed in two islands.

The two n-In _0.53 Ga _0.47
N-In _0.53 Ga between As emitter layers 20a and 20b
_{0.47 On the} As base layer 16, the Si doping amount is 1 × 10 ¹⁹
This embodiment is characterized in that an n ⁺ -InGaAs low resistance layer 34 of cm ⁻³ is formed. Note that this n ⁺ -InG
Instead of the aAs low resistance layer 34, for example, a high concentration n ⁺ −
It is also possible to use an InAs layer.

On the n-In _0.53 Ga _0.47 As emitter layers 20a and 20b, WSi emitter electrodes 26a and 26b are formed, respectively, and n-In _0.53 Ga _0.47
A Cr / Au collector electrode 2 is formed on the As collector layer 12.
8 are formed. Next, a method of manufacturing the ME-HET shown in FIG. 1 will be described with reference to process cross-sectional views shown in FIGS. Note that the same components as those of the ME-HET in FIGS. 2 to 5 are denoted by the same reference numerals, and description thereof will be omitted.

The process shown in FIGS. 2 (a) to 3 (c)
Similarly, on the semi-insulating InP substrate 10, n-I
n_0.53Ga_0.47As collector layer 12, i-In_0.52(A
I_{0. 8}Ga_0.5)_0.48As collector barrier layer 14, n-
In_0.53Ga_0.47As base layer 16, i-In_0.52Al
_0.48As emitter barrier layer 18 and n-In_0.53Ga
_0.47Epitaxial crystal growth of As emitter layer 20 in sequence
After that, this n-In _0.53Ga_0.47As emitter layer 20
A WSi layer 26 is formed thereon.

Subsequently, the WSi layer 26 is patterned into a predetermined shape to form two WSi emitter electrodes 26a, 26
b, the WSi emitter electrodes 26a, 2
6b as a mask, the n-In _0.53 Ga _0.47 As emitter layer 20 is etched, and the WSi emitter electrodes 26a, 26
Then, n-In _0.53 Ga _0.47 As emitter layers 20a and 20b having a T-shape with 6b are formed (see FIG. 8A).

Next, the WSi emitter electrodes 26a, 26
Using the b as a mask, the i-In _0.52 Al _0.48 As emitter barrier layer 18 is selectively etched by RIE using methane and hydrogen to expose the n-In _0.53 Ga _0.47 As base layer 16. Then, MOCVD method, MB
Using the WSi emitter electrode as a mask, the exposed n-In _0.53 Ga _0.47 As base layer 1 is formed by E method, ALE method or the like.
6, n ⁺ -In with an Si doping amount of 1 × 10 ¹⁹ cm ^−3.
The GaAs low resistance layer 34 is selectively regrown (FIG. 8).
(B)).

Next, i-In_0.52Al_0.48As Emi
Ta barrier layer 18, n-In_0.53Ga _0.47As base layer 1
6, and i-In_0.52(AI_0.8Ga_0.5)_0.48Asko
The lector barrier layer 14 is mesa-etched to obtain n-In
_0.53Ga_0.47After exposing the As collector layer 12,
n-In_0.53Ga_0.47Cr on the As collector layer 12
/ Au collector electrode 28 is formed. Thus shown in FIG.
The ME-HET is completed (see FIG. 9C).

Thereafter, an interlayer insulating film 30 is formed on the entire surface, and the WSi emitter electrode 26 is formed through contact holes opened on the WSi emitter electrodes 26a and 26b.
The Ti / Pt / Au wiring layers 32a and 32b connected to the a and 26b, respectively, are formed (see FIG. 9D). Note that n
N ⁺ formed on the In _0.53 Ga _0.47 As base layer 16
-The thickness of the InGaAs low resistance layer 34 is n-In _0.53 G
It is necessary that the thickness of the a _0.47 As emitter layers 20a and 20b be sufficiently smaller than the thickness of the As emitter layers 20a and 20b as in the case of the first embodiment described with reference to FIG. .

As described above, according to the present embodiment, n-In
N-I between _0.53 Ga _0.47 As emitter layers 20a and 20b
n ⁺ -InGaAs is formed on the n _0.53 Ga _0.47 As base layer 16.
Since the s low resistance layer 34 is formed, the parasitic resistance of the base can be reduced, and the same effect as in the first embodiment can be obtained. In the second embodiment, the selective growth method is used as the method of forming the n ⁺ -InGaAs low resistance layer 34, but a method of doping impurities may be used. Where n−I
Since the thickness of the n _0.53 Ga _0.47 As base layer 16 is extremely thin, that is, 30 nm, it is difficult to perform ion implantation using ordinary high energy, and a doping method using low energy and having high controllability is required.

Next, ME-ME according to the third embodiment of the present invention will be described.
HET will be described with reference to FIG. FIG. 10 is a sectional view showing the ME-HET according to the present embodiment. Note that the same components as those of the ME-HET in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. The present embodiment is characterized in that a metal layer is used instead of the n ⁺ -InGaAs low resistance layer 34 in the second embodiment.

On a semi-insulating InP substrate 10, n-In
_{A 0.53} Ga _0.47 As collector layer 12 is formed.
On the In _0.53 Ga _0.47 As collector layer 12, i-In
_0.52 (AI _0.8 Ga _0.5 ) _0.48 As collector barrier layer 1
4 _{through, n-In 0.53 Ga 0. 47} As the base layer 16 is formed. The n-In _0.53 Ga _0.47 As
On the base layer 16, n-In _0.53 Ga _0.47 As emitter layers 20 a and 20 b are formed in two islands via an i-In _0.52 Al _0.48 As emitter barrier layer 18.

The two n-In _0.53 Ga _0.47
N-In _0.53 Ga between As emitter layers 20a and 20b
On _0.47 As the base layer 16, there is a feature of this embodiment in that the AuGe / Au metal layer 35 and the AuGe layer and an Au layer are laminated is formed by ohmic contact. Incidentally, instead of the AuGe / Au metal layer 35, AuGe / N
A metal layer that forms an ohmic junction with the base layer, such as an i / Au metal layer, a Pd / Ge metal layer, or a Pd / Zn metal layer, may be used.

On the n-In _0.53 Ga _0.47 As emitter layers 20a and 20b, WSi emitter electrodes 26a and 26b are formed, respectively, and n-In _0.53 Ga _0.47
A Cr / Au collector electrode 2 is formed on the As collector layer 12.
8 are formed. Next, a method for manufacturing the ME-HET in FIG. 10 will be described. 8A, an n-In _0.53 layer is formed on the semi-insulating InP substrate 10.
Ga _0.47 As collector layer 12, i-In _0.52 (AI _0.8
Ga _0.5 ) _0.48 As collector barrier layer 14, n-In
_0.53 Ga _0.47 As base layer 16, i-In _0.52 Al _0.48
As emitter barrier layer 18 and n-In _0.53 Ga _0.47
After sequentially growing the As emitter layer 20, the n-In
_{On the 0.53} Ga _0.47 As emitter layer 20, two WSi emitter electrodes 26a and 26b are formed, and n-In _0.53 G is formed using these WSi emitter electrodes 26a and 26b as a mask.
a _0.47 As emitter layer 20 is etched to form a T-shaped n-In with WSi emitter electrodes 26a and 26b.
_{The 0.53} Ga _0.47 As emitter layers 20a and 20b are formed.

Next, the WSi emitter electrodes 26a, 26
By using b as a mask, the i-In _0.52 Al _0.48 As emitter barrier layer 18 is selectively etched to obtain n-In _0.53 G
exposing the a _{0. 47} As the base layer 16. Subsequently, the exposed n-In _0.53 Ga _0.47 As as in the second embodiment.
Instead of selectively regrowing the n ⁺ -InGaAs low resistance layer 34 on the base layer 16, an AuGe layer and an Au layer are sequentially deposited using the WSi emitter electrode as a mask, and n
An AuGe / Au metal layer 35 to be in ohmic contact with the -In _0.53 Ga _0.47 As base layer 16 is formed.

Next, i-In_0.52Al_0.48As Emi
Ta barrier layer 18, n-In_0.53Ga _0.47As base layer 1
6, and i-In_0.52(AI_0.8Ga_0.5)_0.48Asko
The lector barrier layer 14 is mesa-etched to obtain n-In
_0.53Ga_0.47After exposing the As collector layer 12,
n-In_0.53Ga_0.47Cr on the As collector layer 12
/ Au collector electrode 28 is formed. Thus in FIG.
The ME-HET shown is completed.

The n-In _0.53 Ga _0.47 As base layer 1
The thickness of the AuGe / Au metal layer 35 formed on the
The reason _why the thickness of the emitter layers 20a and 20b is required to be sufficiently smaller than the thickness of the -In _0.53 Ga _0.47 As
This is the same as the case described with reference to FIG. . Thus, according to the present embodiment, n-In _0.53 Ga
_0.47 n-In _0.53 G between As emitter layers 20a and 20b
a _0.47 AuGe / Au metal layer 35 on the As base layer 16
Is formed, the parasitic resistance of the base can be reduced, and the same effect as in the second embodiment can be obtained.

Next, the ME-ME according to the fourth embodiment of the present invention will be described.
The RHET (Resonant-tunneling HET) will be described with reference to FIG. FIG. 11 shows an ME-RHE according to this embodiment.
It is sectional drawing which shows T. Note that the same components as those of the ME-HET in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is characterized in that an RHET structure is used instead of the HET structure of the first embodiment. On a semi-insulating InP substrate 10, a 300 nm thick S
n-In _0.53 Ga _{0.47 with an} i doping amount of 1 × 10 ¹⁹ cm ⁻³
An As collector layer 12 is formed, and the n-In _0.53 Ga
_{On a 0.47} As collector layer 12, a non-doped i-In _0.52 (AI _0.8 Ga _0.5 ) _0.48 As collector barrier layer 14 having a thickness of 200 nm, a thickness of 30 nm and a Si doping amount of 1 × 10 ¹⁸ cm ⁻³ are provided. An n-In _0.53 Ga _0.47 As base layer 16 is formed.

On the n-In _0.53 Ga _0.47 As base layer 16, an i-InAlAs layer having a thickness of 3 nm, an i-InGaAs layer having a thickness of 3 nm, and an i-InGaAs layer having a thickness of 3 nm are provided.
An In Al As layer are sequentially stacked i-InAlAs / I
Through the nGaAs / In Al As emitter resonance tunnel barrier layer 36, the thickness is 200 nm and the Si doping amount is 1 ×.
10 ¹⁹ cm ⁻³ n-In _0.53 Ga _0.47 As emitter layer 2
0a and 20b are formed in the shape of two islands. That is, R
It has a HET structure.

The two n-In _0.53 Ga _0.47
I-In _0.52 Al between As emitter layers 20a and 20b
_0.48 As a 30 nm thick P on the As emitter barrier layer 18
Pd / Ge in which a d layer and a 40 nm thick Ge layer are laminated
A metal layer 22 is formed, and the Pd / Ge metal layer 22
A metal alloy layer 24 is formed in the lower i-In _0.52 Al _0.48 As emitter barrier layer 18 and the lower n-In _0.53 Ga _0.47 As base layer 16.

Further, n-In_0.53Ga_0.47As emitter
On each of the layers 20a and 20b, a 400 nm-thick W
Si emitter electrodes 26a and 26b are formed, and n-
In _0.53Ga_0.47On the As collector layer 12, a thickness of 10
nm Cr layer and 200 nm thick Au layer were laminated.
A Cr / Au collector electrode 28 is formed. In addition, this
The method for manufacturing the ME-RHET of FIG.
5 is almost the same as the method of manufacturing the ME-HET shown in FIG.
Therefore, the description is omitted.

As described above, according to this embodiment, n-In
N-I between _0.53 Ga _0.47 As emitter layers 20a and 20b
n _0.53 Ga _0.47 As metal layer 24 in base layer 16
Is formed, the parasitic resistance of the base can be reduced, and the same effect as in the case of the ME-HET according to the first embodiment can be achieved in the ME-RHET.

Although not shown, even when the n ⁺ -InGaAs low-resistance layer 34 in the second embodiment is formed instead of the metal alloy layer 24 in the present embodiment, the third embodiment The same effect can be obtained even when the AuGe / Au metal layer 35 in the example is formed. Next, the ME according to the fifth embodiment of the present invention will be described.
An HBT (Hetero-junction Bipolar Transistor) will be described with reference to FIG.

FIG. 12 is a sectional view showing an ME-HBT according to this embodiment. The present embodiment is characterized in that an HBT structure is used instead of the HET structure of the first to third embodiments and the RHET structure of the fourth embodiment. On a semi-insulating InP substrate 40, an n-InGaAs collector contact layer 42 having a thickness of 300 nm and a Si doping amount of 5 × 10 ¹⁸ cm ⁻³ is interposed, and has a thickness of 300 nm and a Si doping amount of 1 × 10 ¹⁷ cm ^{−. 3} n-InGaAs collector layer 4
4 are formed. The n-InGaAs collector layer 44 has a thickness of 50 nm and a Be doping amount of 5 × 10 ^18.
A p-InGaAs base layer 46 of cm ^-3 is formed.

The p-InGaAs base layer 46
On top, a thickness of 150 nm having a band gap larger than that of the p-InGaAs base layer 46,
An n-InAlAs emitter layer 48 having a Si doping amount of 5 × 10 ¹⁷ cm ⁻³ is formed. Also, this n-InA
On the lAs emitter layer 48, n-InGaAs emitter contact layers 50a and 50b having a thickness of 200 nm and a Si doping amount of 5 × 10 ¹⁹ cm ⁻³ are formed in two islands.

The n-InAlAs between these two n-InGaAs emitter contact layers 50a, 50b
On the emitter layer 48, a Pd layer having a thickness of 10 nm and a Pd layer having a thickness of 30 nm are formed.
A Pd / Zn metal layer 52 is formed by laminating a Zn layer with a thickness of 50 nm.
p-InGaAs base through lAs emitter layer 48
In the layer 46 , a thin metal alloy layer 54 having a depth of about 30 nm is provided.
The feature of the present embodiment lies in the fact that is formed. In addition, Pd
Instead of the / Zn metal layer 52, a Pd / Ge metal layer may be used.

On the n-InGaAs emitter contact layers 50a and 50b, a 10 nm-thick C
Cr / A in which an r layer and a 200 nm thick Au layer are laminated
u emitter electrodes 56a and 56b are formed. On the n-InGaAs collector contact layer 42, a Cr / Au collector electrode 58 in which a 10-nm thick Cr layer and a 200-nm thick Au layer are stacked is formed.

Next, a method of manufacturing the ME-HBT shown in FIG. 12 will be described. 300n thickness on semi-insulating InP substrate 40
n-InGaAs with a doping amount of m and Si of 5 × 10 ¹⁸ cm ⁻³
s collector contact layer 42, thickness 300 nm, n-InGaAs collector layer 44 having a Si doping amount of 1 × 10 ¹⁷ cm ⁻³ , thickness 50 nm, Be doping amount 5 × 10 ¹⁸ cm 3
^-3 p-InGaAs base layer 46, p-InGaAs
150 nm thick, having a band gap larger than the band gap of the base layer 46, and a Si doping amount of 5 × 10 ¹⁷
cm ⁻³ n-InAlAs emitter layer 48, thickness 200
nm, n-InGa with a Si doping amount of 5 × 10 ¹⁹ cm ⁻³
The As emitter contact layer 50 is epitaxially grown in order. Subsequently, on the n-InGaAs emitter contact layer 50, a Cr layer having a thickness of 10 nm and a
A Cr / Au layer is formed by laminating a 0 nm Au layer.

Next, the Cr / Au layer is patterned into a predetermined shape to form two Cr / Au emitter electrodes 56.
After the formation of the n-InGaAs emitter contact layers 50a and 50b, the n-InGaAs emitter contact layer 50 is etched using the rCr / Au emitter electrodes 56a and 56b as masks.
b is formed.

Next, these two n-InGaAs emitter contact layers 50a, 50b are formed by EB evaporation using the Cr / Au emitter electrodes 56a, 56b as a mask.
b on the n-InAlAs emitter layer 48 between
a Pd layer having a thickness of 30 nm and a Zn layer having a thickness of 30 nm in this order.
A Pd / Zn metal layer 52 is formed. Subsequently, the temperature 250
At 325 ° C. for 30 seconds to pass through the n-InAlAs emitter layer 48 under the Pd / Zn metal layer 52 to form p-InG
A thin metal alloy layer 54 having a depth of about 30 nm is formed in the aAs base layer 46 .

Next, the n-InAlAs emitter layer 4
8, p-InGaAs base layer 46, and n-InGa
The As collector layer 44 is mesa-etched to form n-InG
After exposing the aAs collector contact layer 42, a Cr / Au collector electrode 58 in which a 10 nm thick Cr layer and a 200 nm thick Au layer are laminated is formed on the n-InGaAs collector contact layer 42.

In the ME-HBT of FIG. 12 , when a positive bias is applied between the emitter and the base,
Electrons from the emitter reach the base layer. Here, the electrons that have reached the base layer reach the collector layer by diffusion and become a collector current. The operating principle is almost the same as ME-HET. As described above, according to the present embodiment, n−I
p between nGaAs emitter contact layers 50a and 50b
Since the metal alloy layer 54 is formed in the InGaAs base layer 46, the parasitic resistance of the base can be reduced, and the same effect as in the ME-HET according to the first embodiment can be obtained in the ME-HBT. Can be played.

Although not shown, even when the n ⁺ -InGaAs low-resistance layer 34 in the first embodiment is formed instead of the metal alloy layer 54 in the present embodiment, the third embodiment The same effect can be obtained even when the AuGe / Au metal layer 35 in the example is formed. It should be noted that the ME-HE according to the above first to fourth embodiments.
As materials for T, ME-RHET, and ME-HBT, in addition to those described above, for example, GaAs / AlGaAs
System, InAs / AlGaSbAS system, InGaAs / I
An nGaP system or the like is also possible, and the content of the present invention is not limited by the semiconductor material. Further, in each case, the case where the number of the emitters is two has been described. However, even when the number of the emitters is three or more, the basic structure of the semiconductor device and the manufacturing method thereof are the same.

[0064]

As described above, according to the present invention, there is provided a semiconductor device having a collector, a base connected to the collector, and two or more island-shaped emitters connected to the base. The provision of the low-resistance region between the two or more island-shaped emitter portions makes it possible to reduce the parasitic resistance of the base, which has conventionally been a problem in the multi-emitter type semiconductor device.

This makes it possible to further increase the speed and reduce the power consumption of the multi-emitter type semiconductor device.
It can also contribute to high integration.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an ME-HET according to a first embodiment of the present invention.

FIG. 2 is a process sectional view (part 1) for describing the method of manufacturing the ME-HET in FIG.

FIG. 3 is a process sectional view (part 2) for describing the method for manufacturing the ME-HET in FIG.

FIG. 4 is a process sectional view (part 3) for describing the method of manufacturing the ME-HET in FIG.

FIG. 5 is a process sectional view (part 4) for describing the method of manufacturing the ME-HET in FIG.

FIG. 6 is a process cross-sectional view for explaining the method of manufacturing the ME-HET in FIG.

FIG. 7 is a sectional view showing an ME-HET according to a second embodiment of the present invention.

FIG. 8 is a process sectional view (part 1) for describing the method of manufacturing the ME-HET in FIG.

FIG. 9 is a process sectional view (part 2) for describing the method for manufacturing the ME-HET in FIG.

FIG. 10 is a sectional view showing an ME-HET according to a third embodiment of the present invention.

FIG. 11 shows a ME-RHET according to a fourth embodiment of the present invention.
FIG.

FIG. 12 is a sectional view showing an ME-HBT according to a fifth embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a conventional ME-HET.

[Explanation of symbols]

10 ... semi-insulating InP substrate _{12 ... n-In 0.53 Ga 0.47} As collector layer _{14 ... i-In 0.52 (AI} 0.8 Ga 0.5) 0.48 As collector barrier layer _{16 ... n-In 0.53 Ga 0.47} As the base layer 18 ... i- In _0.52 Al _0.48 As emitter barrier layer 20, 20a, 20b ... n-In _0.53 Ga _0.47 As emitter layer 22 ... Pd / Ge metal layer 24 ... metal alloy layer 26 ... WSi layer 26a, 26b ... WSi emitter electrode 28 ... Cr / Au collector electrode 30 ... Interlayer insulating film 32a, 32b ... Ti / Pt / Au wiring layer 34 ... n ⁺ -InGaAs low resistance layer 35 ... AuGe / Au metal layer 36 ... i-InAlAs / InGaAs / InGaAs
Emitter resonance tunnel barrier layer 40 ... Semi-insulating InP substrate 42 ... n-InGaAs collector contact layer 44 ... n-InGaAs collector layer 46 ... p-InGaAs base layer 48 ... n-InAlAs emitter layers 50a, 50b ... n-InGaAs emitter contacts Layer 52: Pd / Zn metal layer 54: Metal alloy layer 56a, 56b: Cr / Au emitter electrode 58: Cr / Au collector electrode 60: Semi-insulating InP substrate 62: n-InGaAs collector layer 64: i-InAIGAAs collector barrier Layer 66: n-InGaAs base layer 68: i-InAlAs emitter barrier layer 70a, 70b: n-InGaAs emitter layer 72a, 72b: emitter electrode 74: collector electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/68 H01L 21/331 H01L 29/73-29/737 H01L 29/205

Claims (11)

(57) [Claims] A substrate; a collector layer formed on the substrate; a collector barrier layer formed on the collector layer; a base layer formed on the collector barrier layer; An emitter barrier layer formed,
Two or more island-shaped emitter layers formed on the emitter barrier layer, a collector electrode having an ohmic junction on the collector layer, and two or more emitters having an ohmic junction on each of the two or more island-shaped emitter layers A semiconductor device comprising a multi-emitter transistor having an electrode, wherein the base layer between the two or more island-shaped emitter layers is
A semiconductor device provided with a low resistance region. 2. A semiconductor device comprising: a substrate; a collector layer formed on the substrate; a collector barrier layer formed on the collector layer; a base layer formed on the collector barrier layer; An emitter barrier layer formed,
Two or more island-shaped emitter layers formed on the emitter barrier layer, a collector electrode having an ohmic junction on the collector layer, and two or more emitters having an ohmic junction on each of the two or more island-shaped emitter layers A multi-emitter transistor having an electrode, wherein a low-resistance region is provided in the emitter barrier layer and the base layer between the two or more island-shaped emitter layers. Semiconductor device. 3. A substrate, a collector layer formed on the substrate, a collector barrier layer formed on the collector layer, a base layer formed on the collector barrier layer, and a The formed emitter resonance tunnel barrier layer, two or more island-shaped emitter layers formed on the emitter resonance tunnel barrier layer, a collector electrode that forms an ohmic junction on the collector layer, and the two or more island-shaped In a semiconductor device having a multi-emitter type transistor having two or more emitter electrodes each having an ohmic junction on an emitter layer, the semiconductor device includes a base layer between the two or more island-shaped emitter layers,
A semiconductor device provided with a low resistance region. 4. A substrate, a collector layer formed on the substrate, a collector barrier layer formed on the collector layer, a base layer formed on the collector barrier layer, and a The formed emitter resonance tunnel barrier layer, two or more island-shaped emitter layers formed on the emitter resonance tunnel barrier layer, a collector electrode that forms an ohmic junction on the collector layer, and the two or more island-shaped In a semiconductor device provided with a multi-emitter type transistor having two or more emitter electrodes each having an ohmic junction on an emitter layer, in the emitter resonance tunnel barrier layer and the base layer between the two or more island-shaped emitter layers Wherein a low resistance region is provided. 5. A substrate, a collector layer formed on the substrate, a base layer formed on the collector layer, an emitter layer formed on the base layer, and formed on the emitter layer A multi-layer structure comprising at least two island-shaped emitter contact layers, a collector electrode having an ohmic junction on the collector layer, and two or more emitter electrodes having an ohmic junction on the two or more island-shaped emitter contact layers, respectively. A semiconductor device comprising an emitter-type transistor, wherein a low-resistance region is provided in the base layer between the two or more island-shaped emitter contact layers. 6. A substrate, a collector layer formed on the substrate, a base layer formed on the collector layer, an emitter layer formed on the base layer, and formed on the emitter layer A multi-layer structure comprising at least two island-shaped emitter contact layers, a collector electrode having an ohmic junction on the collector layer, and two or more emitter electrodes having an ohmic junction on the two or more island-shaped emitter contact layers, respectively. A semiconductor device comprising an emitter-type transistor, wherein a low-resistance region is provided in the emitter layer and the base layer between the two or more island-shaped emitter contact layers. 7. The semiconductor device according to claim 1, wherein the low-resistance region is an alloy layer of a metal and a semiconductor. 8. The semiconductor device according to claim 1, wherein the low-resistance region is a metal layer. 9. A first step of sequentially growing a collector layer, a collector barrier layer, a base layer, an emitter barrier layer, and an emitter layer on a substrate, and forming an emitter electrode layer on the emitter layer; Pattern the emitter electrode layer into a predetermined shape,
After forming two or more emitter electrodes, the second emitter layer is selectively etched using the two or more emitter electrodes as a mask to form two or more island-like emitter layers.
Forming a metal layer on the emitter barrier layer between the two or more island-shaped emitter layers using the two or more emitter electrodes as a mask, and then performing a heat treatment to form the emitter barrier under the metal layer. A third step of forming an alloy layer of a metal and a semiconductor in the base layer and the base layer, and after the mesa-etching of the emitter barrier layer, the base layer, and the collector barrier layer, on the exposed collector layer And a fourth step of forming a collector electrode. 10. The method according to claim 9, wherein the emitter barrier layer is selectively etched using the two or more emitter electrodes as a mask, instead of the third step. After exposing the base layer between the island-shaped emitter layers, forming a metal layer on the exposed base layer by ohmic junction using the two or more emitter electrodes as a mask. Manufacturing method of a semiconductor device. 11. A collector layer, a base layer, an emitter layer, and an emitter contact layer are sequentially grown on a substrate,
A first step of forming an emitter electrode layer on the emitter contact layer, and patterning the emitter electrode layer into a predetermined shape;
A second step of selectively etching the emitter contact layer using the two or more emitter electrodes as a mask to form two or more island-shaped emitter contact layers, after forming the two or more emitter electrodes; After forming a metal layer on the emitter layer between the two or more island-shaped emitter contact layers using the two or more emitter contact layers as a mask, a heat treatment is performed, and the emitter layer and the base layer below the metal layer are formed. A third step of forming an alloy layer of a metal and a semiconductor therein, and a fourth step of forming a collector electrode on the exposed collector layer after the emitter layer is mesa-etched. Manufacturing method of a semiconductor device.