JP4182376B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a field effect transistor that has high forward and reverse breakdown voltages at a gate and can have good ohmic contacts such as a source and a drain.
[0002]
[Prior art]
A high electron mobility transistor (HEMT) is known as one of compound semiconductor field effect transistors having good high-frequency characteristics and high-speed operation characteristics.
[0003]
There are various variations in the HEMT depending on the required characteristics. For example, if a high breakdown voltage is required, the doping of the electron supply layer is made uniform without planarization, Means such as laminating a low-concentration doped layer or an undoped layer on the electron supply layer is employed.
[0004]
In the HEMT having such a configuration, it is difficult to obtain an ohmic contact as compared with a HEMT having a standard structure, that is, a HEMT not intended to have a high breakdown voltage.
[0005]
FIG. 12 is a cutaway side view of a main part for explaining a HEMT having a standard structure. In FIG. 12, 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a spacer layer, and 5a is an electron. The supply layer, 6 is a cap layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 11 is an alloying region, 13 is a current path, and 14 is a leakage current path.
[0006]
In this HEMT, the forward and reverse breakdown voltages at the gate are not required to be so high, so the gate electrode 9 is in direct contact with the electron supply layer 5a, and the electron supply layer 5a and the cap layer 6 are Since both are highly doped, the source electrode 7 and the drain electrode 8 and the two-dimensional electron gas layer can be easily brought into ohmic contact.
[0007]
FIGS. 13 and 14 are side cross-sectional side views for explaining a HEMT having a structure that increases the breakdown voltage in the forward direction and the reverse direction in the gate, and the same symbols as those used in FIG. Represent parts or have the same meaning.
[0008]
In FIG. 13, reference numeral 5b denotes a barrier layer formed between the electron supply layer 5a and the cap layer 6 and formed on the entire surface of the electron supply layer 5a.
[0009]
In FIG. 14, reference numeral 12 denotes a low impurity concentration gate electrode buried layer formed on the barrier layer 5B.
[0010]
In the HEMT shown in FIG. 13 or FIG. 14, the presence of the barrier layer 5 b and the low impurity concentration gate electrode buried layer 12 has a high resistance in the region where the source electrode 7 and the drain electrode 8 are formed. It is difficult to take.
[0011]
FIG. 15 is a cutaway side view of the main part for explaining the HEMT for solving the problem of the conventional example explained with reference to FIG. 13 or FIG. 14, and the same symbols as those used in FIGS. Represent parts or have the same meaning.
[0012]
In FIG. 15, reference numeral 21 denotes a recess reaching the channel layer 3 from the surface of the cap layer 6.
[0013]
In the HEMT shown in FIG. 15, layers having high resistance such as the low impurity concentration gate electrode buried layer 12 and the barrier layer 5b are removed, and the source electrode 7 and the drain electrode 8 are in direct contact with the channel layer 3. Although the HEMT problem described with reference to FIG. 13 or FIG. 14 has been solved, a new problem is derived due to the structure.
[0014]
That is, in the HEMT of FIG. 15, since a gap is formed between the gate side wall surface of the recess 21 and the ohmic electrode, a depletion layer spreads in the portion of the channel layer 3 immediately below the gap, and the parasitic resistance increases. Will do.
[0015]
In order to prevent the generation of such a depletion layer, it may be considered that it is not necessary to generate the voids as described above. However, in such a case, a new inconvenience occurs. .
[0016]
FIG. 16 is a cutaway side view of the main part for explaining the HEMT in which the gap in the HEMT described with reference to FIG. 15 is eliminated. Does the same symbol as that used in FIGS. 12 to 15 represent the same part? Or it shall have the same meaning.
[0017]
In the HEMT shown in FIG. 16, the wall surface of the recess and the source electrode 7 or the drain electrode 8 are in contact with each other. In such a structure, the alloy of the source electrode 7 and the drain electrode 8 and the channel layer 3 is present. When the alloying heat treatment is performed, the alloying region 11 is abnormally diffused in the lateral direction, the gate electrode 9 and the ohmic electrode are brought close to each other, and both the forward and reverse breakdown voltages at the gate are lowered.
[0018]
[Problems to be solved by the invention]
In the present invention, even a HEMT in which a low-concentration doped layer or a non-doped layer is interposed between the cap layer and the channel layer to improve the breakdown voltage in the forward direction and the reverse direction in the gate causes any problems. Therefore, it is possible to satisfactorily make ohmic contacts such as a source electrode and a drain electrode.
[0019]
[Means for Solving the Problems]
In the present invention, a recess is formed in the region where the ohmic electrode is formed, and is in direct contact with a semiconductor layer that requires an ohmic contact. Basically, there is a structure in which no voids are formed in the electrode, and an alloying region of the ohmic electrode does not extend in the gate direction.
[0020]
FIG. 1 is a cutaway side view showing a principal part of a semiconductor device for explaining the principle of the present invention. In FIG. 1, 1 is a substrate, 2 is a buffer layer, 3 is a channel layer, 4 is a spacer layer, 5a is An electron supply layer, 5b is a barrier layer, 6 is a cap layer, 7 is a source electrode, 8 is a drain electrode, 9 is a gate electrode, 10 is a refractory metal layer, 11 is an alloyed region, and 12 is a low-concentration gate electrode buried layer. Each is shown.
[0021]
A characteristic configuration in the semiconductor device shown in FIG. 1 is that a refractory metal layer 10 is interposed between a wall surface in each recess for forming the source electrode 7 or the drain electrode 8 and each ohmic electrode. It is.
[0022]
By adopting this configuration, the problem that the depletion layer expands in the channel layer 3 immediately below the wall surface of the recess and the ohmic electrode and the parasitic resistance increases can be solved. When an alloying heat treatment with a semiconductor is performed, there is no problem that the alloying region extends in the gate direction and the breakdown voltage decreases.
[0023]
From the foregoing, in the semiconductor device according to the present invention,
(1)
A semiconductor layer stacked structure formed on a semiconductor substrate (for example, substrate 1) and including at least a channel layer (for example, channel layer 3), a carrier supply layer (for example, electron supply layer 5a), and a barrier layer (for example, barrier layer 5b); A source electrode (for example, source electrode 7) formed in a recess drilled in a source region in a semiconductor layer stacked structure, and interposed between the wall surface of the recess and the source electrode As well as Contact both sides In addition, it is possible to effectively prevent abnormal diffusion of the alloying region (for example, the alloying region 11) during the alloying heat treatment. It is characterized by comprising a refractory metal layer (for example, refractory metal layer 10). According to this structure, a recess is usually formed in a source provided closer to the gate electrode than the drain. Even after the source electrode is formed, the heat-resistant metal layer can effectively prevent the alloying region from abnormally diffusing during the alloying heat treatment,
[0024]
(2)
In the above (1), a drain electrode (for example, drain electrode 8) formed in a recess formed in a drain region in the semiconductor layer laminated structure, and a wall surface of the recess and the drain electrode Intervention As well as Contact both sides In addition, it is possible to effectively prevent abnormal diffusion of the alloying region during the alloying heat treatment. A refractory metal layer, and according to this configuration, usually at the drain. And Even if the drain electrode is formed after forming the recess, the refractory metal layer can effectively prevent abnormal diffusion of the alloying region during the alloying heat treatment,
[0025]
(3)
In the above (1) or (2), the recess reaches the barrier layer, and
[0026]
(4)
In the above (1) or (2), the recess reaches the channel layer. According to this configuration and the configuration seen in (3), the recess is formed according to the semiconductor layer stacked structure. The depth can be selected and the alloying region can be in ohmic contact with the channel layer well by alloying heat treatment,
[0027]
(5)
In any one of the above (1) to (4), the impurity contained in the carrier supply layer is planar-doped, and
[0028]
(6)
In any one of the above (1) to (5), the carrier supply layer is an electron supply layer (for example, an electron supply layer 105a: see FIG. 2, the same applies hereinafter), and an i layer (on the electron supply layer) For example, an n layer (for example, n layer) having a lower impurity concentration than the barrier layer 105b) or the electron supply layer. ^- Layer) is formed by lamination, and
[0029]
(7)
In any one of the above (1) to (5), the carrier supply layer is a hole supply layer and has a lower impurity concentration on the hole supply layer than the i layer or the hole supply layer. It is characterized in that a certain p-layer is laminated, and
[0030]
(8)
In any one of the above (1) to (7), the carrier supply layer (for example, the electron supply layer 135a: see FIG. 9, the same applies hereinafter) is replaced with the channel layer (for example, the channel layer 133) and the semiconductor substrate (for example, the substrate 131). In this structure, a so-called reverse HEMT structure is realized.
[0031]
By adopting the above means, a lightly doped layer or a non-doped layer is interposed between the cap layer and the channel layer in the HEMT to improve the forward and reverse breakdown voltage in the gate, and Even in such a semiconductor layer configuration, the ohmic contact such as the source electrode and the drain electrode can be realized satisfactorily, and problems caused by the configuration, for example, depletion caused by a gap between the recess wall surface and the ohmic electrode There are no problems such as the generation of layers and the alloyed region of the ohmic electrode approaching the gate.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 is a cutaway side view showing a main part of the semiconductor device for explaining the first embodiment of the present invention.
[0033]
In the figure, 101 is a substrate, 102a is a buffer layer, 102b is a buffer layer, 103 is a channel layer, 104 is a spacer layer, 105a is an electron supply layer, 105b is a barrier layer, 106 is a cap layer, 107 is a source electrode, Reference numeral 108 denotes a drain electrode, 109 denotes a gate electrode, 110 denotes a refractory metal layer, and 111 denotes an alloying region.
[0034]
3 to 7 are fragmentary cutaway side views showing the semiconductor device at process points for explaining the manufacturing process of the semiconductor device shown in FIG. 2, and will be described below with reference to these drawings. To do.
[0035]
Refer to FIG.
3- (1)
By applying a MOVPE (metalorganic vapor phase epitaxy) method, the first buffer layer 102a, the second buffer layer 102b, the channel layer 103, the spacer layer 104, the electron supply layer 105a, the barrier layer 105b, and the cap are formed on the substrate 101. Layer 106 is formed.
[0036]
The main data relating to each of the semiconductor parts is exemplified as follows.
(1) About substrate 101
Material: Semi-insulating InP
(2) About the first buffer layer 102a
Material: i-InP
Thickness: 50 [nm]
(3) About the second buffer layer 102b
Material: i-InAlAs (In composition 0.52)
Thickness: 300 [nm]
(4) Channel layer 103
Material: i-InGaAs (In composition 0.53)
Thickness: 20 [nm]
(5) About spacer layer 104
Material: i-InAlAs
Thickness: 3 [nm]
(6) About the electron supply layer 105a
Material: n-InAlAs (In composition 0.52)
Impurity concentration: 5 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 5 [nm]
(7) About the barrier layer 105b
Material: i-InAlAs (In composition 0.52)
Thickness: 20 [nm]
▲ 8 ▼ Cap layer 106
Material: n-InGaAs (In composition 0.53)
Impurity concentration: 1 × 10 ¹⁹ 〔cm ^-3 ]
Thickness: 50 [nm]
[0037]
Refer to FIG.
3- (2)
By applying a resist process in lithography technology, a resist film 161 having an opening at a recess formation scheduled portion is formed.
[0038]
3- (3)
By applying a wet etching method using an etchant as a phosphoric acid-based etching solution, the cap layer 106, the barrier layer 105b, the electron supply layer 105a, and the spacer layer 104 are etched using the resist film 161 as a mask to form a recess 104A. To do.
[0039]
Refer to FIG.
4- (1)
By applying the sputtering method, a WSi film 162 having a thickness of about 5 nm is formed on the entire surface.
[0040]
Refer to FIG.
4- (2)
Etching gas SF ₆ The WSi film 162 is anisotropically etched to leave the WSi film 162 only on the wall surface of the recess 104A.
[0041]
Refer to FIG.
5- (1)
By applying the vacuum deposition method, an electrode material film 163 made of AuGe / Au having a thickness of 30 [nm] / 300 [nm] is formed.
[0042]
Refer to FIG.
5- (2)
Patterning is performed by peeling the resist film 161 together with the laminated electrode material film 163 by immersing it in a resist stripping solution.
[0043]
The electrode material film 163 remaining after the lift-off process becomes the source electrode 107 and the drain electrode 108.
[0044]
5- (3)
By applying the ion milling method, the electrode material film 163 and the WSi film 162 protruding on the recess wall surface are removed by milling from an oblique direction.
[0045]
5- (4)
An alloying region in contact with the channel layer 3 and hence the two-dimensional electron gas layer is obtained by performing an alloying heat treatment of the source electrode 107 and the drain electrode 108 and the semiconductor at a temperature of 400 ° C. and a time of 3 minutes 111 is generated.
[0046]
Refer to FIG.
6- (1)
Electron beam (EB) resist films 164a and 164b having different sensitivities are formed by applying a resist process in lithography technology. The sensitivity of the EB resist films 164a and 164b is 164a <164b.
[0047]
6- (2)
EB drawing is performed, and openings 164B having a shape corresponding to the laterally projecting portion of the gate electrode having a T-shaped cross section and openings 164A having a shape corresponding to the leg portion are formed in the resist films 164b and 164a at the gate electrode formation scheduled portions. Form.
[0048]
Refer to FIG.
6- (3)
The cap layer 106 is etched using the resist films 164b and 164a as a mask by applying a wet etching method in which an etchant is a citric acid-based etching solution.
[0049]
Etching here is over-etching, and side etching of about 0.1 μm, for example, is applied to the cap layer 106 in the lateral direction. As a result, the opening 164A of the resist film 164a (FIG. 5A). A void 106H extending beyond the range of ()) is generated. The citric acid-based etching solution does not etch the barrier layer 105b made of i-InAlAs, which is the base of the cap layer 106.
[0050]
6- (4)
By applying the vacuum deposition method, an Al film having a thickness of about 30 [nm] is formed on the entire surface.
[0051]
The Al film enters the removed portion of the cap layer 106 through the openings of the resist films 164b and 164a, and the tip thereof makes Schottky contact with the barrier layer 105b.
[0052]
See FIG.
7- (1)
By immersing in the resist stripping solution, the resist films 164b and 164a are stripped together with the laminated Al film, thereby patterning the Al film to form the gate electrode 165.
[0053]
In the semiconductor device manufactured through the above process, since the WSi film 162 is interposed between the source electrode 107 or the drain electrode 108 and the recess wall, no depletion layer is generated in the channel layer 103, and therefore, the parasitic device is parasitic. The resistance does not increase, and the problem that the alloyed region 111 extends from the side surface of the source electrode 107 or the drain electrode 108 and approaches the gate electrode 165 does not occur, so that the gate breakdown voltage does not decrease.
[0054]
FIG. 8 is a cutaway side view showing a main part of a semiconductor device for explaining the second embodiment of the present invention. The same reference numerals as those used in FIGS. 2 to 7 represent the same parts. It shall have the same meaning.
[0055]
In the figure, 121 is a substrate, 122a is a buffer layer, 122b is a buffer layer, 123 is a channel layer, 124 is a spacer layer, 125a is an electron supply layer, 125b is a barrier layer, and 126 is a cap layer.
[0056]
The main differences between the second embodiment and the first embodiment are the configuration of the semiconductor portion and the method for forming the recess for the ohmic electrode, which will be described below.
[0057]
(1) About the board 121
Material: Semi-insulating GaAs
(2) About the buffer layer 122a
Material: i-GaAs
Thickness: 50 [nm]
(3) About the buffer layer 122b
Material: i-AlGaAs (Al composition 0.3)
Thickness: 300 [nm]
(4) Channel layer 123
Material: i-InGaAs (In composition 0.15)
Thickness: 15 [nm]
(5) About spacer layer 124
Material: i-InGaP (In composition 0.5)
Thickness: 3 [nm]
(6) About the electron supply layer 125a
Material: n-InGaP (In composition 0.5)
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 20 [nm]
▲ 7 ▼ About the barrier layer 125b
Material: i-InGaP (In composition 0.5)
Thickness: 10 [nm]
▲ 8 ▼ Cap layer 126
Material: n-GaAs
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 50 [nm]
[0058]
As a method for forming a recess for an ohmic electrode,
(1) For GaAs, the etching gas is SiCl. _Four Dry etching or wet etching using an etchant as an ammonia-based etching solution is applied.
(2) For InGaP, wet etching using an etchant as an HCl-based etchant is applied.
[0059]
FIG. 9 is a cutaway side view showing a main part of a semiconductor device for explaining the third embodiment of the present invention. The same reference numerals as those used in FIGS. It shall have the same meaning.
[0060]
In the figure, 131 denotes a substrate, 132a denotes a buffer layer, 132b denotes a buffer layer, 133 denotes a channel layer, 134 denotes a spacer layer, 135a denotes an electron supply layer, 135b denotes a barrier layer, and 136 denotes a cap layer.
[0061]
The main differences between the third embodiment and the first embodiment are the configuration of the semiconductor portion and the method for forming the recess for the ohmic electrode, which will be described below.
[0062]
(1) About substrate 131
Material: Semi-insulating GaAs
(2) About the buffer layer 132a
Material: i-GaAs
Thickness: 50 [nm]
(3) About the buffer layer 132b
Material: i-AlGaAs (Al composition 0.3)
Thickness: 300 [nm]
(4) Channel layer 133
Material: i-InGaAs (In composition 0.15)
Thickness: 15 [nm]
(5) About spacer layer 134
Material: i-AlGaAs (Al composition 0.3)
Thickness: 3 [nm]
(6) About the electron supply layer 135a
Material: n-AlGaAs (Al composition 0.3)
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 20 [nm]
▲ 7 ▼ About the barrier layer 135b
Material: i-AlGaAs (Al composition 0.5)
Thickness: 20 [nm]
▲ 8 ▼ Cap layer 136
Material: n-GaAs
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 50 [nm]
In the case where AlGaAs having an Al composition of 0.4 or more is used as the barrier layer, if an ohmic electrode is formed on the cap layer 136, it is difficult to make an ohmic contact. Therefore, the ohmic electrode is formed in the recess. The configuration is advantageous because the problem is eliminated.
[0063]
As a method for forming the recess for the ohmic electrode, the etching gas is SiCl. _Four Dry etching or wet etching using an etchant as an ammonia-based etching solution is applied.
[0064]
FIG. 10 is a cutaway side view showing a main part of a semiconductor device for explaining the fourth embodiment of the present invention. The same reference numerals as those used in FIGS. 2 to 9 represent the same parts. It shall have the same meaning.
[0065]
In the figure, 141 is a substrate, 142a is a buffer layer, 142b is a buffer layer, 143 is a channel layer, 144 is a spacer layer, 145a is an electron supply layer, 145b is a barrier layer, 145c is a gate buried layer, and 146 is a cap layer. Respectively.
[0066]
The main differences between the fourth embodiment and the first embodiment are the structure of the semiconductor portion, the method of forming the ohmic electrode recess and the etching depth, and the method of manufacturing the gate, which will be described below.
[0067]
(1) About the substrate 141
Material: Semi-insulating GaAs
(2) About the buffer layer 142a
Material: i-GaAs
Thickness: 50 [nm]
(3) About the buffer layer 142b
Material: i-AlGaAs (Al composition 0.3)
Thickness: 300 [nm]
(4) Channel layer 143
Material: i-InGaAs (In composition 0.15)
Thickness: 15 [nm]
(5) About spacer layer 144
Material: i-AlGaAs (Al composition 0.3)
Thickness: 3 [nm]
(6) About the electron supply layer 145a
Material: n-AlGaAs (Al composition 0.3)
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 20 [nm]
▲ 7 ▼ About the barrier layer 145b
Material: i-AlGaAs (Al composition 0.3)
Thickness: 10 [nm]
(8) About gate buried layer 145c
Material: i-GaAs
Thickness: 30 [nm]
▲ 9 ▼ Cap layer 146
Material: n-GaAs
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 50 [nm]
[0068]
As a method for forming the recess for the ohmic electrode, the etching gas is SiCl. _Four The dry etching or wet etching using an etchant as an ammonia-based etching solution is applied, and the recess has a depth obtained by removing the cap layer 146 and the gate buried layer 145c.
[0069]
As in the first embodiment, the gate is manufactured by the lift-off method after the cap layer 146 is etched, the gate buried layer 145c is subsequently etched, and then the gate metal is deposited. Pattern.
[0070]
FIG. 11 is a cutaway side view showing a main part of a semiconductor device for explaining the fifth embodiment of the present invention. The same symbols as those used in FIGS. 2 to 10 represent the same parts. It shall have the same meaning.
[0071]
In the figure, 151 is a substrate, 152a is a buffer layer, 152b is a buffer layer, 153 is a channel layer, 154 is a spacer layer, 155a is an electron supply layer, 155b is a high Al composition barrier layer, 155c is a barrier layer, 155d. Denotes a gate buried layer and 156 denotes a cap layer.
[0072]
The main differences between the fifth embodiment and the first embodiment are the configuration of the semiconductor portion, the method of forming the ohmic electrode recess and the etching depth, and the method of manufacturing the gate, which will be described below.
[0073]
(1) About the substrate 151
Material: Semi-insulating GaAs
(2) About the buffer layer 152a
Material: i-GaAs
Thickness: 50 [nm]
(3) About the buffer layer 152b
Material: i-AlGaAs (Al composition 0.3)
Thickness: 300 [nm]
(4) About the channel layer 153
Material: i-InGaAs (In composition 0.15)
Thickness: 15 [nm]
(5) About the spacer layer 154
Material: i-AlGaAs (Al composition 0.3)
Thickness: 3 [nm]
(6) About the electron supply layer 155a
Material: n-AlGaAs (Al composition 0.3)
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 20 [nm]
(7) About high Al composition barrier layer 155b
Material: i-AlGaAs (Al composition 0.5)
Thickness: 7 [nm]
(8) About the barrier layer 155c
Material: i-AlGaAs (Al composition 0.3)
Thickness: 3 [nm]
(9) About the gate buried layer 155d
Material: i-GaAs
Thickness: 30 [nm]
(10) About the cap layer 156
Material: n-GaAs
Impurity concentration: 2 × 10 ¹⁸ 〔cm ^-3 ]
Thickness: 50 [nm]
[0074]
As a method for forming the recess for the ohmic electrode, the etching gas is SiCl. _Four The dry etching or wet etching using an etchant as an ammonia-based etching solution is applied, and the recess is a depth obtained by removing the cap layer 156 and the gate buried layer 155c.
[0075]
As in the first embodiment, the gate is manufactured by the lift-off method after the cap layer 156 is etched, the gate buried layer 155c is subsequently etched, the gate metal is evaporated, and the like. Pattern.
[0076]
Next, an example in which the carrier supply layer is formed by planar doping will be described as a sixth embodiment of the present invention. As a configuration of the semiconductor device, the first embodiment described with reference to FIGS. In this case, the n-InAlAs electron supply layer 105a is merely replaced with a planar doping layer, and the illustration is omitted.
[0077]
In order to fabricate a semiconductor device using planar doping, the same steps as in the first embodiment are employed to form each semiconductor layer up to the spacer layer 104 on the substrate 101, and then an As raw material such as arsine (AsH). _Three ) Together with Si raw materials such as disilane (Si ₂ H ₆ ) To form a Si planar doping layer.
[0078]
Here, the reason for supplying the As raw material is to prevent As from re-evaporating from the spacer layer 104, and the impurity concentration in the Si planar doping layer is 5 × 10 5. ¹² 〔cm ^-2 ].
[0079]
After the Si planar doping layer is formed, the same steps as in the first embodiment are again performed, that is, the growth of the barrier layer 105b and the cap layer 106, the formation of the WSi film 162, the formation of the source electrode 107 and the drain electrode 108, and the gate electrode It may be completed by forming 165 or the like.
[0080]
In the sixth embodiment, since the electron supply layer or hole supply layer, which is the carrier supply layer, is a monoatomic layer, the distance between the gate electrode and the channel layer is shortened, and the short channel effect is unlikely to occur. It has advantages and is suitable for short gate length semiconductor devices.
[0081]
The present invention is not limited to the above embodiment, and many other modifications can be realized. For example, by appropriately selecting the conductivity type of each semiconductor layer, the electron supply layer is supplied with holes. It is easy to replace the layer with a semiconductor device using holes as carriers.
[0082]
In addition, a material for each semiconductor layer, for example, an appropriate material such as InAlAs, InGaP, or AlGaAs can be selected and used for the carrier supply layer. Further, dimensional conditions such as the thickness of each semiconductor layer, doping, etc. The concentration, impurity addition conditions, metal material, manufacturing process, and the like can be appropriately selected. In particular, as the material of the refractory metal layer, WSiN, TiW, TiWN, in addition to WSi used in the above embodiment, One or more types can be selected from Mo and the like.
[0083]
【The invention's effect】
In a semiconductor device according to the present invention, a semiconductor layer stacked structure formed on a semiconductor substrate and including at least a channel layer, a carrier supply layer, and a barrier layer; Above A source electrode (or drain electrode) formed in a recess formed in a source region (or drain region) in a semiconductor layer stacked structure, and between the wall surface of the recess and the source electrode (or drain electrode) Intervening As well as Contact both sides In addition, it is possible to effectively prevent abnormal diffusion of the alloying region during the alloying heat treatment. A heat-resistant metal layer.
[0084]
By adopting the above-described configuration, a low-concentration doped layer or a non-doped layer is interposed between the cap layer and the channel layer in the HEMT to improve the forward and reverse breakdown voltage in the gate, and Even with such a semiconductor layer configuration, it is possible to satisfactorily achieve ohmic contact such as a source electrode and a drain electrode, and problems due to the configuration, for example, depletion due to a gap between the recess wall surface and the ohmic electrode There are no problems such as the generation of layers and the alloyed region of the ohmic electrode approaching the gate.
[Brief description of the drawings]
FIG. 1 is a cutaway side view of a main part showing a semiconductor device for explaining the principle of the present invention.
FIG. 2 is a cutaway side view showing a main part of the semiconductor device for explaining the first embodiment in the present invention;
FIG. 3 is a cutaway side view showing a main part of the semiconductor device at a process point for explaining a manufacturing process of the semiconductor device shown in FIG. 2;
4 is a cutaway side view showing a main part of the semiconductor device at a process point for explaining a manufacturing process of the semiconductor device shown in FIG. 2; FIG.
FIG. 5 is a cutaway side view showing the main part of the semiconductor device at the main points of the process for explaining the manufacturing process of the semiconductor device shown in FIG. 2;
FIG. 6 is a cutaway side view showing a main part of the semiconductor device at a process point for explaining a manufacturing process of the semiconductor device shown in FIG. 2;
FIG. 7 is a cutaway side view showing a main part of the semiconductor device at a process point for explaining a manufacturing process of the semiconductor device shown in FIG. 2;
FIG. 8 is a cutaway side view showing a main part of a semiconductor device for explaining a second embodiment of the present invention.
FIG. 9 is a cutaway side view showing a main part of a semiconductor device for illustrating a third embodiment of the present invention.
FIG. 10 is a cutaway side view showing a main part of a semiconductor device for explaining a fourth embodiment of the invention.
FIG. 11 is a cutaway side view showing a main part of a semiconductor device for explaining a fifth embodiment of the invention.
FIG. 12 is a cut-away side view of a main part for explaining a HEMT having a standard structure.
FIG. 13 is a cutaway side view of a main part for explaining a HEMT having a structure for increasing the breakdown voltage in the forward direction and the reverse direction at the gate.
FIG. 14 is a cutaway side view of a main part for explaining a HEMT having a structure for increasing the breakdown voltage in the forward direction and the reverse direction at the gate.
FIG. 15 is a cutaway side view of an essential part for explaining a HEMT for solving the problem of the conventional example described with reference to FIG. 13 or FIG. 14;
FIG. 16 is a cutaway side view of an essential part for explaining the HEMT in which the gap in the HEMT described with reference to FIG. 15 is eliminated;
[Explanation of symbols]
1 Substrate
2 Buffer layer
3 channel layer
4 Spacer layer
5a Electron supply layer
5b Barrier layer
6 Cap layer
7 Source electrode
8 Drain electrode
9 Gate electrode
10 Heat-resistant metal layer
11 Alloying region
12 Low impurity concentration gate electrode buried layer

Claims (8)

A semiconductor layer stack structure formed on a semiconductor substrate and including at least a channel layer, a carrier supply layer, and a barrier layer;
A source electrode formed in a recess drilled in a source region in the semiconductor layer laminated structure;
A refractory metal layer that is interposed between the wall surface of the recess and the source electrode and is in contact with both, and can effectively prevent abnormal diffusion of the alloying region during the alloying heat treatment. A featured semiconductor device. A drain electrode formed in a recess formed in the drain region in the semiconductor layer stack structure;
A refractory metal layer that is interposed between the wall surface of the recess and the drain electrode and is in contact with both, and can effectively prevent abnormal diffusion of the alloyed region during the alloying heat treatment. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the recess reaches the barrier layer. 3. The semiconductor device according to claim 1, wherein the recess reaches the channel layer. 5. The semiconductor device according to claim 1, wherein the impurity contained in the carrier supply layer is planar-doped. 6. The carrier supply layer is an electron supply layer, and an i layer or an n layer having a lower impurity concentration than that of the electron supply layer is laminated on the electron supply layer. The semiconductor device according to any one of the above. The carrier supply layer is a hole supply layer, and an i layer or a p layer having a lower impurity concentration than the hole supply layer is laminated on the hole supply layer. The semiconductor device according to any one of 1 to 5. 8. The semiconductor device according to claim 1, wherein a carrier supply layer is interposed between the channel layer and the semiconductor substrate.

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