JPH0964340A - Field effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the source resistance and the drain resistance of a high electron mobility transistor(HEMT). SOLUTION: On an InP substrate 1, the following are laminated in the given order; a buffer layer 2 (film thickness 100nm) composed of undoped InAlAs (In 52%), a channel layer 3 (film thickness 15nm) composed of undoped InGaAs (In 53%), a spacer layer 4 (film thickness 5nm) composed of undoped InAlAs (In 52%), a doped layer 5 (film thickness 10nm) composed of N-type InAlAs (In 52%), a gate contact layer 6 (film thickness 10nm) composed of undoped InAlAs (In 54%), and an ohmic contact layer 71 (film thickness 5nm) composed of δdoped N-type InGaAs (In 80%). A recessed part 71a is formed in the ohmic contact layer 71. A gate electrode 8 having a T-shaped section is formed in the part where the gate contact layer 6 is exposed via the recessed part 71a. A metal film 11 (film thickness 50nm) is formed on the ohmic contact layer 71. A source electrode 9 and a drain electrode 10 are formed on the metal film 11. Thus an HEMT 100 is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as FET), and particularly to a high electron mobility transistor (High Electron Mobility Transistor) used for a high frequency amplifying device, a high speed switching device and the like.
lity Transistor: hereinafter referred to as HEMT).

[0002]

2. Description of the Related Art With the recent increase in demand for radio waves, compound semiconductor FEs operating at higher frequencies than silicon transistors
T, for example, GaAs MESFET (metal semicondu
Demand for ctor FETs) and HEMTs is increasing. In order to support the higher frequency millimeter wave band, InA
HEM using a new structure called lAs / InGaAs
The development of T is underway, for example, Japanese Patent Laid-Open No. 1-258.
Techniques disclosed in Japanese Patent No. 474, etc. are known. This InAlAs / InGaAs HEMT200
FIG. 6 shows the structure. On the substrate 1 made of InP, In
Buffer layer 2 (film thickness 100 nm) made of AlAs, I
Channel layer 3 (thickness: 15 nm) made of nGaAs, I
Spacer layer 4 (thickness 5 nm) made of nAlAs, 1 ×
N-type In doped to a carrier concentration of 10 ¹⁹ cm ^-3
Doped layer 5 (film thickness 10 nm) made of AlAs, InA
gate contact layer 6 (film thickness 10n
m) A cap layer 7 made of n-type InGaAs doped with a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ (film thickness 20n
m) are sequentially stacked. Here, the non-n-type layer is an undoped layer. The composition ratio of In is In
The AlAs layer is 0.52, and the InGaAs layer is 0.53. Then, only the portion where the gate electrode 8 is provided is recess-etched in the cap layer 7 to provide the recess portion 7a, and the gate electrode 8 having a T-shaped cross section is formed on the exposed gate contact layer 6. The source electrode 9 is formed on the cap layer 7.
And the drain electrode 10 is formed.

The purpose of forming the cap layer 7 on the gate contact layer 6 is to prevent oxidation of the gate contact layer 6 and to reduce lateral resistance from the source electrode 9 and the drain electrode 10 to the vicinity of the gate electrode 8 to improve device performance. To improve. Therefore, since the doping is performed at a considerably high concentration, it is necessary to remove the cap layer 7 in order to form the gate electrode 8 requiring the Schottky characteristic. In order to remove the cap layer 7, the gate electrode 8
It is necessary to perform recess etching while sharing the opening of the resist used for forming the gate contact layer and stop the gate contact layer 6 in an exposed state. The width of the resist opening is
Determined by the width of the gate electrode 8, usually 0.1 to 0.25 μm
It is a degree. In FIG. 6, InAlAs / InGaAs system H
The structure of EMT200 is shown. GaAs MESFET
Also in the conventional AlGaAs / GaAs HEMT, a heavily doped n-type cap layer is provided for the same purpose.
It is necessary to form a gate electrode after removing this by recess etching.

[0004]

However, in the above disclosed technique, when the cap layer 7 is recess-etched,
Since the width of the opening of the resist is about 0.1 to 0.25 μm and the cross-sectional shape of the recess 7a is a mesa shape, that is, the side surface 7b is slanted, when the cap layer 7 is formed too thick, the bottom surface 7c of the recess 7a is formed. Is smaller than the width of the opening of the resist, and the gate electrode 8 contacts the cap layer 7. Therefore, the thickness of the cap layer 7 can only be about 20 to 30 nm. There is a problem that there is a limit in reducing the lateral resistance from the drain electrode 10 to the vicinity of the gate electrode 8.

Therefore, in view of the above problems, an object of the present invention is to provide a HEMT in which the lateral resistance from the source and drain electrodes to the vicinity of the gate electrode is reduced by forming the cap layer with a metal film, and a method for manufacturing the HEMT. Is to provide.

[0006]

In order to solve the above-mentioned problems, the structure of the present invention has at least a first semiconductor layer, an opening, an impurity is added, and the first semiconductor layer is formed on the first semiconductor layer. An electric field including a formed second semiconductor layer and a gate electrode having a T-shaped cross-section formed in Schottky contact on the first semiconductor layer through an opening of the second semiconductor layer. An effect transistor having a metal layer formed on the second semiconductor layer in a non-contact manner with a gate electrode, and adopting a technical means in which a source electrode and a drain electrode are formed on the metal layer. Is.

Further, the structure of the second invention adopts a technical means that the upper width of the gate electrode having the T-shaped cross section is larger than the width of the opening of the second semiconductor layer.

According to a third aspect of the invention, the first semiconductor layer is I
The second semiconductor layer is made of nAlAs, and the second semiconductor layer is n-type InGa.
It adopts the technical means of being composed of As.

In the structure of the fourth invention, the first semiconductor layer is n
-Type AlGaAs, the second semiconductor layer is n-type G
The technical means is employed in which a third semiconductor layer made of aAs and provided as GaAs is provided under the first semiconductor layer.

According to a fifth aspect of the invention, the first semiconductor layer is n
-Type AlGaAs, the second semiconductor layer is n-type G
It adopts the technical means that a third semiconductor layer made of aAs and below the first semiconductor layer is made of InGaAs.

According to a sixth aspect of the invention, the first semiconductor layer is n
-Type GaAs, the second semiconductor layer is n-type GaA
The technical means of being composed of s is adopted.

According to a seventh aspect of the present invention, at least the first semiconductor layer, a second semiconductor layer having an opening, doped with impurities, and formed on the first semiconductor layer; A method for manufacturing a field effect transistor, comprising: a gate electrode having a T-shaped cross-section formed in Schottky contact on the first semiconductor layer through an opening of the second semiconductor layer. A step of forming a second semiconductor layer on the semiconductor layer, a step of etching the second semiconductor layer to form an opening, and exposing a part of the first semiconductor layer; Forming a gate electrode having a T-shaped cross-section in Schottky contact on the exposed portion of the layer; forming a metal layer on the second semiconductor layer without contacting the gate electrode; And a step of forming a source electrode and a drain electrode thereon. It is to employ a technical means.

In the eighth aspect of the invention, the step of forming the metal layer employs a technical means of forming the metal layer on the second semiconductor layer by a vapor deposition method.

[0014]

FUNCTION AND EFFECT The function of the present invention having the above-described structure is that a second semiconductor layer having an opening and having an impurity added is formed on the first semiconductor layer, and the second semiconductor layer is formed through the opening. A gate electrode having a T-shaped cross section is formed on one semiconductor layer in Schottky contact. A metal layer is formed on the second semiconductor layer so as not to contact the gate electrode, and a source electrode and a drain electrode are formed on the metal layer.
With such a structure of the FET, a metal layer is used instead of the conventional cap layer made of a semiconductor layer, so that the source resistance and the drain resistance can be reduced. Since this metal layer can be formed to a film thickness of about 50 nm, the source resistance and the drain resistance can be further reduced. Further, since the structure without the cap layer can reduce the etching amount under the gate electrode, it is possible to reduce the variation of the etching depth, that is, the variation of the distance between the gate electrode and the channel layer, and to improve the device characteristics. There is also an effect that variation can be reduced (Claim 1).

The second function is to make the upper width of the gate electrode having the T-shaped cross section larger than the width of the opening of the second semiconductor layer. Thus, if the metal layer is formed on the second semiconductor layer by the vapor deposition method after the gate electrode is formed, the upper portion of the gate electrode functions as a mask, and the metal layer can be prevented from entering the opening. Therefore, it is possible to prevent the occurrence of gate leak (claim 2).

The third action is to use InAl for the first semiconductor layer.
The second semiconductor layer is composed of n-type InGaAs. As a result, InAlAs with excellent device characteristics
/ InGaAs-based FET can be obtained. In particular, since the second semiconductor layer is composed of InGaAs, non-arrow ohmic contact can be obtained (claim 3).

The fourth function is to make the first semiconductor layer an n-type A
1GaAs, and the second semiconductor layer is n-type GaAs
And a third semiconductor layer made of GaAs is provided under the first semiconductor layer. As a result, Al with excellent device characteristics
A GaAs / GaAs FET can be obtained (claim 4).

The fifth function is to make the first semiconductor layer have n-type A
1GaAs, and the second semiconductor layer is n-type GaAs
And a third semiconductor layer made of InGaAs is provided under the first semiconductor layer. As a result, an AlGaAs / InGaAs-based FET having excellent device characteristics can be obtained (claim 5).

A sixth action is to make the first semiconductor layer have an n-type G
The second semiconductor layer is made of n-type GaAs. As a result, a GaAs-based ME with excellent device characteristics
An SFET can be obtained (claim 6).

A seventh action is to provide at least a first semiconductor layer, a second semiconductor layer which has an opening, is doped with impurities, and is formed on the first semiconductor layer, and the second semiconductor layer. A method for manufacturing a field effect transistor, comprising: a gate electrode having a T-shaped cross-section formed in Schottky contact on the first semiconductor layer through an opening of the semiconductor layer. A second semiconductor layer is formed on the semiconductor layer, and the second semiconductor layer is subjected to etching treatment to form an opening to expose a part of the first semiconductor layer. Next, a gate electrode having a T-shaped cross section is formed in Schottky contact with the exposed portion of the first semiconductor layer. Then, a metal layer is formed on the second semiconductor layer without contacting the gate electrode, and a source electrode and a drain electrode are formed on the metal layer by a lift-off method to form an FET. As a result, the gate electrode is T
Since it has a mold cross-sectional shape, if a metal layer is formed on the second semiconductor layer by a vapor deposition method, the upper part of the gate electrode functions as a mask, so that the mask forming step can be omitted, and the FET can be manufactured. Efficiency can be improved (Claim 7).

The eighth function is to form a metal layer on the second semiconductor layer by vapor deposition. Thereby, the metal layer can be formed on the second semiconductor layer in a self-aligned manner, so that there is no problem of pattern alignment accuracy and the yield can be improved (claim 8).

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on specific embodiments. FIG. 1 shows InAlA according to the present invention.
It is a typical structure figure showing composition of a 1st example of s / InGaAs / InP system HEMT100 (equivalent to a field effect transistor). As shown in FIG. 1, the semi-insulating I
On a substrate 1 made of nP, a buffer layer 2 made of InAlAs, a channel layer 3 made of InGaAs, InAl
A spacer layer 4 made of As, a doped layer 5 made of n-type InAlAs doped with a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ , and a gate contact layer 6 made of InAlAs.
A non-alloy ohmic contact layer 71 (corresponding to the second semiconductor layer) (corresponding to the first semiconductor layer) and made of n-type InGaAs having a δ-doped In composition ratio of 0.8 is sequentially formed. . The ohmic contact layer 71 is provided with a recess portion 71a (corresponding to an opening portion) having a width d ₂ , and the exposed portion of the gate contact layer 6 has a width d ₁ of the upper portion 8a having a width d ₁ via the recess portion 71a. A gate electrode 8 having a T-shaped cross section is formed. Here, the width d ₂ of the recess 71a is set smaller than the upper width d ₁ of the gate electrode 8. Further, a metal film 11 (corresponding to a metal layer) made of Al is formed on the ohmic contact layer 71, and a source electrode 9 and a drain electrode 10 made of Au are formed on the metal film 11 to form the HEMT 100. Has been formed. Incidentally, among the above semiconductor layers, the layer which is not the n-type is an undoped layer, and the In composition ratio of the semiconductor layer whose In composition ratio is not particularly described is 0.
52, 0.53 in the InGaAs layer.

Next, a method of manufacturing the HEMT 100 will be described with reference to FIG. FIG. 2 is a schematic structural diagram showing the manufacturing method of the HEMT 100. First, molecular beam crystal growth (Mo
lecular Beam Epitaxy: hereinafter referred to as MBE)
On the substrate 1, the buffer layer 2 has a film thickness of 100 nm, the channel layer 3 has a film thickness of 15 nm, the spacer layer 4 has a film thickness of 5 nm, the doped layer 5 has a film thickness of 10 nm, and the gate contact layer 6 has a film thickness of 1 nm.
A 0 nm thick ohmic contact layer 71 is sequentially grown to a film thickness of 5 nm (see FIG. 2A). Then, recess etching is performed on the ohmic contact layer 71,
A recess portion 71a having a width d ₂ is formed so as not to penetrate the gate contact layer 6. Due to the formation of the recess 71a, the gate electrode 8 having a T-shaped cross-section with an upper width d ₁ is formed on the exposed gate contact layer 6 by using a normal gate electrode forming method (see FIG. 2B).

After forming the gate electrode 8, Al is vapor-deposited on the entire surface to form a metal film 11. At this time, the metal film 11 is formed to be smaller than the height of the lower portion 8b of the gate electrode 8. In this embodiment, the metal film 11 has a thickness of 50 nm.
During vapor deposition, the upper portion 8a of the gate electrode 8 functions as a mask, and the metal film 11 is formed on the ohmic contact layer 71 except the projection region of the gate electrode 8 (FIG. 2).
(C)). Al is also formed on the gate electrode 8 when the metal film 11 is formed, but there is no problem. Since the metal film 11 is formed to be smaller than the height of the lower portion 8a of the gate electrode 8, the metal film 11 and the gate electrode 8 do not come into contact with each other. Further, the upper width d ₁ of the gate electrode 8 is set to the recess 71a.
Since it is set larger than the width d _{2 of} the recess portion 71a
The metal film 11 is prevented from penetrating into the gate electrode and gate leak is prevented from occurring. In order to minimize the wraparound of the vapor-deposited metal under the gate electrode 8 during vapor deposition, it is preferable that the vapor-deposited metal be vapor-deposited in a state where the degree of vacuum is as high as possible and the vapor-deposited metal is incident on the substrate as vertically as possible. After forming the metal film 11, the source electrode 9 and the drain electrode 10 are formed on the metal film 11 by the normal lift-off method, and the HEMT 100 is formed.
Are manufactured (see FIG. 2D).

With the HEMT 100 having the above structure, the resistance in the lateral direction can be made extremely small because the metal film 11 is provided instead of the conventional cap layer made of a semiconductor layer. In this embodiment, the metal film 11 is made of Al.
However, the inventors of the present invention have confirmed that the resistance is about two orders of magnitude smaller than that of the n-type InGaAs layer having the same film thickness, and the source resistance and the drain resistance can be significantly reduced. . Also, by being formed by the vapor deposition method,
Since the metal film 11 is formed on the ohmic contact layer 71 in a self-aligned manner, there is no problem of pattern alignment accuracy, and it is possible to form with a high yield. Further, since there is no conventional cap layer, the recess etching amount under the gate electrode 8 can be small, so that the variation of the etching depth is small and the variation of the distance between the gate electrode 8 and the channel layer 3 is small. Therefore, variations in element characteristics can be reduced. In addition, since the gate electrode 8 is used as a mask for the recess portion 71a when the metal film 11 is formed by vapor deposition, the mask forming step can be omitted and the manufacturing efficiency of the HEMT 100 is improved. be able to.

Although the semiconductor layers are crystal-grown by using the MBE apparatus in this embodiment, other crystal growth methods may be used. Further, the film thickness of each semiconductor layer is not limited to the above film thickness. In this example, the ohmic contact layer 71 was δ-doped and the In composition ratio was 0.8.
The ohmic contact layer 71 is composed of nGaAs.
However, the composition ratio is not limited as long as ohmic contact is formed in a non-alloyed state. Further, although the metal film 11 is made of Al in the present embodiment, the composition of the metal film 11 is not limited to this, and another composition may be used.

Although the buffer layer 2 is provided on the substrate 1 in the above embodiment, the buffer layer 2 is a layer provided to improve the crystallinity of the channel layer 3, and the buffer layer 2 may be provided if necessary. The configuration may be omitted. Further, although the spacer layer 4 is provided below the dope layer 5 in the above-described embodiment, the spacer layer 4 is a layer provided to improve the traveling speed of electrons in the channel layer 3, and may be provided if necessary. The spacer layer 4 may not be provided.

Next, a second embodiment according to the present invention is shown in FIG.
It will be described based on. FIG. 3 is a schematic structural diagram showing the structure of the AlGaAs / GaAs HEMT 101. On a substrate 41 made of semi-insulating GaAs, a buffer layer 42 (film thickness 500 nm) made of undoped GaAs,
A spacer layer 43 (film thickness 5 nm) made of undoped AlGaAs and a doped layer 44 made of n-type AlGaAs doped with a carrier concentration of about 2 × 10 ¹⁸ cm ^−3.
(Corresponding to the first semiconductor layer, film thickness 30 nm), ohmic contact layer 4 made of δ-doped n-type GaAs
5 (corresponding to the second semiconductor layer, film thickness 5 nm) are sequentially stacked. The Al composition ratio of the semiconductor layer is 0.3. In the ohmic contact layer 45, a recess portion 45a (corresponding to an opening portion) having a width d ₂ is formed to the extent that the doped layer 44 is exposed. A gate electrode 8 having a T-shaped cross section with an upper width d ₁ is formed on the exposed portion of the doped layer 44. The metal film 11 made of Al is formed on the ohmic contact layer 45, the source electrode 9 and the drain electrode 10 are formed on the metal film 11, and the HEMT is formed.
101 is configured.

By configuring the HEMT 101 as shown in FIG. 3, the metal film 11 is arranged instead of the conventional cap layer as in the first embodiment, so that the lateral resistance can be made extremely small. Therefore, the source resistance and the drain resistance can be reduced. Further, since the metal film 11 is formed in a self-aligned manner, there is no problem of pattern alignment accuracy, it can be formed with a high yield, and the recess etching amount under the gate electrode 8 can be small, so that the etching depth varies. As a result, the variation in element characteristics can be reduced. In addition to this, the structure can be simpler than that of the first embodiment.

Although the ohmic contact layer 45 is made of GaAs in this embodiment, GaAs is InGaAs.
Since it is more difficult to obtain non-alloy ohmic contact, the contact portion of the gate electrode 8 with the doped layer 44 is formed of a heat-resistant metal such as W or WSix (tungsten silicide),
Alternatively, the metal film 11 may be formed of Au—Ge alloy or the like and lightly alloyed.

Next, a third embodiment according to the present invention will be described with reference to FIG. Figure 4 shows AlGaAs / InGaAs
It is a schematic structural diagram showing a configuration of a system HEMT102.
On a substrate 51 made of semi-insulating GaAs, a buffer layer 52 made of undoped GaAs (film thickness 500 n
m), a channel layer 5 made of undoped InGaAs
3 (film thickness 20 nm), spacer layer 54 made of undoped AlGaAs (film thickness 5 nm), doped layer 55 made of n-type AlGaAs doped with a carrier concentration of about 2 × 10 ¹⁸ cm ⁻³ (first semiconductor). Corresponding to layers, film thickness 30
nm), an ohmic contact layer 56 made of δ-doped n-type GaAs (corresponding to the second semiconductor layer, film thickness 5
nm) are sequentially stacked. In addition, Al of the semiconductor layer
The composition ratio and the In composition ratio are both 0.15. In the ohmic contact layer 56, a recess portion 56a (corresponding to an opening) having a width d ₂ is formed to the extent that the doped layer 55 is exposed. A gate electrode 8 having a T-shaped cross section with an upper width d ₁ is formed on the exposed portion of the doped layer 55. A metal film 11 made of Al is formed on the ohmic contact layer 56, and the source electrode 9 is formed on the metal film 11.
The drain electrode 10 is formed, and the HEMT 102 is configured. In this way, HEMT 102 is replaced with AlGa
By using the As / InGaAs system, the same effect as that of the first embodiment can be obtained.

Further, FIG. 5 shows a fourth embodiment according to the present invention.
It will be described based on. Figure 5 shows GaAs MESFET1
FIG. 3 is a schematic structural diagram showing the configuration of No. 03. Semi-insulating G
On a substrate 61 made of aAs, a buffer layer 62 made of undoped GaAs (film thickness 500 nm), 4 × 10 ¹⁷
n-type GaA doped to a carrier concentration of about cm ^-3
A channel layer 63 made of s (corresponding to the first semiconductor layer, film thickness 200 nm) and an ohmic contact layer 64 made of δ-doped n-type GaAs (corresponding to the second semiconductor layer, film thickness 5 nm) are sequentially laminated. Has been done. In the ohmic contact layer 64, a recess portion 64a (corresponding to an opening) having a width d ₂ is formed to the extent that the channel layer 63 is exposed. A gate electrode 8 having a T-shaped cross section with an upper width d ₁ is formed on the exposed portion of the channel layer 63.
The metal film 11 made of Al is formed on the ohmic contact layer 64, and the source electrode 9 and the drain electrode 10 are formed on the metal film 11 to form the MESFET 103. By configuring the MESFET 103 in this way, the same effect as in the first embodiment can be obtained.

As indicated above, according to the present invention,
By forming a metal film on the ohmic contact layer and forming the source electrode and the drain electrode on the metal film, the lateral resistance can be made extremely small, and the source resistance and the drain resistance can be made small. . Further, if the metal film is formed by the vapor deposition method, it can be formed in a self-aligned manner on the ohmic contact layer.
It is possible to form with a high yield without the problem of pattern alignment accuracy. Furthermore, since there is no conventional cap layer, the amount of recess etching under the gate electrode can be small, so that the variation in etching depth can be reduced and the variation in the distance between the gate electrode and the channel layer can be reduced. Can be reduced. In addition, since the gate electrode having the T-shaped cross section can be used as a mask when forming the metal film, the mask forming step can be omitted and the HEMT productivity can be improved.

[Brief description of drawings]

FIG. 1 is a schematic structural diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a schematic diagram showing a manufacturing method of a first embodiment according to the present invention.

FIG. 3 is a schematic structural diagram showing a configuration of a second embodiment according to the present invention.

FIG. 4 is a schematic structural diagram showing the configuration of a third embodiment according to the present invention.

FIG. 5 is a schematic structural diagram showing the configuration of a fourth embodiment according to the present invention.

FIG. 6 Conventional InAlAs / InGaAs HEMT
Schematic structural diagram showing the configuration of.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 InP substrate 2 Undoped InAlAs buffer layer 3 Undoped InGaAs channel layer 4 Undoped InAlAs spacer layer 5 n-type InAlAs doped layer 6 undoped InAlAs gate contact layer 8 gate electrode 9 source electrode 10 drain electrode 11 metal film 71 δ-doped n-type InGaAs ohmic contact Layer 71a Recessed portion 100 InAlAs / InGaAs / InP
System HEMT

Claims (8)

[Claims] 1. A second semiconductor layer which has at least a first semiconductor layer and an opening, is doped with impurities, and is formed on the first semiconductor layer, and an opening of the second semiconductor layer. And a gate electrode having a T-shaped cross-section formed in Schottky contact on the first semiconductor layer through a gate portion, the gate electrode being provided on the second semiconductor layer. A field-effect transistor comprising a metal layer formed in a non-contact manner, wherein a source electrode and a drain electrode are formed on the metal layer. 2. The field effect transistor according to claim 1, wherein an upper width of the gate electrode having a T-shaped cross section is larger than a width of the opening of the second semiconductor layer. 3. The field effect transistor according to claim 1, wherein the first semiconductor layer is made of InAlAs, and the second semiconductor layer is made of n-type InGaAs. 4. The first semiconductor layer is n-type AlGaAs
2. The field effect transistor according to claim 1, wherein the second semiconductor layer is made of n-type GaAs, and a third semiconductor layer made of GaAs is provided under the first semiconductor layer. . 5. The first semiconductor layer is n-type AlGaAs
2. The field effect transistor according to claim 1, wherein the second semiconductor layer is made of n-type GaAs, and a third semiconductor layer made of InGaAs is provided under the first semiconductor layer. . 6. The field effect transistor according to claim 1, wherein the first semiconductor layer is made of n-type GaAs, and the second semiconductor layer is made of n-type GaAs. 7. A second semiconductor layer, which has at least a first semiconductor layer, an opening portion, is doped with impurities, and is formed on the first semiconductor layer, and an opening in the second semiconductor layer. And a gate electrode having a T-shaped cross-section formed in Schottky contact on the first semiconductor layer via a portion, the method comprising: A step of forming a second semiconductor layer, a step of performing an etching process on the second semiconductor layer to form the opening, and exposing a part of the first semiconductor layer, the first semiconductor Forming a gate electrode having a T-shaped cross-section in Schottky contact on the exposed portion of the layer; forming a metal layer on the second semiconductor layer without contacting the gate electrode; Forming a source electrode and a drain electrode on the metal layer Method of manufacturing a field effect transistor, characterized in that it consists of a process. 8. The method of manufacturing a field effect transistor according to claim 7, wherein in the step of forming the metal layer, the metal layer is formed on the second semiconductor layer by a vapor deposition method.