JPH10107260A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element wherein a deterioration of reproducibility and uniformity of element characteristics by heat-treatment is suppressed, and a deterioration in element characteristics is also suppressed. SOLUTION: A non-drop GaAs layer 6 is provided between an n-type GaAs layer 5 and a non-dope AlGaAs layer 7, and a film thickness of the non-dope GaAs layer 6 is set so that electronic concentration in a hetero-junction interface between AlGaAs and GaAs is almost 1×10<16> cm<-3> or less. Thereby, a generation of cavity by heating is suppressed, and diffusion of dopant in the n-type GaAs layer 5 and mutual diffusion of structure elements in the heterojunction interface are suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a heterojunction.

[0002]

2. Description of the Related Art Gallium arsenide (GaAs) and others
III-V compound semiconductors are widely used as materials for high-frequency transistors for communication and the like due to the high speed of electrons traveling through them. In particular, a semiconductor element having a heterojunction composed of two kinds of compound semiconductors has a much greater degree of freedom in designing a semiconductor layer than a semiconductor element having a single compound semiconductor. And so on.

Usually, a semiconductor layer of a semiconductor device having such a heterojunction is manufactured by a molecular beam epitaxy (MBE) or a metal organic chemical vapor deposition (MOVPE).
Method) or the like, and a steep hetero interface and a steep doping profile (impurity distribution shape) are realized.

FIG. 5 is a schematic cross-sectional view showing the structure of a conventional epitaxial growth substrate for a field effect transistor using a compound semiconductor, and FIG. 6 is a schematic cross section of the conventional field effect transistor using the epitaxial growth substrate of FIG. FIG.

In FIG. 5, a semi-insulating GaAs substrate 21
On top, a non-doped GaAs buffer layer 22 and n-type GaAs
The s channel layer 23 and the non-doped AlGaAs barrier layer 24 are sequentially formed by epitaxial growth (at a growth temperature of 500 ° C.). Since the n-type GaAs channel layer 23 is a layer through which electrons travel, when this epitaxial growth substrate is used for a high-output transistor, for example,
It is necessary to increase the carrier concentration of the n-type GaAs channel layer 23 to, for example, 1 × 10 ¹⁸ cm ⁻³ so that a large amount of current can flow. The non-doped AlGaAs barrier layer 24 is a layer with which the gate electrode makes Schottky contact as described later, and is provided to suppress leakage current to the gate electrode.

In FIG. 6, a gate electrode 28 is formed at the center of the non-doped AlGaAs barrier layer 24 so as to make Schottky contact with the AlGaAs barrier layer 24. On both sides of the gate electrode 28, a source electrode which makes ohmic contact with the AlGaAs barrier layer 24 is formed. 26 and a drain electrode 27 are formed respectively.

The field-effect transistor of FIG. 6 has a planar structure and thus has excellent productivity. When fabricating such a field-effect transistor having a planar structure, the source electrode 26 and the drain electrode 27 are formed in order to reduce the contact resistance between the source electrode 26 and the drain electrode 27 and the AlGaAs barrier layer 24 and obtain good device characteristics. It is necessary to form the n-type high conductive regions 25a and 25b immediately below the region 27 by an ion implantation method. In the ion implantation step, a heat treatment is performed at a temperature of, for example, 800 ° C. or higher in order to activate the implanted ions and restore the crystallinity of the semiconductor layer damaged by the ion implantation.

In the field effect transistor shown in FIG. 6, when a voltage is applied between the source electrode 26 and the drain electrode 27, the n-type GaAs channel layer 23 which is heavily doped is formed.
Electrons travel at high speed in parallel with the layer interface. for that reason,
Such a GaAs field-effect transistor can operate at high speed and can be used as a high-frequency element.

[0009]

However, in the above-mentioned conventional field effect transistor, in the step of forming the high conductive regions 25a and 25b by the ion implantation method, it is necessary to perform a heat treatment at a high temperature which is higher than the growth temperature during the epitaxial growth. is there. By performing the heat treatment at such a high temperature, n
Of dopant in the GaAs channel layer 23 and Al
Inter-diffusion and the like of constituent elements at the heterojunction of the GaAs barrier layer 24 and the n-type GaAs channel layer 23 occur, and the state of the semiconductor layer differs from the originally designed one.

In particular, when the doping concentration of the n-type GaAs channel layer 23 is high, many holes of Ga and Al, which are group III elements, are mainly generated during the heat treatment, and these holes are used for diffusion of the dopant and constituent elements. It works to promote mutual diffusion. In this case, the doping profile and the edge profile of the conduction band greatly change, and the actual device characteristics greatly differ from the design values, and the reproducibility of the device characteristics and the uniformity on the wafer surface are reduced. In addition, the generation of defects due to vacancies deteriorates device characteristics.

An object of the present invention is to provide a semiconductor device in which deterioration of reproducibility and uniformity of device characteristics and deterioration of device characteristics due to heat treatment are suppressed.

[0012]

A semiconductor device according to the present invention has a heterojunction between a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has one conductivity type. In a semiconductor element in which an impurity element is doped and carriers travel in the first semiconductor layer, the semiconductor element is made of the same semiconductor material as the first semiconductor layer between the first semiconductor layer and the second semiconductor layer, and is undoped or Carrier concentration is 10 ¹⁶ cm ^-3
The following third semiconductor layer is provided.

Here, "non-doped" means that an impurity element serving as a dopant is not intentionally introduced during epitaxial growth. In the semiconductor device according to the present invention, a heterojunction is formed by the second semiconductor layer and the third semiconductor layer. Since the third semiconductor layer is non-doped or has a carrier concentration of 10 ¹⁶ cm ⁻³ or less, the carrier concentration in the vicinity of the heterojunction decreases. Since the holes generated by the heat treatment are generated by the movement of the carriers, it is considered that when the carrier concentration decreases, the number of generated holes decreases. As the number of vacancies decreases,
Diffusion of the dopant in the first semiconductor layer and mutual diffusion of constituent elements near the interface of the heterojunction are suppressed, and defects due to vacancies are reduced. Thereby, the change of the semiconductor layer due to the heat treatment is reduced, the reproducibility of the device characteristics and the uniformity on the wafer surface are improved, and the deterioration of the device characteristics is suppressed.

Therefore, errors between actual device characteristics and design values are reduced, and a high-performance semiconductor device can be stably manufactured with good controllability. In particular, the first semiconductor layer has a higher electron affinity than the second semiconductor layer, the one conductivity type impurity element is an n-type impurity element, and the third semiconductor layer is an interface with the second semiconductor layer. It is preferable to have an electron concentration of 10 ¹⁶ cm ⁻³ or less in the vicinity.

In this case, since the vacancies generated by the heat treatment are generated by the transfer of electrons, when the electron concentration near the heterojunction interface becomes 10 ¹⁶ cm ⁻³ or less, the vacancies generated near the heterojunction interface are reduced. It is expected that the number will decrease. When vacancies are less likely to be generated, diffusion of the dopant in the first semiconductor layer and mutual diffusion of constituent elements near the interface of the heterojunction are suppressed, and defects due to vacancies are reduced. As a result, the change in the doping profile and the conduction band edge profile due to the heat treatment is reduced, the reproducibility of the device characteristics and the uniformity on the wafer surface are improved, and the deterioration of the device characteristics is suppressed.

The first, second and third semiconductor layers may be made of a III-V compound semiconductor. In this case, the generation of vacancies of the group III element during the heat treatment is suppressed.

In particular, the first and third semiconductor layers are made of GaAs, and the second semiconductor layer is made of AlGaAs.
Alternatively, it may be made of InGaP. Further, the first semiconductor layer and the third semiconductor layer are made of InGaAs, and the second semiconductor layer is made of GaAs, AlGaAs, InGaP,
It may be made of InAlAs or InP. In this case, a high-performance compound semiconductor device is stably manufactured with good controllability.

[0018]

FIG. 1 is a schematic cross-sectional view showing the structure of an epitaxial growth substrate for a field effect transistor according to one embodiment of the present invention. FIG. 2 is an electric field of the same embodiment using the epitaxial growth substrate of FIG. FIG. 3 is a schematic cross-sectional view illustrating a structure of an effect transistor. This field-effect transistor has both low-noise operation characteristics and high-output operation characteristics.
It is called an MT (Two Mode Channel FET) element.

In FIG. 1, a non-doped GaAs layer (buffer layer) 2 having a thickness of 8000 °, a non-doped InGaAs layer (a low-noise running layer) 3 having a thickness of 100 ° and a non-doped layer having a thickness of 50 ° are formed on a semi-insulating GaAs substrate 1. A GaAs layer 4, a 400 ° thick Si-doped n-type GaAs layer (high-power running layer) 5, a non-doped GaAs layer 6, and a thickness of 30
A 0 ° non-doped AlGaAs layer (barrier layer) 7 is sequentially formed by epitaxial growth. n-type GaAs
The doping concentration of layer 5 is 1 × 10 ¹⁸ cm ⁻³ . Each of the above layers 2 to 7 is continuously grown at a growth temperature of 500 ° C.

In FIG. 2, a gate electrode 11 is formed at the center of the non-doped AlGaAs layer 7 in Schottky contact with the AlGaAs layer 7, and a source electrode 9 and a drain electrode 10 are formed on both sides of the gate electrode 11, respectively. I have. Immediately below the source electrode 9 and the drain electrode 10, the n-type highly conductive regions 8 a,
8b is formed, and is in ohmic contact with the source electrode 9 and the drain electrode 10. As the ion implantation conditions, the implantation energy is 100 keV, and the implantation amount is 4 × 10 ¹³ cm ⁻² . After ion implantation, 5 at 880 ° C
Activation annealing is performed for seconds.

The source electrode 9 and the drain electrode 10 are Au / Ni alloyed by heat treatment at 450 ° C.
/ AuGe three-layer metal layer is used, and the gate electrode 1
As 1, a three-layer metal layer of Au / Pd / Ti is used.

In the TMT element of FIG. 2, when the gate potential is deep, the depletion layer extends to the lower side, and the n-type GaAs layer 5
Is mainly non-doped InGaAs
Run in layer 3. In this case, the electrons are undoped InGa
Since the semiconductor layer is well confined in the quantum well of the As layer 3, it is less affected by impurities in the n-type GaAs layer 5 doped at a high concentration, and an ultra-low noise characteristic can be obtained.

On the other hand, when the gate potential is shallow, the depletion layer shrinks and electrons mainly travel through the n-type GaAs layer 5. Therefore, the n-type GaAs layer 5 heavily doped acts as a channel, so that a high and flat transconductance is obtained and high output characteristics are obtained.

Here, a plurality of samples were prepared by changing the thickness of the non-doped GaAs layer 6 from 0 to 100 °, and the device characteristics were measured. The gate length was 0.5 μm and the gate width was 400 μm.

The element characteristics include the standard deviation of the drain saturation current measured for 100 TMT elements in the wafer, the standard deviation of the drain saturation current of the TMT element between 10 wafers, and the phase noise of the TMT element. Examined.
The standard deviation of the drain saturation current in the wafer is an index of the uniformity of the device characteristics on the wafer surface. The standard deviation of the drain saturation current between wafers is an index of the reproducibility of the device characteristics. The average value of the drain saturation current is about 100 mA. Further, the phase noise is an index indicating the state of occurrence of a defect.

Table 1 shows the thickness of the non-doped GaAs layer 6 and the heterojunction interface (non-doped GaAs layer 6 and non-doped GaAs layer 6).
The relationship between the electron concentration at the interface of the lGaAs layer 7, the standard deviation of the drain saturation current, and the phase noise is shown. The electron concentration at the heterojunction interface was obtained by calculation based on the carrier concentration of the n-type GaAs layer 5 and the film thickness of the non-doped GaAs layer 6.

[0027]

[Table 1]

As is clear from Table 1, non-doped Ga
As the thickness of the As layer 6 increases, the standard deviation of the drain saturation current within the wafer and between the wafers decreases. This indicates that as the thickness of the non-doped GaAs layer 6 increases, the uniformity of the device characteristics in the wafer surface and the reproducibility of the device characteristics become better.

The phase noise decreases as the thickness of the non-doped GaAs layer 6 increases. This indicates that the generation of defects is suppressed as the thickness of the non-doped GaAs layer 6 increases.

In particular, when the thickness of the non-doped GaAs layer 6 is 5
At 0 °, the electron concentration at the heterojunction interface is about 1 × 1
0 ¹⁶ cm ^-3 , and the standard deviations of the drain saturation current in the wafer and between the wafers are 2.2 mA and 3.
0 mA and the phase noise is -63.0 dBc
/ Hz. When the thickness of the non-doped GaAs layer 6 is increased to 50 ° or more, the electron concentration at the heterojunction interface is further reduced, but the device characteristics are hardly changed.

From the above results, it can be seen that the non-doped GaAs layer 6
If the thickness of the undoped GaAs layer 6 is designed so that the electron concentration at the heterojunction interface between the GaAs layer 7 and the non-doped AlGaAs layer 7 becomes approximately 1 × 10 ¹⁶ cm ⁻³ or less, a TMT device having good device characteristics can be stabilized. Can be manufactured.

As described above, in the TMT element of the present embodiment, since the non-doped GaAs layer 6 is provided between the n-type GaAs layer 5 and the non-doped AlGaAs layer 7,
Diffusion of dopant in n-type GaAs layer 5 and GaAs
Inter-diffusion of constituent elements at the heterojunction interface between AlGaAs and AlGaAs is suppressed, and defects due to vacancies are reduced. As a result, changes in the doping profile and conduction band edge profile due to the heat treatment are reduced, and the uniformity of the device characteristics and the reproducibility of the device characteristics within the wafer surface are improved, and the deterioration of the device characteristics due to the occurrence of defects is improved. Is also suppressed. Therefore, the error between the actual element characteristics and the design value is reduced, and a high-performance TMT element can be stably manufactured with good controllability.

In this embodiment, a non-doped GaAs layer is provided between the n-type GaAs layer 5 and the non-doped AlGaAs layer 7.
Although the s layer 6 is provided, instead of the non-doped GaAs layer 6, a low-concentration n-type G layer having a doping concentration of 10 ¹⁶ cm ⁻³ or less is used.
An aAs layer or a p-type GaAs layer may be provided. Also in this case, the electron concentration at the heterojunction interface is about 1 × 10 ¹⁶ c
m ^-3 as to become less than the low concentration n-type GaAs layer or p
By setting the film thickness of the type GaAs layer, the same effect as in the present embodiment can be obtained.

The semiconductor device of the present invention is not limited to a TMT device, but can be applied to other field effect transistors. FIG. 3 is a schematic sectional view showing the structure of an epitaxial growth substrate for a field effect transistor according to another embodiment of the present invention, and FIG. 4 is a schematic sectional view of the field effect transistor of the same embodiment using the epitaxial growth substrate of FIG. FIG.

In FIG. 3, the semi-insulating GaAs substrate 21
On top, a non-doped GaAs buffer layer 22 and n-type GaAs
An s channel layer 23, a non-doped GaAs layer 23a, and a non-doped AlGaAs barrier layer 24 are sequentially formed by epitaxial growth. The carrier concentration of the n-type GaAs channel layer 23 is, for example, 1 × 10 ¹⁸ cm ⁻³ .

In FIG. 4, a gate electrode 28 is formed at the center of the AlGaAs barrier layer 24 in Schottky contact with the AlGaAs barrier layer 24, and a source electrode 26 and a drain electrode 27 are formed on both sides of the gate electrode 28, respectively. ing. Immediately below the source electrode 26 and the drain electrode 27, n-type high conductive regions 25a and 25b into which Si is ion-implanted are formed, and are in ohmic contact with the source electrode 26 and the drain electrode 27.

In particular, the thickness of the non-doped GaAs layer 23a is the same as that of the non-doped GaAs layer 23a.
The electron concentration at the heterojunction interface with the As barrier layer 24 is set to be approximately 1 × 10 ¹⁶ cm ⁻³ or less.

In the field effect transistor of this embodiment, n
A non-doped GaAs layer 23a is provided between the GaAs channel layer 23 and the non-doped AlGaAs barrier layer 24 such that the electron concentration at the heterojunction interface between AlGaAs and GaAs is approximately 1 × 10 ¹⁶ cm ⁻³ or less. Therefore, even when a high-temperature heat treatment is performed when forming the n-type high conductive regions 25a and 25b, generation of vacancies near the interface of the hetero junction is suppressed. This suppresses the diffusion of the dopant in the n-type GaAs channel layer 23 and the interdiffusion of the constituent elements near the interface of the heterojunction, and reduces defects due to vacancies. As a result, changes in the doping profile and the conduction band edge profile due to high-temperature heat treatment are reduced, and the uniformity of device characteristics and the reproducibility of device characteristics within the wafer surface are improved. Deterioration is also suppressed. Therefore, the error between the actual device characteristics and the design value is reduced, and a high-performance field-effect transistor can be stably manufactured with good controllability.

In this embodiment, the non-doped GaAs layer 23a is provided between the n-type GaAs channel layer 23 and the non-doped AlGaAs layer 24.
Doping concentration of 10 ¹⁶ cm ^-3 instead of the aAs layer 23a
The following low-concentration n-type GaAs layer or p-type GaAs layer may be provided.

In the embodiments shown in FIGS. 2 and 4, the case where the present invention is applied to a field-effect transistor having an AlGaAs / n-type GaAs heterojunction has been described. However, the present invention relates to InGaP / n-type GaAs and AlGaAs. / N-type InGaAs, GaAs / n-type InGaAs, InGa
P / n-type InGaAs, InAlAs / n-type InGaAs
The present invention can be similarly applied to a field effect transistor having a heterojunction such as s, InP / n-type InGaAs or the like and other semiconductor elements, and the same effect as the above embodiment can be obtained.

In the embodiments shown in FIGS. 2 and 4, the case where the present invention is applied to a field-effect transistor having an n-type channel has been described. However, the present invention is also applicable to a semiconductor device having a p-type channel. Good.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of an epitaxial growth substrate for a field effect transistor according to one embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the structure of the field-effect transistor of the same example using the epitaxial growth substrate of FIG.

FIG. 3 is a schematic sectional view showing a structure of an epitaxial growth substrate for a field effect transistor according to another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the structure of the field-effect transistor of the same example using the epitaxial growth substrate of FIG.

FIG. 5 is a schematic sectional view showing the structure of a conventional epitaxial growth substrate for a field effect transistor.

6 is a schematic cross-sectional view showing a structure of a conventional field-effect transistor using the epitaxial growth substrate of FIG.

[Explanation of symbols]

 Reference Signs List 1 semi-insulating GaAs substrate 3 non-doped InGaAs layer 5 n-type GaAs layer 6 non-doped GaAs layer 7 non-doped AlGaAs layer 8a, 8b n-type high conductive region 23 n-type GaAs channel layer 23a non-doped GaAs layer 24 non-doped AlGaAs barrier layer 25a, 25b Mold high conductivity area

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Emi Fujii 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (5)

[Claims] The semiconductor device has a heterojunction between a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is doped with an impurity element of one conductivity type, and a carrier in the first semiconductor layer. Travels between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer is made of the same semiconductor material as the first semiconductor layer, and has a non-doped or carrier concentration of 10 ¹⁶ cm ⁻³ or less. 3. A semiconductor device, wherein the semiconductor device according to claim 3 is provided. 2. The method according to claim 1, wherein the first semiconductor layer has a higher electron affinity than the second semiconductor layer, the one conductivity type impurity element is an n-type impurity element, and the third semiconductor layer is 2. The semiconductor device according to claim 1, wherein the semiconductor element has an electron concentration of 10 ¹⁶ cm ^-3 or less in the vicinity of the interface with the second semiconductor layer. 3. The semiconductor device according to claim 1, wherein said first semiconductor layer, said second semiconductor layer, and said third semiconductor layer are made of a group III-V compound semiconductor. 4. The semiconductor device according to claim 1, wherein said first semiconductor layer and said third semiconductor layer are made of GaAs, and said second semiconductor layer is made of AlGa.
4. The semiconductor device according to claim 2, wherein the semiconductor device is made of As or InGaP. 5. The semiconductor device according to claim 2, wherein said first semiconductor layer and said third semiconductor layer are made of InGaAs, and said second semiconductor layer is made of GaAs, AlGaAs, InGaP, InAlAs or InP. 3
The semiconductor element as described in the above.