JPH07153779A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the performance of a hetero-junction FET by decreasing a parasitic capacitance and resistance of a gate electrode. CONSTITUTION:In a hetero-junction FET wherein a GaAs-made first barrier layer 3 and an AlGaAs-made second barrier layer 4 are piled up between a gate electrode 5a and a channel layer 2, the impurity concentration of the second barrier layer 4 except for a part just under the gate electrode 5a is made 5X10<17>/cm<3> or above by injecting impurities into the second barrier layer 4 by ion implantation self-alignedly with the gate electrode 5a.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a field effect transistor.
The present invention relates to (Field Effect Transistor; FET) and manufacturing technology thereof, and particularly to a technology effective when applied to high performance of a heterojunction FET formed on a compound semiconductor substrate.

[0002]

2. Description of the Related Art As a compound semiconductor integrated circuit device, a so-called GaAs semiconductor integrated circuit device in which FETs are integrated on a semi-insulating substrate such as GaAs (gallium arsenide) has been developed.

The GaAs • FET is superior in high speed because the electron moving speed is higher than that of the FET formed on the Si (silicon) substrate, and particularly, the GaAs • FET has a high impurity concentration between the channel region and the Schottky gate electrode. A heterojunction FET having a structure in which a barrier layer having a low impurity concentration and a large band gap is sandwiched therebetween is particularly excellent in high speed.

FIG. 9 is a sectional view showing the structure of a typical heterojunction FET formed on a GaAs substrate.

On the semi-insulating substrate 30 made of GaAs,
An n-type channel layer 31 having a high impurity concentration formed by an epitaxial growth method such as an MBE (Molecular Beam Epitaxy) method, and a barrier layer 32 made of AlGaAs having a low impurity concentration and a large band gap are provided.

[0006] On top of the barrier layer 32, a tungsten silicide (WSi _X) gate electrode 33 is provided made of, the gate electrode 33 and the self-aligned with the source, each of n-type impurity layer 34 of a drain, 34 are provided. Further, on each of the n-type impurity layers 34, the source and drain n ⁺ GaAs layers 35 formed by an epitaxial growth method such as MOCVD method.
And an ohmic electrode 36 made of AuGe alloy or the like is connected thereto.

The barrier layer 32 interposed between the channel layer 31 and the gate electrode 33 is in direct contact with the high impurity concentration channel layer 31 and the gate electrode 33, and the gate electrode 3 is formed.
It is provided to prevent the Schottky characteristic of No. 3 from deteriorating. In addition, a heterojunction F provided with this kind of barrier layer
Regarding ET, for example, "Extended Abstract of International Electron
Device Meeting (1988) (Extended Abst
ract of International Electron Devises Meeting (19
88) ”on page 692.

[0008]

In order to improve the performance of a transistor such as a heterojunction FET, the gate electrode may be miniaturized, but it is not possible to further miniaturize the gate electrode having a submicron gate length. However, there are processing limitations.

However, even if the dimensions of the intrinsic transistor portion such as the gate electrode and the channel layer are not changed, the performance can be improved by reducing the parasitic portion of the transistor. For that purpose, it is necessary to devise the structure of the transistor to reduce the parasitic capacitance and the parasitic resistance. For example, in the case of the heterojunction FET described above, in order to increase the impurity concentration of the source and drain and reduce the parasitic resistance, ion implantation is performed in self-alignment with the gate electrode.

However, according to a study made by the present inventor, when the ion implantation is performed in a self-aligned manner with the gate electrode, impurities are introduced into the immediate vicinity of the gate electrode, so that the parasitic capacitance of the gate electrode increases. , It turned out that it is not possible to achieve the expected high performance.

An object of the present invention is to provide a technique capable of improving the performance of a heterojunction FET by reducing the parasitic resistance without increasing the parasitic capacitance of the gate electrode.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In the heterojunction FET of the present invention, a barrier layer having a bandgap larger than that of the substrate is provided between the gate electrode and the channel layer, and impurities are ion-implanted into the barrier layer in self-alignment with the gate electrode. The impurity concentration of the barrier layer in the region except directly below the gate electrode is set to 5 × 10 ¹⁷ / cm ³ or more.

[0015]

According to the above means, by setting the impurity concentration of the barrier layer in the region excluding the region directly below the gate electrode to be 5 × 10 ¹⁷ / cm ³ or more, the carrier concentration in the lower portion of the barrier layer is high and the carrier concentration is high. Since a two-dimensional electron gas layer having high mobility can be formed, the parasitic resistance between the source / drain and the gate electrode can be reduced without increasing the parasitic capacitance of the gate electrode.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view of an essential part of a semi-insulating substrate showing an essential part of a heterojunction FET which is an embodiment of the present invention.

On the semi-insulating substrate 1 made of GaAs, n
A channel layer 2 made of GaAs is formed.
A first barrier layer 3 made of GaAs and a second barrier layer 4 made of AlGaAs are sequentially stacked on the channel layer 2, and a gate electrode made of a tungsten silicide film is formed on the second barrier layer 4. 5a is formed.
Further, n ⁺ GaAs layers 6 forming a source and a drain are formed on both sides of the gate electrode 5a, and an ohmic electrode 7 is further formed on each n ⁺ GaAs layer 6.

The impurity concentration of the first barrier layer 3 is 1 × 10 ¹⁷ / cm ³ or less. The second barrier layer 4 has a bandgap larger than that of the semi-insulating substrate 1, and the impurity concentration in the region immediately below the gate electrode 5a is 1 × 1.
Although it is 0 ¹⁷ / cm ³ or less, the impurity concentration in the region excluding directly under the gate electrode 5a is 5 × 10 ¹⁷ / cm ³ or more. A two-dimensional electron gas layer 8 which becomes a conductive layer by supplying electrons from impurities in the second barrier layer 4 during the operation of the FET is provided below the second barrier layer 4 except directly below the gate electrode 5a.
Exists.

Next, a method of manufacturing the heterojunction FET will be described with reference to FIGS.

First, as shown in FIG. 2, the semi-insulating substrate 1
A channel layer 2 made of n-type GaAs, a first barrier layer 3 made of GaAs, and Al by molecular beam epitaxy.
After the second barrier layer 4 made of GaAs is sequentially epitaxially grown, the tungsten silicide film 5 is deposited on the second barrier layer 4 by the sputtering method.

The channel layer 2 has a film thickness of about 20 nm,
The impurity concentration is about 3 × 10 ¹⁸ / cm ³ , the thickness of the first barrier layer 3 is about 2 to 5 nm, and the thickness of the second barrier layer 4 is about 10 to 20 nm. The film thickness of the tungsten silicide film 5 is about 300 to 500 nm.

Next, as shown in FIG. 3, the tungsten silicide film 5 is etched by using the photoresist 9 as a mask to form the gate electrode 5a, and then the second barrier layer 4 is formed as shown in FIG. Ion implantation of n-type impurities (for example, Si) is performed. At this time, the energy of ion implantation is optimized so that only the second barrier layer 4 is doped with impurities. For example, when the film thickness of the second barrier layer 4 is about 20 nm, SiF ₂ is used as the ion source and 10 k
Ion implantation is performed with energy of eV.

Next, to prevent the impurities from diffusing into the first barrier layer 3, high-speed annealing is performed at 800 ° C. for 5 seconds to activate the impurities, so that the second barrier layer 4 and the second barrier layer 4 are formed as shown in FIG. The two-dimensional electron gas layer 8 is formed at the interface with the first barrier layer 3.
Is formed.

Next, as shown in FIG. 6, by selective epitaxial growth using the MOCVD method on the second barrier layer 4, for example, the impurity concentration is about 3 × 10 ¹⁸ / cm and the film thickness is about 250 nm. ⁺ GaAs layer 6 is formed, then
An AuGe alloy is deposited on the n ⁺ GaAs layer 6 and heat-treated at about 400 ° C. for 2 minutes to form an ohmic electrode 7, whereby the heterojunction FET shown in FIG. 1 is substantially completed.

FIG. 7 is a band diagram in the BB 'cross section of FIG. In addition, the AA ′ cross section of FIG. 1 (gate electrode 5
A band diagram (immediately below a) is shown in FIG. 8 for comparison.

As is apparent from FIG. 7, in the heterojunction FET of this embodiment, the number of donor ions in the second barrier layer 4 between the gate electrode 5a and the n ⁺ GaAs layer 6 is small and the depletion layer spreads. Therefore, the parasitic capacitance at the end of the gate electrode 5a is small. However, the two-dimensional electron gas layer 8 exists at the end of the gate electrode 5a, and although the number of donor ions is small, the number of carriers in the portion where the current flows is large, and the mobility of carriers in the two-dimensional electron gas layer 8 is further increased. Is big. Therefore,
The parasitic resistance between the gate electrode 5a and the source / drain (n ⁺ GaAs layer 6) is extremely low, and the high-performance heterojunction FET has low parasitic capacitance and low parasitic resistance.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-mentioned embodiment, the performance improvement of the heterojunction FET formed on the semi-insulating substrate made of GaAs has been described. For example, AlGaAs, InGaAs,
It can also be applied to improve the performance of a heterojunction FET formed on a semi-insulating substrate made of another compound semiconductor such as InP.

[0030]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, since the parasitic resistance and the parasitic capacitance of the heterojunction FET formed on the semi-insulating substrate made of a compound semiconductor can be reduced at the same time, a high-performance compound semiconductor integrated circuit device is realized. be able to.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semi-insulating substrate showing a heterojunction FET according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semi-insulating substrate showing a method for manufacturing a heterojunction FET which is an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semi-insulating substrate showing a method for manufacturing a heterojunction FET which is an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semi-insulating substrate showing a method of manufacturing a heterojunction FET which is an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semi-insulating substrate showing a method for manufacturing a heterojunction FET which is an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semi-insulating substrate showing a method for manufacturing a heterojunction FET which is an embodiment of the present invention.

FIG. 7 is a band diagram in a B-B ′ cross section of FIG. 1.

FIG. 8 is a band diagram in the A-A ′ cross section of FIG. 1.

FIG. 9 is a cross-sectional view of essential parts of a semi-insulating substrate showing a conventional heterojunction FET.

[Explanation of symbols]

1 semi-insulating substrate 2 channel layer 3 first barrier layer 4 second barrier layer 5 tungsten silicide film 5a gate electrode 6 n ⁺ GaAs layer 7 ohmic electrode 8 two-dimensional electron gas layer 9 photoresist 30 semi-insulating substrate 31 Channel layer 32 Barrier layer 33 Gate electrode 34 n-type impurity layer 35 n ⁺ GaAs layer 36 Ohmic electrode

Claims (5)

[Claims] 1. A channel layer and a barrier layer having a low impurity concentration and a bandgap larger than that of the semi-insulating substrate are sequentially stacked on a semi-insulating substrate made of a compound semiconductor, and the barrier layer is formed on the barrier layer. A field effect transistor having a high impurity concentration layer of a source and a drain on an impurity layer formed in self-alignment with the Schottky gate electrode, which is directly below the Schottky gate electrode. A field effect transistor, characterized in that the impurity concentration of the barrier layer in the region excluding the region is 5 × 10 ¹⁷ / cm ³ or more. 2. A semi-insulating substrate made of a compound semiconductor, a channel layer having an impurity concentration of 5 × 10 ¹⁷ / cm ³ or more, and a first barrier layer having an impurity concentration of 1 × 10 ¹⁷ / cm ³ or less,
A second barrier layer having an impurity concentration of 1 × 10 ¹⁷ / cm ³ or less and having a bandgap larger than that of the semi-insulating substrate is sequentially laminated, and a Schottky gate electrode is formed on the second barrier layer. A high-impurity concentration layer of a source and a drain is provided on an impurity layer formed in self-alignment with the Schottky gate electrode, and the field effect transistor is provided in a region excluding a region right below the Schottky gate electrode. The impurity concentration of the second barrier layer is 5 × 10 ¹⁷ / cm ³
A field effect transistor characterized by the above. 3. The field effect transistor according to claim 1, wherein the semi-insulating substrate and the channel layer are each made of GaAs, and the barrier layer having a large band gap is made of AlGaAs. 4. The semi-insulating substrate is made of GaAs,
The channel layer is made of InGaAs, and the barrier layer having a large band gap is GaAs or AlGaAs.
The field effect transistor according to claim 1 or 2, comprising: 5. A method for manufacturing a field effect transistor, which comprises the following steps (a) to (c). (a) A step of sequentially epitaxially growing a channel layer and a barrier layer having a low impurity concentration and a bandgap larger than that of the semi-insulating substrate on a semi-insulating substrate made of a compound semiconductor by the MBE method. (b) The barrier layer is formed by etching a conductive film deposited on the barrier layer to form a Schottky gate electrode, and then ion-implanting impurities into the barrier layer using the Schottky gate electrode as a mask. The impurity concentration of 5 × 10 ¹⁷ / cm ³ or more. (c) A step of epitaxially growing a high impurity concentration layer of a source and a drain on the barrier layer by MOCVD, and then forming an ohmic electrode on the high impurity concentration layer.