JPH0472381B2 - - Google Patents

Info

Publication number
JPH0472381B2
JPH0472381B2 JP57226602A JP22660282A JPH0472381B2 JP H0472381 B2 JPH0472381 B2 JP H0472381B2 JP 57226602 A JP57226602 A JP 57226602A JP 22660282 A JP22660282 A JP 22660282A JP H0472381 B2 JPH0472381 B2 JP H0472381B2
Authority
JP
Japan
Prior art keywords
recess
gate electrode
insulating film
layer
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57226602A
Other languages
Japanese (ja)
Other versions
JPS59119765A (en
Inventor
Kinshiro Kosemura
Yoshimi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22660282A priority Critical patent/JPS59119765A/en
Publication of JPS59119765A publication Critical patent/JPS59119765A/en
Publication of JPH0472381B2 publication Critical patent/JPH0472381B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8128Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate

Description

【発明の詳細な説明】 (1) 発明の分野 本発明は、電界効果型半導体装置に関し、特に
ガリウム砒素(GaAs)化合物半導体のシヨツト
キゲート電界効果トランジスタ(SBFET)に製
造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a field effect semiconductor device, and particularly to a method for manufacturing a shot gate field effect transistor (SBFET) made of a gallium arsenide (GaAs) compound semiconductor.

(2) 技術の背景 GaAsシヨツトキゲート電界効果トランジスタ
は高周波特性が優れかつ高出力化が図れるので、
研究開発が進み実用化されつつある。特に、この
電界効果トランジスタの高性能化(高周波化、高
出力化、高効率化)および高信頼性化のために
種々の構造および製造方法が提案されている。高
性能化のためには、ゲート長の短縮化および寄生
抵抗であるソース・ゲート間抵抗(ソース直列抵
抗Rs)およびゲート抵抗(Rg)の低減化などが
重要である。
(2) Technical background GaAs shot gate field effect transistors have excellent high frequency characteristics and can achieve high output.
Research and development is progressing and it is being put into practical use. In particular, various structures and manufacturing methods have been proposed to improve the performance (higher frequency, higher output, higher efficiency) and reliability of this field effect transistor. In order to improve performance, it is important to shorten the gate length and reduce parasitic resistances such as source-gate resistance (source series resistance R s ) and gate resistance (R g ).

(3) 従来技術と問題点 GaAsシヨツトキゲート電界効果トランジスタ
の高性能化の方法としてゲート電極部分でのリセ
ス(凹所)構造が提案されている。第1図に示す
ようにリセス4はGaAs基板1上にエピタキシヤ
ル連続成長させたバツフア層2上の活性層3を選
択エツチングすることによつて形成され、そのリ
セス深さはゲート電極5直下の能動膜厚さが最適
値となるように設定される。また、ゲート長を単
に短かくするとゲート抵抗Rgの増加を招くので、
ゲート電極厚さを増すことでゲート抵抗の低減化
を図ることになる。そうするとゲート電極5と活
性層3との接触面積が減つてゲート電極5の高さ
が高くなるわけで、例えば、洗浄工程においてゲ
ート電極5が剥離しやすくなる。一般的には、微
細加工に適した電子線リソグラフイで第1図に示
すように電子ビーム露光用レジスト層6をマスク
としてエツチングによりリセス4を形成し、次に
金属蒸着膜7を全面に形成し、このときリセス4
にゲート電極5を形成する。そして、レジスト層
6を除去すると同時にその上の金属蒸着膜7も除
去する(いわゆるリフトオフ法である)。リセス
4とゲート電極5とはセルフアライン的に形成さ
れかつレジスト層の形成が1回で済むので製造工
程的には有利である。しかしながら、ポジ形レジ
ストを電子ビーム露光するので、現像されてでき
る窓(透孔)はありみぞ的形状になつて、リセス
幅がゲート電極幅より大きくなつてしまう(第1
図)。そのために、リセス4によつて薄くされた
活性層3部分がゲート電極の両側にあつて、この
部分では活性層の直列抵抗が大きいためにソー
ス・ゲート間抵抗(Rs)の低減化が図れない。
(3) Prior art and problems A recessed structure in the gate electrode has been proposed as a method for improving the performance of GaAs shot gate field effect transistors. As shown in FIG. 1, the recess 4 is formed by selectively etching the active layer 3 on the buffer layer 2 that has been epitaxially and continuously grown on the GaAs substrate 1, and the recess depth is set just below the gate electrode 5. The active membrane thickness is set to an optimum value. Also, simply shortening the gate length will result in an increase in gate resistance R g .
By increasing the thickness of the gate electrode, it is possible to reduce the gate resistance. In this case, the contact area between the gate electrode 5 and the active layer 3 decreases, and the height of the gate electrode 5 increases, making it easier for the gate electrode 5 to peel off during a cleaning process, for example. Generally, as shown in FIG. 1, a recess 4 is formed by etching using an electron beam exposure resist layer 6 as a mask using electron beam lithography suitable for microfabrication, and then a metal vapor deposition film 7 is formed on the entire surface. At this time, recess 4
A gate electrode 5 is formed thereon. Then, at the same time as removing the resist layer 6, the metal vapor deposited film 7 thereon is also removed (this is a so-called lift-off method). The recess 4 and the gate electrode 5 are formed in a self-aligned manner, and the resist layer only needs to be formed once, which is advantageous in terms of manufacturing process. However, since the positive resist is exposed to electron beam, the developed window (through hole) has a dovetail-like shape, and the recess width is larger than the gate electrode width (the first
figure). For this reason, the active layer 3 parts thinned by the recess 4 are on both sides of the gate electrode, and since the series resistance of the active layer is large in these parts, it is difficult to reduce the source-gate resistance (R s ). do not have.

(4) 発明の目的 本発明の目的は、リセス構造のGaAsシヨツト
キゲート電界効果トランジスタにおいてゲート長
を短かくしてもゲート電極の剥離が生ぜず、また
リセスによつて薄くされた活性層でのソース・ド
レイン間抵抗の低減化を図り、超高周波で高性能
動作するGaAsシヨツトキゲート電界効果トラン
ジスタの半導体装置の製造方法を提供することで
ある。
(4) Purpose of the Invention The purpose of the present invention is to prevent peeling of the gate electrode even if the gate length is shortened in a GaAs shot gate field effect transistor with a recessed structure, and to prevent separation of the source and drain in the active layer thinned by the recess. It is an object of the present invention to provide a method for manufacturing a semiconductor device of a GaAs shot gate field effect transistor which reduces the inter-resistance and operates with high performance at ultra-high frequencies.

(5) 発明の構成 本発明の目的は、半導体活性層上に、絶縁膜と
第1のマスク層とを順次積層し、該第1のマスク
層のゲート電極形成予定領域に対応する部分に開
口を形成し、次いで該第1のマスク層をマスクと
して該絶縁膜を選択的に除去して該絶縁膜に開口
窓を形成し、該第1のマスク層を除去してから第
2マスク層を積層し、該第2のマスク層に該開口
窓よりも大きくかつ該開口窓を表出させている開
口部を形成し、更に該絶縁膜をマスクとして該半
導体活性層を所定の深さまでエツチング除去して
リセスを形成し、該開口部内で該リセスおよび該
リセス周辺の該絶縁膜上にゲート電極となる金属
を被着する工程を含んでなることを特徴とする半
導体装置の製造方法によつて達成される。
(5) Structure of the Invention An object of the present invention is to sequentially stack an insulating film and a first mask layer on a semiconductor active layer, and to form an opening in a portion of the first mask layer corresponding to a region where a gate electrode is to be formed. forming an opening window in the insulating film by selectively removing the insulating film using the first mask layer as a mask, removing the first mask layer, and then forming a second mask layer. forming an opening in the second mask layer that is larger than the opening window and exposing the opening window, and further etching the semiconductor active layer to a predetermined depth using the insulating film as a mask; A method for manufacturing a semiconductor device, comprising the steps of: forming a recess in the opening, and depositing a metal serving as a gate electrode on the recess and the insulating film around the recess within the opening. achieved.

本発明の製造方法によると、絶縁膜に設けた開
口窓を通してのエツチングによつてリセスが形成
され、ゲート電極が真空蒸着法又はスパツタリン
グ法で開口窓を通してリセス上に同時に絶縁膜上
に形成した導体層から作られることになる。
According to the manufacturing method of the present invention, the recess is formed by etching through the opening window provided in the insulating film, and the gate electrode is made of a conductor simultaneously formed on the insulating film on the recess through the opening window by vacuum evaporation or sputtering. It will be made up of layers.

(6) 発明の実施態様 以下、添付図面を参照して本発明の実施態様例
によつて本発明を詳しく説明する。
(6) Embodiments of the invention The present invention will be described in detail below by way of embodiments of the invention with reference to the accompanying drawings.

第2図に示すように、半絶縁性GaAs基板11
上に気相又は液相エピタキシヤル連続成長法でノ
ンドープのバツフア層12(厚さ:3〜5μm)
そして活性層13(能動層、厚さ:0.1〜0.5μm)
を形成する。なお、この活性層の不純物濃度は1
〜3×1017個/cm3である。次に、AuGe(Ge:
12wt%)およびAuの連続蒸着膜をフオトエツチ
ング法又はリフトオフ法で所定パターン形状にし
て活性層3上にソース電極14およびドレイン電
極15を形成する。約450℃のアニール熱処理に
よつてこれら電極14および15をオーミツクコ
ンタクト(オーム性接触)にする。
As shown in FIG. 2, a semi-insulating GaAs substrate 11
A non-doped buffer layer 12 (thickness: 3 to 5 μm) is formed on top using a continuous vapor phase or liquid phase epitaxial growth method.
And active layer 13 (active layer, thickness: 0.1 to 0.5 μm)
form. Note that the impurity concentration of this active layer is 1
~3×10 17 pieces/cm 3 . Then AuGe(Ge:
12 wt%) and Au are formed into a predetermined pattern by photoetching or lift-off to form a source electrode 14 and a drain electrode 15 on the active layer 3. These electrodes 14 and 15 are brought into ohmic contact by annealing at about 450°C.

次に、第3図に示すように、絶縁膜16(厚さ
0.1〜0.2μm)をスパツタ法、減圧気相成長法
(CVD法)などによつて全面に形成する。このと
き、絶縁膜16は二酸化珪素(SiO2)で構成す
ることにする。この絶縁膜16上に第1のマイク
層のレジスト層17を形成し、電子ビーム露光に
より形成すべきゲート電極パターンのありみぞ的
形状の開口(孔)18を形成する。このレジスト
層17には市販の電子ビーム露光用ポジレジスト
を用い、孔18の上面側での幅をゲート電極の幅
(すなわち、ゲート長)に相当する0.2〜0.5μmと
する。
Next, as shown in FIG.
0.1 to 0.2 μm) is formed over the entire surface by sputtering, reduced pressure vapor deposition (CVD), or the like. At this time, the insulating film 16 is made of silicon dioxide (SiO 2 ). A resist layer 17 of a first microphone layer is formed on this insulating film 16, and a dovetail-shaped opening (hole) 18 of a gate electrode pattern to be formed is formed by electron beam exposure. A commercially available positive resist for electron beam exposure is used for this resist layer 17, and the width of the hole 18 on the upper surface side is set to 0.2 to 0.5 μm, which corresponds to the width of the gate electrode (ie, gate length).

次に、このレジスト層17をマスクとして二酸
化珪素からなる絶縁膜16をCHF3ガスを使用し
たドライエツチング法によつて異方性的に選択エ
ツチングして開口窓19を開ける(第4図)。こ
の開口窓の幅は0.2〜0.5μmとなる。絶縁膜のみ
を選択エツチングする際のレジスト層であるの
で、薄く形成することができ、開口がありみぞ的
になつても、その下方拡大は小さく、異方性エツ
チングで開口がほとんど拡大することもなく、レ
ジスト層の開口サイズがほぼそのまま絶縁膜の開
口窓のサイズである。そして、レジスト層17を
除去する。
Next, using this resist layer 17 as a mask, the insulating film 16 made of silicon dioxide is selectively etched anisotropically by a dry etching method using CHF 3 gas to open an opening window 19 (FIG. 4). The width of this opening window is 0.2 to 0.5 μm. Since this is a resist layer used when selectively etching only the insulating film, it can be formed thinly, and even if there is an opening in the form of a groove, its downward expansion is small, and the opening can be almost enlarged by anisotropic etching. The size of the opening in the resist layer is almost exactly the size of the opening window in the insulating film. Then, the resist layer 17 is removed.

第5図に示すように、第2のマスク層である別
のレジスト層20をレジスト層17と同じポジレ
ジストで形成し、電子ビーム露光により、該レジ
スト層20に開口窓19に対応した孔21を形成
する。このとき、この孔21の上面側での幅を
0.5〜1.0μmとする。即ち開口窓19よりも幅の
広い開口部を形成する。
As shown in FIG. 5, another resist layer 20 as a second mask layer is formed of the same positive resist as the resist layer 17, and holes 20 corresponding to the opening windows 19 are formed in the resist layer 20 by electron beam exposure. form. At this time, the width on the top side of this hole 21 is
Set to 0.5 to 1.0 μm. That is, an opening wider than the opening window 19 is formed.

レジスト層20および絶縁膜16をマスクとし
て活性層13を弗酸・過酸化水素混合水溶液でエ
ツチングしてリセス22を形成する(第6図)。
このとき、リセス22の深さが電界効果トランジ
スタの設定特性から決められる値となるようにす
る。絶縁膜16の下で開口窓19の付近の活性層
13もアンダーカツトとして第6図のようにエツ
チングされる。
Using the resist layer 20 and the insulating film 16 as a mask, the active layer 13 is etched with a mixed aqueous solution of hydrofluoric acid and hydrogen peroxide to form a recess 22 (FIG. 6).
At this time, the depth of the recess 22 is set to a value determined from the set characteristics of the field effect transistor. The active layer 13 in the vicinity of the opening window 19 under the insulating film 16 is also etched as an undercut as shown in FIG.

次に、GaAs基板11に対してほぼ垂直な方向
からシヨツトキバリア特性のゲート電極を構成す
る金属(アルミニウム)を蒸着法又はスパツタ法
で全面に飛着させて、レジスト層20上に金属膜
23を同時にレジスト層20の開口部(孔)21
内にゲート電極24を形成する(第7図)。
Next, a metal (aluminum) constituting a gate electrode with shot barrier properties is deposited on the entire surface of the GaAs substrate 11 in a direction substantially perpendicular to it by vapor deposition or sputtering, thereby simultaneously forming a metal film 23 on the resist layer 20. Openings (holes) 21 in the resist layer 20
A gate electrode 24 is formed inside (FIG. 7).

レジスト層20を除去することによつてその上
の金属膜23をも除去して、第8図に示すように
GaAsシヨツトキゲート電界効果トランジスタが
得られる。このトランジスタにおいて、ゲート電
極24は絶縁膜16に設けられた開口窓19を通
して活性層13のリセス(凹所)内にまで伸びて
おり、ゲート長が窓19(第6図)によつて規定
されている。また、リセス22(第6図)の形成
においても開口窓19がリセス22の幅を規定さ
れているので、ゲート電極24はリセス22のほ
ぼ全体(アンダーカツト部分を除いて)を埋める
ことになり、したがつて、従来の電界効果トラン
ジスタで問題となつたリセスによつて薄くなつた
活性層部分がないためにそれだけソース・ゲート
間抵抗を下げることができる。さらに、ゲート電
極24は絶縁膜16の上にも載つているので、ゲ
ート電極24の下面の付着面積が大きくなり剥離
しにくくなる。しかも、第8図から明らかなよう
にゲート電極24の体積を従来の場合よりも大き
くすることができるのでゲート抵抗が小さくな
る。
By removing the resist layer 20, the metal film 23 thereon is also removed, as shown in FIG.
A GaAs shot gate field effect transistor is obtained. In this transistor, the gate electrode 24 extends into the recess (concavity) of the active layer 13 through an opening window 19 provided in the insulating film 16, and the gate length is defined by the window 19 (FIG. 6). ing. Furthermore, in forming the recess 22 (FIG. 6), the width of the recess 22 is defined by the opening window 19, so the gate electrode 24 fills almost the entire recess 22 (excluding the undercut portion). Therefore, since there is no active layer portion thinned by a recess, which is a problem in conventional field effect transistors, the source-gate resistance can be reduced accordingly. Further, since the gate electrode 24 is also placed on the insulating film 16, the adhesion area on the lower surface of the gate electrode 24 becomes large, making it difficult to peel off. Moreover, as is clear from FIG. 8, the volume of the gate electrode 24 can be made larger than in the conventional case, so that the gate resistance is reduced.

(7) 発明の効果 本発明の製造方法に従つて製造したGaAsシヨ
ツトキゲート電界効果トランジスタは特に小信号
用(低雑音用)のトランジスタとして使用でき、
また製造方法として同一導電型のヘテロ接合を有
する高移動度トランジスタ、例えば、HEMTに
も適用できる。
(7) Effects of the invention The GaAs shot gate field effect transistor manufactured according to the manufacturing method of the invention can be used particularly as a small signal (low noise) transistor,
The manufacturing method can also be applied to high mobility transistors having heterojunctions of the same conductivity type, such as HEMTs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の電界効果型半導体装置の製造工
程の一部を示した半導体装置の概略断面図であ
り、第2図ないし第8図は、本発明に係る電界効
果半導体装置の製造方法を説明する製造工程での
電界効果型半導体装置の概略断面図である。 1……GaAs基板、3……活性層、4……リセ
ス(凹所)、5……ゲート電極、11……GaAs
基板、13……活性層、14……ソース電極、1
5……ドレイン電極、16……絶縁膜、17……
レジスト層、18……開口(孔)、19……開口
窓、20……レジスト層、21……開口部、23
……金属膜、24……ゲート電極。
FIG. 1 is a schematic cross-sectional view of a semiconductor device showing a part of the manufacturing process of a conventional field effect semiconductor device, and FIGS. 2 to 8 show a method of manufacturing a field effect semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view of a field-effect semiconductor device in a manufacturing process to be described. 1...GaAs substrate, 3...Active layer, 4...Recess (concave), 5...Gate electrode, 11...GaAs
Substrate, 13... Active layer, 14... Source electrode, 1
5...Drain electrode, 16...Insulating film, 17...
Resist layer, 18... Opening (hole), 19... Opening window, 20... Resist layer, 21... Opening, 23
...metal film, 24...gate electrode.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体活性層13上に、絶縁膜16と第1の
マスク層17とを順次積層し、前記第1のマスク
層17のゲート電極形成予定領域に対応する部分
に開口18を形成し、次いで前記第1のマスク層
17をマスクとして前記絶縁層を選択的に除去し
て前記絶縁膜16に開口窓19を形成し、前記第
1のマスク層を除去してから第2マスク層20を
積層し、該第2のマスク層に前記開口窓19より
も大きくかつ該開口窓を表出させている開口部2
1を形成し、更に前記絶縁膜16をマスクとして
前記半導体活性層13を所定の深さまでエツチン
グ除去してリセス22を形成し、前記開口部21
内で該リセス22および該リセス周辺の前記絶縁
膜16上にゲート電極24となる金属を被着する
工程を含んでなることを特徴とする半導体装置の
製造方法。
1. An insulating film 16 and a first mask layer 17 are sequentially stacked on the semiconductor active layer 13, an opening 18 is formed in a portion of the first mask layer 17 corresponding to a region where a gate electrode is to be formed, and then the The insulating layer is selectively removed using the first mask layer 17 as a mask to form an opening window 19 in the insulating film 16, and a second mask layer 20 is laminated after removing the first mask layer. , an opening 2 in the second mask layer that is larger than the opening window 19 and exposes the opening window.
1 is formed, and then the semiconductor active layer 13 is etched and removed to a predetermined depth using the insulating film 16 as a mask to form a recess 22.
A method for manufacturing a semiconductor device, comprising the step of depositing metal to become a gate electrode 24 on the recess 22 and the insulating film 16 around the recess.
JP22660282A 1982-12-27 1982-12-27 Manufacture of field effect type semiconductor device Granted JPS59119765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22660282A JPS59119765A (en) 1982-12-27 1982-12-27 Manufacture of field effect type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22660282A JPS59119765A (en) 1982-12-27 1982-12-27 Manufacture of field effect type semiconductor device

Publications (2)

Publication Number Publication Date
JPS59119765A JPS59119765A (en) 1984-07-11
JPH0472381B2 true JPH0472381B2 (en) 1992-11-18

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JP22660282A Granted JPS59119765A (en) 1982-12-27 1982-12-27 Manufacture of field effect type semiconductor device

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JP (1) JPS59119765A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700462A (en) * 1986-10-08 1987-10-20 Hughes Aircraft Company Process for making a T-gated transistor
JPH01274477A (en) * 1988-04-26 1989-11-02 Fujitsu Ltd Manufacture of semiconductor device
JPH0265141A (en) * 1988-08-30 1990-03-05 Sanyo Electric Co Ltd Manufacture of semiconductor device
JP2550412B2 (en) * 1989-05-15 1996-11-06 ローム株式会社 Method for manufacturing field effect transistor
JP2667250B2 (en) * 1989-06-15 1997-10-27 松下電子工業株式会社 Method for manufacturing semiconductor device
KR920007357B1 (en) * 1990-03-12 1992-08-31 재단법인 한국전자통신연구소 Method of manufacturing a gaas semiconductor device
JP2655488B2 (en) * 1994-09-29 1997-09-17 日本電気株式会社 Method for manufacturing semiconductor device
JP4752163B2 (en) * 2001-09-21 2011-08-17 日立電線株式会社 Method for manufacturing field effect transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194373A (en) * 1982-05-10 1983-11-12 Nec Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194373A (en) * 1982-05-10 1983-11-12 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS59119765A (en) 1984-07-11

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