JP2000223504A - Field-effect semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect transistor having a T-shaped gate electrode, together with its manufacturing method which has a reduced source resistance, a reduced gate resistance, and a reduced gate capacitance while keeping a sufficient gate breakdown voltage, and which can be manufactured with high accuracy and a high yield. SOLUTION: A first doped layer 6 of n-GaAs, a side-etching prevention layer 7 of Al0.22Ga0.78As, and a second doped layer 8 of n-GaAs, are sequentially grown on a layer 5 of n-Al0.22Ga0.78As. A recess is formed in a central region of the second doped layer 8, the side-etching prevention layer 7 and the first doped layer 6, so as to expose the layer 5 of n-Al0.22Ga0.78As there. On the exposed layer 5 of n-Al0.22Ga0.78As in the recess, a T-shaped gate electrode is formed. The etching rate of the side-etching pretension layer 7 is smaller than those of the first and the second doped layers 6 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field-effect semiconductor device having a T-type gate electrode and a recess structure, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A heterojunction MESFET (metal-semiconductor field effect transistor) using a compound semiconductor such as GaAs has recently been used as a semiconductor device for microwave and millimeter wave bands because of its high electron mobility. It is applied in various fields.

In general, in order to improve the performance of the above-mentioned FET, it is required to improve the accuracy of the gate length, to reduce the parasitic resistance of the source and the gate, and to obtain a sufficient gate breakdown voltage.

In order to satisfy these requirements, various self-alignment processes have been developed. In addition, a step-like recess (recess) structure using an etching technique is adopted,
The source resistance is reduced. Further, in order to reduce the gate resistance, a T-type gate electrode using a patterning technique is used.

FIGS. 4 and 5 are schematic sectional views showing the steps of a method for manufacturing a conventional FET. Hereinafter, FIGS. 4 and 5
A conventional method for manufacturing an FET will be described with reference to FIG.

[0006] First, as shown in FIG.
An undoped GaAs having a thickness of 800 nm is formed on a substrate 21.
Buffer layer 22, 10-nm thick undoped In_0.2
Ga _0.8As layer 23, undoped Al 2 nm thick
_0.22Ga_0.78As layer 24, 35 nm thick Si-doped
n-Al_0.22Ga_0.78As layer 25, 20 nm thick Si
Doped n-GaAs layer 26 and 50 nm thick Si
Epitaxial growth of doped n-GaAs layer 27 in order
Let it. n-Al_0.22Ga_0.78The electron concentration of the As layer 25 is
2 × 10¹⁸cm^-3And the electron concentration of the n-GaAs layer 26.
The degree is 7 × 10¹⁷cm^-3And the voltage of the n-GaAs layer 27 is
Child concentration is 3 × 10¹⁸cm^-3It is.

Next, a photoresist is formed in a predetermined region on the n-GaAs layer 27, and etching is performed using a tartaric acid-based etchant to form a mesa pattern (trapezoidal pattern; not shown). Thereafter, the photoresist is removed.

Subsequently, a photoresist having openings in the source electrode formation region and the drain electrode formation region on the n-GaAs layer 27 is formed, and an AuGe film, a Ni film and an Au film are sequentially vacuum-deposited, and lift-off method is used. The AuGe film, the Ni film and the Au film on the photoresist are removed together with the photoresist to form a source electrode 28 and a drain electrode 29. Further, the source electrode 28 and the drain electrode 29 are heat-treated at 400 ° C. for 2 minutes to perform alloying.

Next, as shown in FIG.
A photoresist 31 having an opening 32 in a gate electrode formation region on the As layer 27 is formed.

Next, as shown in FIG. 4C, a phosphoric acid-based etchant (phosphoric acid: hydrogen peroxide: water = 2: 1: 4)
Using 0), the n-GaAs layer 27 and the n-GaAs layer 26 are partially etched. Etching time is 3
0 seconds. In this case, the n-GaAs layer 27 and the n-
The GaAs layer 26 is etched in the depth direction and side-etched in the lateral direction.

Subsequently, as shown in FIG.
_The n-GaAs layer 26 is etched by the RIE method (reactive ion etching method) using a mixed gas of ₂ and SF ₆ using the photoresist 31 as a mask to form a two-step recess structure.

Thereafter, as shown in FIG. 5E, n-Al _0.22 Ga on the photoresist 31 and in the opening 32 is formed.
_{On the 0.78} As layer 25, a gate electrode layer 30a made of a Ti film, a Pd film, and an Au film is formed by vacuum evaporation.

After that, the gate electrode layer 30a on the photoresist 31 is removed together with the photoresist 31 by a lift-off method to form a T-type gate electrode 30 as shown in FIG.

[0014]

However, since the umbrella portion of the T-type gate electrode 30 is in contact with the n-GaAs layer 26, the gate capacitance increases and the high-frequency characteristics deteriorate. In addition, there is a problem that the dimensions of the umbrella portion of the T-type gate electrode 30 cannot be accurately controlled, and the yield does not improve.

An object of the present invention is to reduce source resistance, improve gate breakdown voltage, and reduce gate resistance.
An object of the present invention is to provide a field-effect semiconductor device having a T-type gate electrode that can be formed with high precision and high yield while reducing gate capacitance, and a method for manufacturing the same.

[0016]

According to the field effect type semiconductor device of the present invention, a second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer are sequentially formed on a first semiconductor layer. A recess is formed in the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer such that the first semiconductor layer is exposed, and an umbrella portion and a foot are formed on the first semiconductor layer in the recess. A T-shaped gate electrode consisting of a portion is formed, and a second
A gap is formed between the side surface of the semiconductor layer and the side surface of the foot portion of the gate electrode, the side surface of the third semiconductor layer contacts the side surface of the foot portion of the gate electrode in the concave portion, and the umbrella portion of the gate electrode forms the 3 extending to the upper surface of the semiconductor layer.

In the field effect type semiconductor device according to the present invention, since the recess structure is formed by the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer, the source resistance can be reduced and the gate breakdown voltage can be reduced. Improvement is achieved. Also, T
Gate resistance can be reduced by the umbrella portion of the gate electrode. Further, since a gap is formed below the umbrella portion of the gate electrode, the gate capacitance is reduced. Therefore,
The element characteristics are improved. Further, since the size of the foot of the T-type gate electrode corresponding to the gate length is defined by the distance between the third semiconductor layers in the concave portion, it is possible to form the T-type gate electrode with high accuracy and high yield. Become.

In particular, it is preferable that the second semiconductor layer and the fourth semiconductor layer have an etching rate higher than that of the third semiconductor layer.

In this case, when the concave portions are formed in the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer, the side etching amount of the second semiconductor layer and the fourth semiconductor layer is set to the third level. It becomes larger than the side etching amount of the semiconductor layer. Thereby, a gap is formed between the side surface of the second semiconductor layer and the side surface of the foot portion of the gate electrode in the recess when the gate electrode is formed, and the foot of the gate electrode is formed in the recess in the side surface of the third semiconductor layer. The dimensions of the portion can be defined, and the head portion of the gate electrode extending on the upper surface of the third semiconductor layer can be formed.

The material constituting the second, third and fourth semiconductor layers is GaAs, InGaAs, AlGaAs.
It may be two or three materials selected from the group consisting of s, InAlAs, InGaP and InP.

In this case, of the above-mentioned material group, the second and fourth semiconductor layers are made of a material having a high etching rate, and the third and fourth semiconductor layers are made of a material having a low etching rate.
Is formed. This makes it possible to increase the amount of side etching of the fourth semiconductor layer and the second semiconductor layer and decrease the amount of side etching of the third semiconductor layer when forming the concave portion.

An ohmic electrode may be formed on the fourth semiconductor layer opposed to the concave portion. In this case, the recess resistance reduces the source resistance and improves the gate breakdown voltage.

According to the method of manufacturing a field-effect semiconductor device according to the present invention, the second semiconductor layer, the third semiconductor layer having a smaller etching rate than the second semiconductor layer, are formed on the first semiconductor layer. Forming a fourth semiconductor layer having an etching rate higher than that of the third semiconductor layer in order, forming a mask pattern having a first opening on the fourth semiconductor layer; Etching the fourth semiconductor layer and the third semiconductor layer so that the second semiconductor layer is exposed through the first opening; and etching the mask pattern to form a second opening larger than the first opening. Forming a portion, etching the second semiconductor layer such that the first semiconductor layer is exposed through the second opening of the mask pattern, and forming a portion in the second opening of the mask pattern. It is obtained and forming a T-shaped gate electrode on a semiconductor layer.

In the method for manufacturing a field effect semiconductor device according to the present invention, a second semiconductor layer is formed on the first semiconductor layer.
A third semiconductor layer and a fourth semiconductor layer are sequentially formed.
The etching rates of the second semiconductor layer and the fourth semiconductor layer are higher than the etching rate of the third semiconductor layer.
Then, a mask pattern having a first opening is formed on the fourth semiconductor layer. The fourth semiconductor layer and the third semiconductor layer are etched so that the second semiconductor layer is exposed through the first opening of the mask pattern. As a result, a recess having a size corresponding to the first opening of the mask pattern is formed in the fourth semiconductor layer and the third semiconductor layer.

Next, the mask pattern is etched to form a second opening larger than the first opening. The second semiconductor layer is etched such that the first semiconductor layer is exposed through the second opening of the mask pattern. At this time, since the etching rates of the fourth semiconductor layer and the second semiconductor layer are higher than the etching rate of the third semiconductor layer, the fourth semiconductor layer in the recess is etched in the lateral direction and the second semiconductor layer is etched. The semiconductor layer is etched in the depth direction and the lateral direction. On the other hand, the third semiconductor layer
The third semiconductor layer is hardly etched since it has a smaller etching rate than the first and fourth semiconductor layers.

After that, a T-type gate electrode is formed on the first semiconductor layer in the second opening of the mask pattern. The size of the foot of the gate electrode is defined by the side surface of the third semiconductor layer in the recess, and the size of the umbrella of the gate electrode is defined by the second opening of the mask pattern. Further, a gap is formed between the side surface of the second semiconductor layer and the side surface of the foot of the gate electrode.

As described above, in the method for manufacturing a field-effect semiconductor device according to the present invention, since the recess structure is formed by the second, third and fourth semiconductor layers, the source resistance is reduced. , And the gate withstand voltage is improved. In addition, the gate resistance of the T-type gate electrode can reduce the gate resistance. Further, since a gap is formed below the umbrella portion of the gate electrode, the gate capacitance can be reduced. Therefore, the element characteristics are improved.

The size of the umbrella portion of the T-type gate electrode is defined by the size of the second opening of the mask pattern, and the T-type portion corresponding to the gate length is defined by the side surface of the third semiconductor layer in the recess. Of the gate electrode is self-aligned. Therefore, it is possible to form the T-type gate electrode with high accuracy and high yield.

The step of forming the gate electrode includes forming a conductive material on the mask pattern and on the first semiconductor layer in the second opening, and removing the conductive material on the mask pattern together with the mask pattern. And a step.

In this case, a T-type gate electrode is formed on the first semiconductor layer in the recess by the lift-off method.

The method for manufacturing a field-effect semiconductor device according to the present invention may further include a step of forming a pair of ohmic electrodes on the fourth semiconductor layer. In this case, the recess structure reduces source resistance and improves gate breakdown voltage.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a MESFET will be described as an example of a field-effect semiconductor device according to the present invention.

FIG. 1 is a schematic sectional view of an FET according to an embodiment of the present invention. In FIG. 1, an undoped GaAs buffer layer 2 having a thickness of 800 nm and an undoped In _0.2 Ga _0.8 As having a thickness of 10 nm are formed on a GaAs substrate 1.
Layer 3, 2 nm thick undoped Al _0.22 Ga _0.78 As
Layer 4, n-Al _0.22 Ga _0.78 As layer 5 having a thickness of 35 nm,
An n-GaAs layer 6 having a thickness of 20 nm, an undoped Al _0.22 Ga _0.78 As layer 7 having a thickness of 10 nm, and a thickness of 50 n
m n-GaAs layers 8 are sequentially stacked.

In this case, the n-type dopant is
Si is used and n-Al_0.22Ga _0.78Electrons in As layer 5
The concentration is 2 × 10¹⁸cm^-3And the n-GaAs layer 6 and
And the electron concentration of the n-GaAs layer 8 is 3 × 10¹⁸cm^-3In
You.

N-GaAs layer 8, Al _0.22 Ga _0.78 As
In the central region of the layer 7 and the n-GaAs layer 6, n-A
A recess (recess) is formed so that the l _0.22 Ga _0.78 As layer 5 is exposed.

Hereinafter, the n-GaAs layer 6 will be referred to as an n-GaAs layer.
Called 1 doped layer 6 and Al_0.22Ga _0.78As layer 7 is made of Al
_0.22Ga_0.78Called As side etching prevention layer 7, n
The -GaAs layer 8 is referred to as an n-GaAs second doped layer 8.

The etching rate of the Al _0.22 Ga _0.78 As side etching preventing layer 7 is smaller than the etching rates of the n-GaAs first doped layer 6 and the n-GaAs second doped layer 8.

A source electrode 9 and a drain electrode 10 are respectively formed on the pair of n-GaAs second doped layers 8 with the concave portion interposed therebetween. The source electrode 9 and the drain electrode 10 are in ohmic contact with the n-GaAs second doped layer 8. Further, the exposed n-Al _0.22 Ga _0.78
On the As layer 5, a T-type gate electrode 11 is formed. The T-type gate electrode 11 is in Schottky contact with the n-Al _0.22 Ga _0.78 As layer 5.

In the recess, the side surface of the n-GaAs first doped layer 6 and the foot (lower layer) 110 of the T-type gate electrode 11 are formed.
A gap 16 is formed between the side wall and the side wall. Also, A
sides of l _{0. 22} Ga _0.78 As side etching preventing layer 7 is in contact with the side surface of the foot portion 110 of the T-shaped gate electrode 11. Further, the side surface of the n-GaAs second doped layer 8 is separated from the side surface of the umbrella portion (upper layer) 111 of the T-type gate electrode 11, and the umbrella portion 111 extends to the upper surface of the Al _0.22 Ga _0.78 As side etching prevention layer 7. I have.

2 and 3 are schematic sectional views showing the steps of a method for manufacturing the FET shown in FIG. Hereinafter, FIGS. 2 and 3
The method of manufacturing the FET of this embodiment will be described with reference to FIG.

First, as shown in FIG.
On a substrate 1, a GaAs buffer layer 2, In _0.2 Ga _0.8
As layer 3, Al _0.22 Ga _0.78 As layer 4, n-Al _0.22 G
a _{0. 78} As layer 5, n-GaAs first doped layer 6, Al
_0.22 Ga _0.78 As side etching preventing layer 7 and n
-GaAs second doped layer 8 is epitaxially grown in order.

Next, a photoresist is formed in a predetermined region on the n-GaAs second doped layer 8, and etching is performed using a tartaric acid-based etchant to form a mesa pattern (trapezoidal pattern; not shown). . Thereafter, the photoresist is removed.

Subsequently, a photoresist having openings in the source electrode formation region and the drain electrode formation region on the n-GaAs second doped layer 8 is formed, and an AuGe film, Ni
The film and the Au film are sequentially vacuum-deposited, and the AuGe film, the Ni film and the Au film on the photoresist are removed together with the photoresist by a lift-off method, so that a source electrode 9 and a drain electrode 10 are formed. Next, the source electrode 9 and the drain electrode 10 are heat-treated at 400 ° C. for 2 minutes to perform alloying.

Next, as shown in FIG.
A photoresist 12 having an opening 13 with a width W1 is formed in the gate electrode formation region on the As
by RIE using a mixed gas of l ₂ and SF _6,
n-GaAs first doped layer 8 and Al _0.22 Ga _0.78 A
The s-side etching prevention layer 7 is etched. As the etching conditions, the flow rate of BCl ₂ was 20 sccm, the flow rate of SF ₆ was 10 sccm, and the pressure was 100 m.
Torr, high-frequency power is 75 W, and etching time is 30 seconds. In this case, n-GaAs second doped layer 8 and the Al _{0. 22} Ga _0.78 As side etching prevention layer 7 is etched in the depth direction.

In this embodiment, the width W1 of the opening 13 is set to 0.
5 μm. In this case, the size of the concave portion of the Al _0.22 Ga _0.78 As side etching preventing layer 7 defines the size of the foot of the T-type gate electrode formed in a later step.

Subsequently, as shown in FIG. 2C, the opening 13 of the photoresist 12 is enlarged by plasma etching using O ₂ to form an opening 13a having a width W2. In this embodiment, the etching amount is 0.6 μm.
Therefore, the width W2 of the opening 13a is 1.7 μm. The width W2 of the opening 13a of the photoresist defines the size of the head portion of the T-type gate electrode formed in a later step.

Next, as shown in FIG.
System etchant (citric acid: hydrogen peroxide = 2: 1)
And the n-GaAs second doped layer 8, Al_0.22Ga_0.78
As side etching preventing layer 7 and n-GaAs first layer
The doped layer 6 is etched. Etching time is 2 minutes
is there. In this case, the etching rate of GaAs is Al
_0.22Ga_0.78Larger than the etching rate of As,
GaAs and Al_0.22Ga _0.78Etching selectivity with As
Is about 100. Therefore, the n-GaAs second gate
Layer 8 and n-GaAs first doped layer 6 are in the depth direction.
Side etching
Is On the other hand, Al_0.22Ga_{0. 78}As side
The etching prevention layer 7 is hardly etched.

Subsequently, as shown in FIG. 3E, Al _0.22 Ga on the photoresist 12 and in the opening 13a is formed.
_The gate electrode layer 11a is formed on the _0.78 As layer 5 by vacuum-depositing a Ti film, a Pd film, and an Au film, and the gate electrode layer 1 on the photoresist 12 is formed by a lift-off method.
1a is removed together with the photoresist 12, and FIG.
A T-type gate electrode 11 as shown in FIG.

Here, the foot 110 of the T-type gate electrode 11
The dimension S1 not defined by the distance between the Al _0.22 Ga _0.78 As side etching prevention layer 7, in this embodiment 0.5μ
m. The dimension S2 of the umbrella portion 111 of the T-type gate electrode 11 is defined by the width W2 of the opening 13a of the photoresist 12, and is 1.7 μm in this embodiment.

In the FET of this embodiment, as shown in FIG. 1, the n-GaAs first doped layer 6, the Al _0.22 Ga
_0.78 As side etching preventing layer 7 and n-GaAs
Since the recess structure is formed by the second doped layer 8, reduction of the source resistance and improvement of the gate withstand voltage are achieved.
Further, the umbrella portion 111 of the T-type gate electrode 11 reduces the gate resistance. Further, since the n-GaAs first doped layer 6 does not exist below the umbrella portion 111 of the T-type gate electrode 11 and the air gap 16 is formed, the gate capacitance is reduced. Therefore, the element characteristics are improved.

The opening 13a of the photoresist 12
Of the umbrella portion 111 of the T-type gate electrode 11 is defined by the width W2 of the T-type gate electrode 11, and the size S1 of the foot portion 110 of the T-type gate electrode 11 is self-aligned by the Al _0.22 Ga _0.78 As side etching prevention layer 7. (Consistent). Dimension S1 of foot 110 of T-type gate electrode 11
Corresponds to the gate length. Therefore, the T-type gate electrode 1
1 can be formed with high accuracy and high yield.

The FET of the present embodiment shown in FIGS. 1 to 3 and the conventional FET shown in FIGS. 4 and 5 were manufactured, and the gate capacitance Cgs below the umbrella of the T-type gate electrodes 11 and 30 was measured. did. Table 1 shows the measurement results.

[0053]

[Table 1]

As shown in Table 1, in the FET of the present embodiment, the gate capacitance C
gs is reduced to about 10% of the gate capacitance Cgs below the umbrella of the gate electrode 30 of the conventional FET.

In the FET of the above embodiment, undoped Al _0.22 Ga _{0.78 is used} as the side etching prevention layer 7.
As layer is used, but lightly doped n-Al
_{A 0.22} Ga _0.78 As layer may be used.

In the FET of the above embodiment, the side etching amount of the second doped layer 8 is larger than the side etching amount of the first doped layer 6. The amount of side etching of the first doped layer 6 may be equal, or the amount of side etching of the second doped layer 8 may be smaller than the amount of side etching of the first doped layer 6.

In the above FET, GaAs / Al _0.22 Ga _0.78 As / GaAs is used as the material of the first doped layer 6 / side etching preventing layer 7 / second doped layer 8.
Although the combination of s is used, the combination of the materials of the first doped layer 6 / side etching preventing layer 7 / second doped layer 8 may be other than this. In this case, a combination in which the etching rates of the first doped layer 6 and the second doped layer 8 are higher than the etching rate of the side etching preventing layer 7 is selected. For example, GaAs, In _0.2
Ga _0.8 As, Al _0.22 Ga _0.78 As, In _0.49 Ga
Of the material group consisting of _0.51 P, In _0.52 Al _0.48 As and InP, a material having a large etching rate ratio between the first and second doped layers 6 and 8 and the side etching preventing layer 7, that is, a material having a large etching selectivity. May be combined. In this case, the first and second doped layers 6 and 8 are made of a material having a high etching rate, and the side etching preventing layer 7 is made of a material having a low etching rate. Table 2 shows the etching rates of these materials for citric acid-based etchants.

[0058]

[Table 2]

As shown in Table 2, the etching selectivity was large.
The combination of materials is, for example, GaAs and Al_0.22G
a_0.78As, GaAs and In_0.49Ga_0.51P, In_0.2
Ga _0.8As and Al_0.22Ga_0.78As, In_0.2Ga
_0.8As and In_0.52Al_0.48As and In_0.53Ga
_0.47As and InP.
The switching selectivity is 100, 400, 100, 1 respectively.
00 and 500.

First doped layer 6 formed on GaAs substrate
The combination of the material of the / side etching preventing layer 7 / the second doped layer 8 is GaAs / AlGaAs / GaAs or GaAs / InGaP / GaAs;
The material combination of the first doped layer 6 / side etching preventing layer 7 / second doped layer 8 formed on the substrate is InGa
As / InAlAs / InGaAs or InGaAs
In the case of / InP / InGaAs, there is no limitation on the thickness of each semiconductor layer because the substrate and each semiconductor layer are lattice-matched. Therefore, it is preferable to use such a material system as the material of the first doped layer 6 / side etching preventing layer 7 / second doped layer 8.

The material of the first doped layer 6 and the material of the second doped layer 8 may be different. For example, the material combination of the first doped layer 6 / side etching preventing layer 7 / second doped layer 8 is GaAs / AlGaAs / InGaAs.
It may be.

In the manufacturing method of the above-described embodiment, the first doped layer 6, the side etching preventing layer 7, and the second doped layer 8 are etched with a citric acid-based etchant. When the etching rate of 6, 8 is higher than the etching rate of the side etching preventing layer 7, another etchant may be used or dry etching may be used.

In the above embodiment, the case where the present invention is applied to an FET having a single hetero structure has been described. In addition to this, the present invention is also applicable to a double hetero structure or a TMT (Two-Mode channel Transistor). It is also possible to apply to a field effect type semiconductor device having a structure.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a method for manufacturing an FET according to an embodiment of the present invention.

FIG. 2 is a schematic process sectional view illustrating a method for manufacturing an FET according to an embodiment of the present invention.

FIG. 3 is a schematic process sectional view showing a method of manufacturing an FET according to an embodiment of the present invention.

FIG. 4 is a schematic process sectional view showing a conventional method for manufacturing an FET.

FIG. 5 is a schematic process sectional view showing a conventional method for manufacturing an FET.

[Explanation of symbols]

Reference Signs List 1 GaAs substrate 2 GaAs buffer layer 3 In _0.2 Ga _0.8 As layer 4 Al _0.22 Ga _0.78 As layer 5 n-Al _0.22 Ga _0.78 As layer 6 n-GaAs first doped layer 7 Al _0.22 Ga _0.78 As side etching preventing layer 8 n -GaAs second doped layer 9 Source electrode 10 Drain electrode 11 T-type gate electrode 110 Foot 111 Umbrella

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 21/306 H01L 21/306 B 21/308 S 29/778 29/80 HF term (reference) 4M104 AA04 AA05 BB11 BB14 CC01 CC03 DD08 DD10 DD34 DD68 DD78 FF07 FF27 FF28 GG12 5F004 AA03 BA04 BB13 DA11 DA18 DA26 DB19 DB20 DB21 DB26 EA09 EA10 EA17 EA23 EA28 EB02 5F043 AA14 BB07 DD15 DD20 FF01 G01 GM01 GN05 GN06 GN08 GQ01 GQ03 GR04 GR10 GS02 GS04 GT03 HB02 HB05 HB07 HC17 HC19

Claims (7)

[Claims] A second semiconductor layer, a third semiconductor layer, and a fourth semiconductor layer are sequentially formed on the first semiconductor layer, and the fourth semiconductor layer, the third semiconductor layer, and the 2
A concave portion is formed in the semiconductor layer so that the first semiconductor layer is exposed; a T-shaped gate electrode including an umbrella portion and a foot portion is formed on the first semiconductor layer in the concave portion; A gap is formed between the side surface of the second semiconductor layer and the side surface of the foot portion of the gate electrode, and the side surface of the third semiconductor layer is formed in the recess in the side surface of the foot portion of the gate electrode. A field-effect-type semiconductor device, wherein an umbrella portion of the gate electrode is in contact with and extends to an upper surface of the third semiconductor layer. 2. The field effect semiconductor device according to claim 1, wherein said second semiconductor layer and said fourth semiconductor layer have an etching rate higher than that of said third semiconductor layer. 3. The material forming the second, third and fourth semiconductor layers is GaAs, InGaAs, AlGaAs.
3. The field-effect semiconductor device according to claim 2, wherein the semiconductor device is two or three materials selected from the group consisting of s, InAlAs, InGaP, and InP. 4. The field-effect semiconductor device according to claim 1, wherein an ohmic electrode is formed on the fourth semiconductor layer opposed to the concave portion. 5. A second semiconductor layer, a third semiconductor layer having an etching rate lower than that of the second semiconductor layer, and an etching rate higher than that of the third semiconductor layer are formed on the first semiconductor layer. Forming a fourth semiconductor layer in order, forming a mask pattern having a first opening on the fourth semiconductor layer, and forming the second pattern through the first opening of the mask pattern. Etching the fourth semiconductor layer and the third semiconductor layer so that the first semiconductor layer is exposed; and etching the mask pattern to form a second opening larger than the first opening. And etching the second semiconductor layer so that the first semiconductor layer is exposed through the second opening of the mask pattern. Serial method for producing a field effect semiconductor device characterized by comprising a step of forming a T-shaped gate electrode on the second of said first semiconductor layer in the opening. 6. The step of forming the gate electrode includes: forming a conductive material on the mask pattern and on the first semiconductor layer in the second opening; and forming the conductive material on the mask pattern. 6. A method for manufacturing a field-effect semiconductor device according to claim 5, further comprising the step of removing a conductive material together with said mask pattern. 7. The method according to claim 5, further comprising the step of forming a pair of ohmic electrodes on the fourth semiconductor layer.