JPH07326631A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable formation of a T type gate electrode and a source-drain electrode in a manner of self-alignment by a method wherein a spacer to be a lower gate electrode region and an opening of the spacer to be a region of a visor are opened in the manner of self-alignment with each other. CONSTITUTION:A photoresist film 8 having an opening 81 is formed on the surface of a semiconductor substrate and an opening 71 having larger dimensions than the opening 81 is formed in a spacer 7. Next, an opening 51 being equal in dimensions to the opening 81 is formed in a part from a spacer 5 to the surface of the substrate. Insulating side-wall films 9 are formed on the lateral sides of the openings 71 and 51. A metal film 15 to be fitted on the substrate and to be a material of a gate is formed on the whole surface, a photoresist film 11 is provided on this metal film and the surface thereof is flattened. By etching back the photo-resist film 11 subsequently, the surface part other than the photoresist film 11 on a surface recession of the metal film 15 is exposed. This photoresist film 11 being used as a mask, the spacers 5 and 7 and others are removed sequentially so that the surface of the substrate be exposed, and metal electrodes 13S and 13D are fitted ohmically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect transistor (MES FET) having a Schottky junction type gate structure.

[0002]

2. Description of the Related Art In order to improve the characteristics of a field effect transistor, it is important to reduce the parasitic resistance between the gate electrode, the source electrode and the drain electrode, and the resistance of the gate electrode. is necessary. For this reason, various manufacturing methods for so-called mushroom type T-type gate electrode structures have been conventionally proposed.

FIG. 11 is a sectional view showing a method of manufacturing a conventional field effect transistor as disclosed in Japanese Patent Laid-Open No. 174374/1988 according to manufacturing steps.

First, in FIG. 11A, the semi-insulating G
A non-doped GaAs layer 22 having a thickness of about 0.5 to 1 μm on an aAs substrate 21, and an n-type AlGaAs layer 23 having a thickness of about 40 nm doped with silicon to a concentration of about 2 × 10 ¹⁸ cm ^−3.
And a thickness of 1 or more that is doped with silicon to the same extent or more.
The n-type GaAs layer 24 of about 20 μm is formed by MBE method or M
Epitaxial growth is sequentially performed by the OCVD method. Next, the first insulating film 26 having a thickness of 0.3 is formed on the n-type GaAs layer 24.
A silicon oxide film (SiO ₂ ) of about μm is deposited by the CVD method. Next, a resist mask 27 having an opening is formed on the first insulating film 26, and the first insulating film 26 is provided with an opening 26A for forming a gate region by, for example, a dry etching method using CF ₄ gas. To form. The opening dimension W ₁ of the opening 26A is, for example, 0.5 μm.

Next, in FIG. 11B, the recess structure 2 is formed by reactive ion etching (RIE) using the resist mask 27 and the first insulating film 26 as a mask.
4R is formed on the n-type GaAs layer 24.

Next, in FIG. 11C, after removing the resist mask 27, SiO ₂ is redeposited as a _second insulating film 28 on the entire surface of the wafer by a plasma CVD method or the like to fill the side-etched portion of the recess structure 24R. To do.

Next, referring to FIG. 11D, anisotropic RIE is performed.
By etching the second insulating film 28 to form the sidewall film 2
An opening having an opening size W ₂ of about 0.25 μm is formed so as to leave 8 A.

Next, in FIG. 11 (E), a photoresist mask 29 having an inverse tapered opening having an opening width W ₃ of about 1 μm is provided on the first insulating film 26, and, for example, titanium is used as a gate electrode metal. (Lower layer) / Platinum (Intermediate layer) /
Gold (upper layer) (Ti / Pt / Au) is deposited to a thickness of about 0.5 μm to form a lower layer gate electrode 30G.

Next, in FIG. 11F, the resist mask 29 is removed by a solvent to remove the gate metal material 30 on the resist mask 29 by lift-off, and then the first insulating film 26 is removed to form the lower gate electrode 30G. As a mask
Then, the first insulating film 26A is left only inside the lower gate electrode 30G. Next, in order to obtain an ohmic contact electrode, gold / germanium (lower layer) / nickel (intermediate layer) / gold (upper layer) (Au · Ge / Ni / A)
u) 25 is deposited and heat-treated to form ohmic-connected drain electrode 25D and source electrode 25S. At this time, AuGe / N is also formed on the lower layer gate electrode 30G.
i / Au is provided as the upper layer gate electrode 25G to obtain a conventional field effect transistor.

As described above, in this conventional example, since the source / drain electrodes are vapor-deposited using the gate electrode as a mask,
Since the source / drain electrode and the gate electrode can be formed close to each other in a self-aligned manner, the source parasitic resistance can be reduced. Moreover, the ohmic electrode metal 25G is also formed on the gate electrode 30G.
Thus, the gate resistance can be reduced at the same time. Further, since the sidewall film technique is used, a fine gate electrode pattern for Schottky junction can be obtained.

Next, a method of forming a mushroom type gate electrode by a conventional plating method as disclosed in Japanese Patent Laid-Open No. 61-8976 will be described in order of steps with reference to FIGS. 13 and 14.

In FIG. 13A, a first dielectric film 36 is provided on a GaAs wafer 31 having a surface operation layer,
An opening 37 is formed at the gate electrode formation position by photolithography.
And then a second dielectric film 38 is provided on the entire upper surface.

Next, in FIG. 13B, a sidewall film (side wall) is formed from the second dielectric film 38 by the RIE method.
38A is formed.

Next, in FIG. 13C, a plating base metal film 33 made of titanium, gold or the like is formed on the entire surface, a photoresist film 34 is provided leaving the gate electrode region, and then the base metal film 33 is formed as an electrode. As the electric field gold plating, a mushroom type gate electrode 35G is formed.

Next, referring to FIG. 13D, the first dielectric film 36, the sidewalls 38A, the photoresist film 34 and the underlying metal film 33 for plating are removed, and a mushroom having an underlying metal film 33G on the bottom surface is removed. The mold gate electrode 35G is completed.

In the manufacturing method according to this method, the gate parasitic resistance can be reduced by making the gate electrode a mushroom type by a gold plating method.

Also, using this mushroom type gate electrode as a mask, ohmic metal is vapor-deposited from the vertical direction of the substrate 31 to form the source electrode 37S and the drain electrode 37D in a self-aligned manner as shown in FIG. An upper electrode 37G can be formed on 35G.

[0018]

However, in the method of manufacturing the semiconductor device of the prior art shown in FIG. 11, the resist mask 29 and the first insulating film 26 are formed in the step of FIG. 11 (E) when forming the gate electrode 30G. However, at this time, a change in the gate electrode due to the pattern position shift of the resist mask 29 occurs due to the influence of the photolithography precision, as shown in FIG. That is, in FIG. 12, for example, the distance T ₁ shifted to the right in the figure from the distance T ₁ between the end of the gate region that is in Schottky contact with the n-type AlGaAs layer 23 and the end of the original gate electrode shown by the dotted line.
The end of the gate electrode is located at ₂ , which causes a difference ΔT between them. As a result, the distance between the gate and the source and the drain fluctuates, which causes a problem that the source resistance cannot be stably obtained.

Also in the prior art shown in FIGS. 13 and 14, the photoresist film 34 is used in the step of FIG.
However, there is a problem of misregistration caused by photolithography precision, and for example, as shown in FIG. The photoresist film 34 is not formed in the center of the opening 37 of the first insulating film 36 due to the shift in the direction, and the Au-plated gate electrode 35G is deformed. The source and drain electrodes 37S and 37D obtained by self-aligning by depositing ohmic metal using this as a mask are shown in FIG.
As shown in (B), a good source-gate distance cannot be obtained, which causes variation in the source resistance.

As described above, the conventional technique shown in FIG. 11 is also shown in FIG.
3, the prior art shown in FIG. 14 also has a common problem of misregistration in photolithography when forming the gate electrode, which is one of the major causes of reduction in production yield. Furthermore, if the gold plating is made thicker in order to reduce the gate resistance by using the method shown in FIGS. 13 and 14, the mushroom portion will inevitably increase. Therefore, when the ohmic metal is deposited using this as a mask and the source / drain electrodes are formed in a self-aligned manner, the distances between the gate and the source and between the gate and the drain are increased. Therefore, there is a problem that the parasitic resistance also increases.

In order to solve the above-mentioned problems, the object of the present invention is to obtain a novel T-type (mushroom type) gate electrode in a self-aligned manner and to form source / drain electrodes in a self-aligned manner. A method of manufacturing an effect transistor is provided.

[0022]

A feature of the present invention is that a first spacer, then a second spacer, and further a first spacer for providing a gate region are provided on a surface of a semiconductor substrate having a predetermined crystal structure. Forming a photoresist film having an opening; forming a second opening in the second spacer, the second opening having a size larger than that of the first opening; and forming the semiconductor substrate from the first spacer. Forming a third opening having a size equal to the size of the first opening over the surface of the first opening, removing the photoresist film, a side surface of the second opening and the third opening. Forming a side wall film of an insulating film on a side surface of the opening; forming a metal film to be a gate material on the entire surface of the semiconductor substrate exposed in the third opening; Hotrage as a flattening material on top A step of providing a photoresist film to planarize the surface, and etching back the photoresist film as the planarizing material to form a photoresist film on the surface recess of the metal film generated by the second and third openings. To expose the other surface portion of the metal film, and using the remaining photoresist film as a mask to expose the exposed metal film portion, the second spacer and the side surface of the second opening. A step of sequentially removing the sidewall film, and further removing a portion of the first spacer located under the sidewall film on the side surface of the second spacer and the second opening to expose the surface of the semiconductor substrate; A method of manufacturing a semiconductor device, which comprises a step of ohmic-connecting and depositing a metal electrode on the exposed surface of the semiconductor substrate. Here, a step of forming a metal film or an insulating film having an etching rate slower than the etching rate of the second spacer can be included between the first spacer and the second spacer. In addition, a conductive film that serves as a plating current path may be formed between the first spacer and the second spacer, and a plating process may be included in forming the metal film that serves as the gate material.

[0023]

According to the method of the present invention, in the gate electrode, a so-called T-shaped gate electrode is formed which is composed of a lower gate electrode portion which comes into contact with the semiconductor and a large portion having an eaves on the upper portion thereof. In a method of forming source / drain electrodes in a self-aligned manner by using, a first spacer having an opening serving as a lower gate electrode region and a second spacer having an opening serving as an eaves region are provided. Since the openings of the first and second spacers are opened in a self-aligned manner, the eaves formed on the left and right sides of the gate electrode are always equal in size to obtain a T-type gate electrode. For this reason,
By using this, the gate-source and gate-drain distances obtained in a self-aligned manner can be obtained uniformly, so that the source and drain resistances can always have stable characteristics.

[0024]

EXAMPLE Next, a first example of the manufacturing method according to the present invention will be described with reference to the sectional process drawings of FIGS.

In FIG. 1A, a compound semiconductor substrate is constructed by epitaxially growing a non-doped GaAs layer 2, an n-type AlGaAs layer 3 and an n ⁺ -type GaAs layer 4 on a semi-insulating GaAs substrate 1. A first spacer 5, for example, an insulating film SiO ₂ is grown on this compound semiconductor substrate to a film thickness of 200 nm by an ordinary method, for example, a vapor phase epitaxy method,
Further, as the second spacer 7, an insulating film having an etching rate faster than that of the first spacer, for example, a silicon nitride film SiN is grown to a film thickness of 700 nm by plasma vapor deposition, and then an opening for forming a gate region is formed. The photoresist film 8 is provided to form the portion (first opening) 81. Opening 8
The opening width W ₁ of ₁ is, for example, 500 nm. Here, a two-dimensional electron gas is formed near the heterojunction interface between the non-doped GaAs layer 2 and the n-type AlGaAs layer 3.

Next, in FIG. 1B, a film thickness of 700 nm is obtained by anisotropic reactive ion etching (RIE) using CF ₄ gas with the photoresist film 8 as a mask.
The SiN film of the second spacer 7 is opened by etching, and then isotropically etched by the RIE method to form an opening having a larger opening size than the opening 81 of the photoresist film 8 (second
Opening 71) is formed. The opening dimension W ₂ of the opening 71 is 900 nm, for example.

In FIG. 1C, the photoresist film 8 is formed by an ion milling method using argon gas with the photoresist film 8 as a mask and the first spacer 5 is anisotropic RIE method using CF ₄ gas. openings (first opening) aperture dimension W ₁ equivalent opening dimension W ₃ of 81 (50
0 nm) opening (upper part of the third opening) 51
Are formed by etching. After that, the n ⁺ -type GaAs layer 4 of the compound semiconductor substrate is subjected to RIE using CCl ₂ F ₂ gas.
By etching to form an opening portion (lower portion of the third opening portion) 41 having an opening size of 500 nm in the same manner.
The type AlGaAn layer 3 is exposed.

Next, in FIG. 2A, when the photoresist film 8 is removed with an organic solvent, the opening 41 of the n ⁺ -type GaAs layer 4 and the opening 51 of the first spacer 5 have an opening size 50.
At 0 nm, a stepped recess shape in which a T-shaped recess 71 having an opening size of 900 nm is formed in the second spacer 7 is obtained.

Next, in FIG. 2 (B), an insulating film, for example, a SiO ₂ film is grown to a thickness of 200 nm on the entire surface including the opening by a vapor phase growth method, and then R ₄ using CF ₄ gas is used.
The IE method, an SiO ₂ film of thickness 200nm by etching the n ⁺ -type GaAs layer 4, the side surface of the opening 41,51,71 of the first spacer 5 and the second spacer 7 by the SiO ₂ film Then, the sidewall film 9 is formed. Therefore, the opening 71 of the second spacer has an opening width of 500 nm, and the opening 51 of the first spacer and the n ⁺ -type GaA are formed.
The opening 41 of the s layer has an opening size of 100 nm.

Next, in FIG. 2C, first, as the base film material 14 of the gate metal material 10, for example, tungsten silicon alloy (WSi) having a thickness of 30 nm and a low resistance metal film 15 are formed as the base film material 14 of the gate metal material 10. , For example, gold (Au) is deposited by a 600 nm sputtering method. Next, a photoresist film 11 is applied on the entire surface to flatly fill the surface of the recess formed by the openings 41, 51 and 71.

Next, referring to FIG. 3A, the photoresist film 11 is etched back to extend the photoresist film 11A only in the recesses of the openings to expose the surface of the gate metal material 10 on the second spacer film 7. Next, the gate metal 10 is etched by an ion milling method to expose the surface of the second spacer 7. As a result, the gate electrode base film 14G formed of the base film 14 and forming the Schottky junction with the n-type AlGaAs layer 3 and the low-resistance metal film 15 are formed to form the gate electrode 10G from the gate electrode body 15G.

Next, in FIG. 3B, the second spacer 7, the side wall film 9 and the first spacer 5 connected to the second spacer 7 are etched by the anisotropic RIE method using CF ₄ gas using the gate electrode 10G as a mask. Then, the photoresist film 11A in the recess is removed with an organic solvent or O ₂ asher.
Here, the portion 5A of the first spacer below the gate electrode 10G remains.

Next, in FIG. 3 (C), gold / germanium (Au / Ge), which is an ohmic metal, is seen from the vertical direction of the gate.
The alloy is vacuum-deposited to have a thickness smaller than that of the first spacer 5, for example, 130 nm, and heat-treated to obtain source and drain electrodes 13S and 13D. The metal film 13G is formed.

The semiconductor device obtained as described above is
The gate electrode 10G is a T-type gate electrode in which the Au metal has a thickness of 600 nm, the ohmic metal 13G has a thickness of 130 nm, the upper portion has a length of 500 nm, and the lower portion has a length of 100 nm. The length between the gate and the source and between the gate and the drain is equal to the length of the upper portion of the gate minus the length of the lower portion, that is, the length of the eaves is 200 nm.

In the above embodiment, the case where the SiO ₂ film is used for the first spacer and the SiN film is used for the second spacer film has been described, but another insulating film such as SiON is used for the second spacer. A film may be used, and if the second spacer has sufficient etching selectivity with the gate metal material in the step of FIG. 3B, for example, polycide silicon (S
The object of the present invention can be achieved by using a metal film such as i) or aluminum (Al).

Next, a second embodiment of the manufacturing method according to the present invention will be described with reference to the sectional process drawings of FIGS.

In FIG. 4, a first spacer 5 such as SiO 2 is formed on a compound semiconductor substrate formed by epitaxially growing a non-doped GaAs layer 2, an n-type AlGaAs layer 3 and an n ⁺ GaAs layer 4 on a semi-insulating GaAs substrate 1.
_{(2) An} insulating film is grown to a thickness of 200 nm on the entire surface by a normal method such as vapor phase epitaxy, and aluminum (Al) metal is formed as a stopper 60 to a thickness of about 40 nm on the entire surface by a vapor deposition method or the like. As the second spacer 7, an insulating film, for example, a silicon oxide film (SiO ₂ ) 70
Grown by plasma vapor deposition to a film thickness of about 0 nm,
Next, a photoresist film 8 having an opening size of 500 nm and an opening portion 81 for forming a gate region is provided.

Next, in FIG. 4B, the SiO ₂ film 700 nm of the second spacer 7 is etched and opened by anisotropic RIE using CF ₄ gas with the photoresist film 8 as a mask to expose the surface of the stopper 60. Exposed. Next, by etching back by an isotropic RIE method, an opening size larger than the opening 81 of the photoresist film 8 is set to, for example, 900 nm.
An opening 71 is formed in the second spacer 7. At this time, since the etching rate of the stopper 60 is much slower than that of SiO _2, there is an advantage that the etching by the opening 71 does not affect the first spacer. Therefore, when the second spacer is opened, the opening 71 may be formed by overetching after the etching is continued after the anisotropic spacer RIE has the same size as the opening 81 of the photoresist film 8.

Next, in FIG. 4C, Al of the stopper 60 is opened by an ion milling method using Ar gas, and then the stopper 60 is used as a mask by an anisotropic RIE method using CF ₄ gas. The first spacer 5 has an opening 5
1 is formed to expose the surface of the n ⁺ -type GaAs layer 4 of the semiconductor substrate, and then the exposed n is formed using the first spacer as a mask.
^{The +} GaAa layer 4 is etched by an anisotropic RIE method using CCl ₂ F ₂ gas to form an opening 41, and the surface of the n-type AlGaAs layer 3 is exposed. Therefore,
The opening 51 of the first spacer 5 and the opening 41 of the n ⁺ -type GaAs layer 4 are opened to 500 nm which is the same size as the opening 81 of the photoresist film 8.

In this step, the stopper 60 is set to phosphoric acid (H
₃ PO ₄ ) may be used to form the opening portion 61 by etching so as to have the same size as the opening portion 71 of the second spacer 7.

Next, in FIG. 5A, the photoresist film 8 is removed with an organic solvent, and the stopper 60 exposed in the opening 71 is removed by etching with phosphoric acid to the same size as the opening 71 of the second spacer 7. To do. Therefore, the n ⁺ GaAs layer 4
The opening 41 of the first spacer 5 and the opening 51 of the first spacer 5 have an opening size of 500 nm, and the opening 71 of the second spacer 7 and the opening 61 of the stopper 60 have a opening size of 900 nm.

Next, in FIG. 5 (B), an insulating film, for example, a SiO ₂ film is grown to a thickness of 200 nm on the entire surface including the openings 41, 51, 61 and 71 by the vapor phase epitaxy method. This SiO ₂ film having a film thickness of 200 nm is etched by an anisotropic RIE method using CF ₄ gas to etch n ⁺ type Ga.
As layer 4, first spacer 5 and stopper 60, second
Sidewall films 9 are formed only on the side surfaces of the openings of the spacers 7, respectively. Therefore, the stopper 60 and the second spacer opening have an opening size of 500 nm, and the opening of the first spacer and the opening of the n ⁺ -type GaAs layer are 10 nm.
The opening size is 0 nm.

Next, in FIG. 5C, first, for example, tungsten-silicon alloy (WSi) 3 is formed as the base film 14 of the gate metal material 10 on the entire surface including the opening.
0 nm and a low resistance metal film 15, for example, gold (Au) 6
Then, the photoresist film 11 is applied to the entire surface, and the surface of the recess formed by the opening is flatly filled.

Next, in FIG. 6A, the photoresist film 11 is etched back by the RIE method using CF ₄ + O ₂ gas which is usually used, and the photoresist film 11A is left only in the concave portions of the openings to form the second spacer film. Of the gate metal film is exposed, and then the gate metal is etched by the ion milling method using Ar gas using the photoresist film of the recess as a mask to expose the surface of the second spacer 7, The ground electrode 14G and the gate electrode body 15G form the gate electrode 10G.

Next, in FIG. 6B, the second spacer and the side wall film connected to the second spacer are removed by etching using the gate electrode 10G as a mask by anisotropic RIE using CF ₄ gas, and then phosphoric acid is used. Then, the stopper 60 is removed by etching, and then the first spacer is etched by using the gate as a mask by the RIE method using CF ₄ gas to expose the surface of the n ⁺ -type GaAs layer 4 and the photoresist of the concave portion. The film is removed with an organic solvent or O ₂ asher.

Next, in FIG. 6C, an ohmic metal of gold / germanium (Au / Ge) is seen from the vertical direction of the gate.
Alloy (lower layer) / Nickel (Ni) (intermediate layer) / Gold (A
u) (upper layer) is deposited by a vacuum deposition method to a thickness smaller than that of the first spacer, for example, 130 nm, and heat-treated to obtain source and drain electrodes 13S and 13D, and an alloy film 13G on the gate electrode. To get

The semiconductor device obtained as described above is
The gate 10 is provided with Au metal having a thickness of 600 nm and ohmic metal having a thickness of 130 nm, and has an upper length of 50 nm.
A T-type gate electrode having a length of 0 nm and a lower gate electrode portion of 100 nm is obtained. Then, between the gate and the source and between the gate and the drain, the length of the upper part of the gate minus the length of the lower part, that is, the length of the eaves, is uniformly formed to be 200 nm.

Further, according to the second embodiment of the present invention, the stopper 60 is provided in the second spacer 7 shown in FIG. The influence can be prevented. Therefore, there is no restriction on the etching selectivity of the first spacer 5 and the second spacer 7. That is, for example, SiN having a high etching rate may be used for the first spacer and SiO ₂ having a low etching rate may be used for the second spacer, and a material having an equivalent etching rate, for example, SiO ₂ may be used as the first spacer. Can also be used as the spacer and the second spacer.

Although the explanation has been given for the case where the Al metal is used as the stopper 60 of this embodiment, the etching selectivity with the second spacer is used as the stopper in either the dry etching or the wet etching. If sufficient, it can be used regardless of metal or insulator.

Next, a third embodiment of the manufacturing method according to the present invention will be described with reference to the sectional process drawings of FIGS.

In FIG. 7A, a first spacer 5, for example, an insulating layer, is formed on a compound semiconductor substrate obtained by epitaxially growing a non-doped GaAs layer 2, an n-type AlGaAs layer 3 and an n ⁺ GaAs layer 4 on a semi-insulating GaAs substrate 1. Membrane S
io ₂ is added to a conventional method, for example, 200 n by vapor phase epitaxy.
Then, titanium (Ti) (lower layer) / gold (Au) (upper layer), for example, is formed as a conductor film 6 for plating by a sputtering method to a thickness of about 100 nm. Insulating film having an etching rate faster than that of the spacer, for example, a nitride film SiN having a film thickness of 700 nm
Is grown by plasma vapor deposition, and then a photoresist film 8 having an opening 81 of, for example, 500 nm for forming a gate region is provided.

Next, in FIG. 7B, the SiN film of the second spacer 7 is etched until the plating conductor film 6 is exposed by anisotropic RIE using CF ₄ gas with the photoresist film 8 as a mask. Then, the etching is further continued to form an opening 71 having an opening size of 900 nm, which is larger than the size of the opening 81 of the photoresist film 8.

Next, in FIG. 7C, the plating conductor film 6 is etched and removed by an ion milling method using Ar gas by using the photoresist film 8 as a mask to expose the first spacers 5, and then CF. Anisotropic RIE using ₄ gases
By using the photoresist film 8 as a mask, the first spacer 5 is etched to have an opening size equal to the opening size of the photoresist film 8 to form an opening 51, and the n ⁺ -type Ga of the semiconductor substrate is formed.
The surface of the As layer 4 is exposed. That is, the opening has a size of 500 nm.

Next, in FIG. 8A, after removing the photoresist film 8 with an organic solvent, the first spacer 5 is used as a mask to anisotropy the n ⁺ -type GaAs layer 4 with CCl ₂ F ₂ gas. The n-type AlGaAs layer 3 is exposed by etching and removing the opening 41 by the RIE method. Therefore n ⁺
The opening 41 of the type GaAs layer 4, the opening 51 of the first spacer 5 and the opening 61 of the plating conductor film 6 are 500 n.
The opening size of the second spacer 7 is 900 nm, and the opening size of the second spacer 7 is 900 nm.

Next, in FIG. 8B, an insulating film 9 to be a side wall film is formed of, for example, a SiO ₂ film of 200 n by a vapor deposition method.
The entire thickness including the opening is grown to a thickness of m.

Next, in FIG. 8C, S which becomes a sidewall film is formed.
The iO ₂ film is etched by anisotropic RIE using CF ₄ gas from the direction perpendicular to the opening until the n-type AlGaAs layer 3 is exposed, and the SiO ₂ film is formed only on the side surfaces of the openings 41, 51, 61, 71. Then, the sidewall films 9 are formed, respectively. Therefore, the opening 41 of the n ⁺ type GaAs layer 4, the opening 51 of the first spacer 5 and the opening 61 of the conductor film for plating are 500 nm, and the opening 71 of the second spacer 7 is 900 nm. It is formed.

Next, in FIG. 9A, first, for example, a tungsten-silicon alloy (WSi) is deposited on the entire surface including the opening as the metal of the gate electrode base film material 14.
0 nm Further, if necessary, gold (Au) is formed by a 30 nm sputtering method for the purpose of facilitating plating deposition, and a photoresist film 11 is applied on the entire surface to form openings 41, 5
The recesses formed by 1, 61 and 71 are filled flat.

Next, in FIG. 9B, the photoresist film 11 is etched back to extend the photoresist film 11 only in the recesses on the openings to expose the surface of the Schottky metal material 14 on the second spacer film. Then, the second spacer 7 is etched by ion milling or RIE until the surface of the second spacer 7 is exposed, and then the photoresist film 11 in the recess is removed by using a solvent. Here, the Schottky junction gate electrode base film 14G is formed.

Next, referring to FIG. 9C, the gate metal base film 14G is formed through the plating conductor film 6 by electroplating.
An Au plating 12 having a film thickness of 600 nm is formed on the gate electrode 10G.

Next, in FIG. 10A, the gate electrode 1
The second spacer 7 and the sidewall film 9 connected to the second spacer 7 are removed by etching by RIE using 0 G as a mask. At this time, a wet etching method using hydrofluoric acid (HF) may be used. Next, the plating conductor film 6 is removed by etching by the ion milling method, and then the first spacer film 5 is removed by etching by the anisotropic RIE method to expose the surface of the n ⁺ GaAs layer.

Next, referring to FIG. 10B, the gold / germanium (Au.Ge) alloy (lower layer) / Ni (intermediate layer) / A, which is an ohmic metal, is seen from the vertical direction of the gate plating Au12.
u (upper layer) is deposited by vacuum vapor deposition to a thickness smaller than that of the first spacer, for example, 130 nm, and heat-treated to obtain source and drain electrodes 13S and 13G. This metal film is used as the gate electrode 10G. An upper film 13G is deposited on top.

The gate of the semiconductor device obtained as described above has an upper length of 500 nm, a lower gate electrode portion has a length of 100 nm, and low resistance gold (Au) is thickly plated. As a result, a T-shaped gate electrode coated with is obtained. And the gate source and gate
Between the drains, the length of the upper part of the gate-the length of the lower part, that is, 20
It is uniformly formed at 0 nm.

[0063]

As described above, the present invention comprises the first spacer having the opening serving as the lower gate electrode region and the second spacer having the opening serving as the eave region. Since the openings of the second spacers are opened in a self-aligned manner with each other, a T-shaped gate electrode having a size that is always equal to the eaves formed on the left and right of the gate electrode can be obtained. For this reason, the gate-source and gate-drain distances obtained in a self-aligned manner by using this can be obtained uniformly, so that the source and drain resistances can always have stable characteristics.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention in process order.

2A to 2C are cross-sectional views sequentially showing a step following that of FIG.

3A to 3D are cross-sectional views sequentially showing a step that follows FIG.

FIG. 4 is a sectional view showing a second embodiment of the present invention in process order.

5A to 5C are cross-sectional views sequentially showing a step following that of FIG.

6A to 6C are cross-sectional views sequentially showing a step following that of FIG.

FIG. 7 is a cross-sectional view showing the third embodiment of the present invention in the order of steps.

8A and 8B are cross-sectional views sequentially showing a step following that of FIG.

9A to 9C are cross-sectional views sequentially showing a step following that of FIG.

10A to 10D are cross-sectional views sequentially showing a step following the step of FIG.

FIG. 11 is a cross-sectional view showing a conventional technique in order of steps.

FIG. 12 is a cross-sectional view illustrating the problem of the conventional technique of FIG.

FIG. 13 is a cross-sectional view showing another conventional technique in the order of steps.

14 is a cross-sectional view showing the field effect transistor obtained in FIG.

FIG. 15 is a cross-sectional view illustrating the problem of the conventional technique of FIG.

[Explanation of symbols]

1, 21 Semi-insulating GaAs substrate 2, 22 Non-doped GaAs layer 3, 23 n-type AlGaAs layer 4, 24 n ⁺ type (n-type) GaAs layer 5 First spacer 6 Conductive film for plating 7 Second spacer 8, 11, 27, 29, 34 Photoresist film 9, 28A, 38A Side wall film 10 Gate electrode material 10G, 35G Gate electrode 13G Alloy film on gate electrode 13S Source electrode 13D Drain electrode 14 Underlayer film 14G Gate electrode Underlayer film 15 Low resistance metal Film 15G Gate electrode body 21 Semi-insulating 24R recess structure 25 Ohmic contact film 26, 28 Insulating film 30 Gate metal material 30G Lower layer gate electrode 31 GaAs wafer 33G Base metal film 36, 38 Dielectric film 37, 41, 51, 61, 71,81 Opening 60 Stopper

Claims (3)

[Claims] 1. A first spacer, then a second spacer, and a photoresist film having a first opening for providing a gate region are formed on the surface of a semiconductor substrate having a predetermined crystal structure. A step of forming a second opening larger than the size of the first opening in the second spacer, and the first opening from the first spacer to the surface portion of the semiconductor substrate. Forming a third opening having the same size as the above-mentioned dimension, removing the photoresist film, a side surface of the second opening and the third opening.
Forming a side wall film of an insulating film on the side surface of the opening of the semiconductor substrate, forming a metal film to be a gate material on the entire surface of the semiconductor substrate exposed in the third opening, A step of providing a photoresist film as a planarizing material on the film to planarize the surface; and etching back the photoresist film as the planarizing material to form the second and third layers.
Of leaving the photoresist film on the surface concave portion of the metal film caused by the opening of the metal film and exposing the other surface portion of the metal film, and using the remaining photoresist film as a mask to form the exposed metal film. The portion, the second spacer and the side wall film on the side surface of the second opening are sequentially removed,
Further, the step of exposing the surface of the semiconductor substrate by removing the location of the first spacer located under the sidewall film on the side surface of the second spacer and the second opening, and the exposed surface of the semiconductor substrate. And a step of depositing a metal electrode by ohmic connection. 2. A step of forming, between the first spacer and the second spacer, a metal film or an insulating film having an etching rate lower than that of the second spacer. The method for manufacturing a semiconductor device according to claim 1. 3. A conductive film serving as a plating current path is formed between the first spacer and the second spacer, and a metal film serving as the gate material is formed by a plating process. The method of manufacturing a semiconductor device according to claim 1.